Prosecution Insights
Last updated: April 18, 2026
Application No. 18/883,156

PRE-DISTORTION TRAINING FEEDBACK VIA INDUCTIVE COUPLING

Final Rejection §102§103§112
Filed
Sep 12, 2024
Examiner
TSE, YOUNG TOI
Art Unit
2632
Tech Center
2600 — Communications
Assignee
Qualcomm Incorporated
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
2y 7m
To Grant
98%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
889 granted / 998 resolved
+27.1% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
33 currently pending
Career history
1031
Total Applications
across all art units

Statute-Specific Performance

§101
4.7%
-35.3% vs TC avg
§103
20.0%
-20.0% vs TC avg
§102
17.4%
-22.6% vs TC avg
§112
47.6%
+7.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 998 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Response to Arguments Applicant’s arguments, see page 1 of the remarks, filed on March 23, 2026, with respect to the objections to the specification have been fully considered and are persuasive. The objection of the specification has been withdrawn. Applicant’s arguments, see page 1 of the remarks, filed on March 23, 2026, with respect to the claim objections have been fully considered and are persuasive. The objection of claims 2-10, 12, and 14 has been withdrawn. Claims 2, 4, and 15 have been canceled. Applicant's arguments filed on March 23, 2026 have been fully considered but they are not persuasive. Regarding the rejections of claims 1-6 and 8-20 rejected under 35 U.S.C. §102(a)(2), Applicant’s arguments on pages 1-3 of the remarks have been fully considered by the examiner, however, the examiner respectfully disagreed with the Applicant’s arguments. At page 2 of the remarks, Applicant argued that Panseri fails to disclose “a receive path comprising a first inductive element that includes an inductor; a transmit path comprising a first amplifier and a second inductive element coupled to a first output of the first amplifier, wherein the first inductive element is inductively coupled to the second inductive element; ... one or more processors coupled to the one or more memories, the receive path, and the transmit path, wherein the one or more processors are configured to cause the apparatus to: obtain a first signal, based on a second signal output by the first amplifier, via the first inductive element being inductively coupled to the second inductive element,” as recited in amended claim 1 and similarly recited in amended claims 13 and 20 (emphasis added). At pages 2 and 3 of the remarks, Applicant mainly argued that each of the attenuator 360 shown in Panseri’s Figure 3 and the capacitor attenuator 454 shown in Panseri’s Figure 4A is not an inductive element that includes an inductor. An attenuator that incorporates an inductor is considered an inductive element or, more precisely, a reactive attenuator. Based on Applicant’s arguments, even the attenuator 360 shown in Figure 3 and the capacitor attenuator 454 shown in Figure 4A are not considered as the first inductive element that includes an inductor, the amended independent claim 1 and the similarly amended independent claims 13 and 20 are not patentable over Panseri. As shown in Figure 3, the wireless transceiver 300 further comprises another path (which includes a matching network 350, an inductor L1, and a variable resistive element R1) coupled between the output of the second conductive element (transformer 345) in the transmit path and the input of the LNA 370 in the receive path. For example, a matching network is frequently designed using inductive elements (inductors) to transform impedance, particularly in LC networks like L, Pi, or T-networks. It is considered a network of reactive components, which includes inductors (storing energy) and capacitors, rather than resistors. Clearly, either the matching network 350 or the inductor L1 may consider as the first inductive element that includes an inductor being inductively coupled to the second inductive element (transformer 345). Therefore, the rejections of claim 1 and the similarity claim features of claims 13 and 20, including the dependent claims 3, 5-8, 14, 18, and 19 are proper and remain rejected under 35 U.S.C. 102(a)(2) over Panseri for at least the reasons described above. For further consideration, the rejections of claims 9-10 and 16-17 have been withdrawn. Claims 2, 4, and 15 have been canceled. See detailed rejections below. Claim Objections Claims 1, 3, 5-12, 16, 17, 19, and 20 are objected to because of the following informalities: 1. (Proposed Amendment) An apparatus configured for wireless communications, comprising: a receive path comprising a first inductive element that includes an inductor: a transmit path comprising a first amplifier and a second inductive element coupled to an output of the first amplifier, wherein the first inductive element is inductively coupled to the second inductive element; one or more memories; and one or more processors coupled to the one or more memories, the receive path, and the transmit path, wherein the one or more processors are configured to cause the apparatus to: obtain a first signal, based on a second signal output by the first amplifier, via the first inductive element being inductively coupled to the second inductive element; determine one or more parameters for digital pre-distortion (DPD) associated with the first amplifier based at least in part on the first signal; pre-distort a third signal based at least in part on the one or more parameters; amplify the pre-distorted third signal via the first amplifier; and transmit the amplified third signal. 5. (Proposed Amendment) The apparatus of claim 1, wherein the receive path further comprises a second amplifier having an output coupled to the first inductive element. 7. (Proposed Amendment) The apparatus of claim 6, wherein the variable resistive element comprises a resistor bank comprising a plurality of branches arranged in parallel, wherein each of the plurality of branches comprises a resistive element and a switch coupled in series with the resistive element. 9. (Proposed Amendment) The apparatus of claim 6, wherein the receive path further comprises: a second amplifier having an output coupled to the first inductive element; and one or more mixers, wherein the first inductive element and the variable resistive element are coupled between the one or more mixers and the 16. (Proposed Amendment) The apparatus of claim 13, wherein the receive path further comprises: a second amplifier having an output coupled to the first inductive element; and one or more mixers, wherein the first inductive element and the variable resistive element are coupled between the one or more mixers and the output of the second amplifier. 19. (Proposed Amendment) The apparatus of claim 13, wherein the variable resistive element comprises a resistor bank comprising a plurality of branches arranged in parallel, wherein each of the plurality of branches comprises a resistive element and a switch coupled in series with the resistive element. 20. (Proposed Amendment) A method for wireless communications by an apparatus, comprising: obtaining a first signal, based on a second signal output by an amplifier of a transmit path, via a first inductive element of a receive path being inductively coupled to a second inductive element of the transmit path, wherein the first inductive element includes an inductor, and wherein the second inductive element is coupled to an output of the determining one or more parameters for digital pre-distortion (DPD) associated with the pre-distorting a third signal based at least in part on the one or more parameters; amplifying the pre-distorted third signal via the transmitting the amplified third signal. Claims 3, 6, 8, and 10-12 depend either directly or indirectly from claim 1, therefore they are also objected. Claim 17 depends from claim 16, therefore it is also objected. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 16 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 16 recites the limitation “the amplifier” in line 5. There is insufficient antecedent basis for this limitation in the claim because it is unclear the amplifier references to the first amplifier recited in the precedent claim 13 or the second amplifier recited in claim 16. It appears the amplifier is referenced to the second amplifier. Claim 17 depends from claim 16, therefore it is also rejected. Claim Rejections - 35 USC § 102 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1, 3, 5, 6, 8, 11-14, and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by PANSERI et al. (US 2021/0399690 A1), hereinafter “Panseri”. Panseri illustrates a wireless transceiver (300) in Figure 3 including the details of the distortion characterization circuit (395) and the adaptive distortion circuit (310) illustrated in Figure 3. Regarding claim 1, as shown in Figure 3, an apparatus (wireless transceiver 300) configured for wireless communications, comprising: a receive path (bottom section of the wireless transceiver 300, paragraph [0042]) comprising a first inductive element that includes an inductor (matching network 350 or inductor L1); a transmit path (top section of the wireless transceiver 300, paragraph [0042]) comprising a first amplifier (PA 340) and a second inductive element (transformer 345) coupled to an output of the first amplifier (PA 340), wherein the first inductive element (matching network 350 or inductor L1) is inductively coupled to the second inductive element (transformer 345); one or more memories (distortion characterization circuit 395 and ADPD LUT 312, a lookup table (LUT) is fundamentally a form of small, fast memory, especially in FPGAs where they act as “distributed RAM,” storing precomputed values to implement complex logic or functions quickly by looking up results instead of calculating them); and one or more processors (control circuit 315 or DSP 110 of Figure 1) coupled to the one or more memories, the receive path, and the transmit path, wherein the one or more processors are configured to cause the apparatus to: obtain a first signal (feedback signals Iout and Qout of the receive path), based on a second signal output by the first amplifier (PA 340), via the first inductive element (matching network 350 or inductor L1) being inductively coupled to the output of the first amplifier (PA 340); determine one or more parameters (amplitude and phase pre-distortion signals generated by the adaptive pre-distortion LUT circuits 412 and 414 of Figure 4) for digital pre-distortion (DPD) associated with the first amplifier based at least in part on the first signal; pre-distort a third signal (by the distortion characterization circuit 395) based at least in part on the one or more parameters; amplify the pre-distorted third signal via the first amplifier (PA 340); and transmit the amplified third signal. Regarding claim 3, as shown in Figure 3, wherein the first inductive element comprises a transformer (transformer 345). Regarding claim 5, as shown in Figure 3, wherein the receive path further comprises a second amplifier (LNA 370) having an output coupled to the first inductive element (matching network 350 or inductor L1). Regarding claim 6, as shown in Figure 3, wherein the receive path further comprises a variable resistive element (R1) coupled to the second inductive element (matching network 350 or inductor L1), wherein the variable resistive element is configured to adjust an attenuation applied to the first signal via a variable resistance of the variable resistive element (a variable resistive element, such as R1, is inherently used to adjust attenuation, forming the core of many attenuators, especially resistive pads and potentiometers, by changing resistance to control signal strength (voltage/current) continuously or in steps, acting as a voltage divider to reduce signal power without distortion. The resistance change effectively modifies the gain (or loss) of the circuit, making it fundamental for attenuation control in various applications, also see paragraph [0047]). Regarding claim 8, as shown in Figure 3, wherein the one or more processors are configured to cause the apparatus to adjust the attenuation applied to the first signal via the variable resistive element (R1). Regarding claim 11, as shown in Figure 3, wherein to determine the one or more parameters, the one or more processors are inherently to cause the apparatus to determine the one or more parameters for the DPD based at least in part on a comparison between the first signal and a DPD training signal (since the comparison is fundamental to the DPD training process. The primary goal of DPD is to linearize the power amplifier (PA), such as the PA 340, which introduces nonlinear distortion. To achieve this, the DPD system must first characterize the amplifier's nonlinear behavior. This characterization, or training, is typically an adaptive process that involves a comparison. For example, Training Signal: An ideal or undistorted input signal is applied to the PA. Comparison Point: The resulting actual output signal from the PA is captured using a feedback loop (which includes an ADC, such as the ADC 390) and compared to a reference signal, which often is (or is derived from) the original ideal input signal (the “wanted output signal”). Parameter Adjustment: An error signal is generated based on the difference between the actual output and the ideal/reference signal. This error signal is then used by an adaptive algorithm (such as Least Mean Squares (LMS) or Recursive Least Squares (RLS)) to estimate or update the DPD model's parameters (e.g., coefficients of a memory polynomial model or values in a look-up table). This comparison process allows the DPD to create an inverse model of the PA's nonlinearity, ensuring that when the pre-distorted signal is transmitted, the PA's output is as close to the ideal, linear signal as possible). Regarding claim 12, as shown in Figure 3, wherein the one or more parameters comprises one or more of: one or more pre-distortion coefficients; an amplitude-to-phase modulation (AM-PM) conversion associated with the first amplifier; or an amplitude-to-amplitude modulation (AM-AM) conversion associated with the first amplifier (paragraph [0040]). Regarding claim 13, as shown in Figure 3, Panseri illustrates an apparatus (wireless transceiver 300) configured for wireless communications, comprising: a receive path (bottom section of the wireless transceiver 300, paragraph [0042]) comprising a variable resistive element (R1) and a first inductive element that includes an inductor (matching network 350 or inductor L1); a transmit path (top section of the wireless transceiver 300, paragraph [0042]) comprising a first amplifier (PA 340) and a second inductive element (transformer 345) coupled to an output of the first amplifier (PA 340), wherein the second inductive element (matching network 350 or inductor L1) is arranged to be inductively coupled to the first inductive element (transformer 345); one or more memories (distortion characterization circuit 395 and ADPD LUT 312, a lookup table (LUT) is fundamentally a form of small, fast memory, especially in FPGAs where they act as “distributed RAM,” storing precomputed values to implement complex logic or functions quickly by looking up results instead of calculating them); and one or more processors (control circuit 315 or DSP 110 of Figure 1) coupled to the one or more memories and the receive path, wherein the one or more processors are configured to cause the apparatus to: determine one or more parameters (amplitude and phase pre-distortion signals generated by the adaptive pre-distortion LUT circuits 412 and 414 of Figure 4) for digital pre-distortion (DPD) associated with the first amplifier based at least in part on the first signal; pre-distort a third signal (by the distortion characterization circuit 395) for distortion compensation based on a first signal (feedback signals Iout and Qout of the receive path) inductively received at the receive path, via the first inductive element (transformer 345) being inductively coupled to the second inductive element (matching network 350 or inductor L1), during a first mode(transmission mode or training mode); and adjust a first attenuation (attenuation of R1), applied to the inductively received first signal, via a variable resistance of the variable resistive element based on the first mode. Regarding claim 14, as shown in Figure 3, wherein the one or more processors are configured to cause the apparatus to adjust a second attenuation (attenuator 360 or after the feedback loop of R1) applied to a second signal obtained via the receive path based on a second mode (transmission or reception mode). Regarding claim 18, as shown in Figure 3 and described in claim 11 above, wherein to determine the one or more parameters, the one or more processors are inherently to cause the apparatus to determine the one or more parameters for the DPD based at least in part on a comparison between the first signal and a DPD training signal (since the comparison is fundamental to the DPD training process. The primary goal of DPD is to linearize the power amplifier (PA), such as the PA 340, which introduces nonlinear distortion. To achieve this, the DPD system must first characterize the amplifier's nonlinear behavior. This characterization, or training, is typically an adaptive process that involves a comparison. For example, Training Signal: An ideal or undistorted input signal is applied to the PA. Comparison Point: The resulting actual output signal from the PA is captured using a feedback loop (which includes an ADC, such as the ADC 390) and compared to a reference signal, which often is (or is derived from) the original ideal input signal (the “wanted output signal”). Parameter Adjustment: An error signal is generated based on the difference between the actual output and the ideal/reference signal. This error signal is then used by an adaptive algorithm (such as Least Mean Squares (LMS) or Recursive Least Squares (RLS)) to estimate or update the DPD model's parameters (e.g., coefficients of a memory polynomial model or values in a look-up table). This comparison process allows the DPD to create an inverse model of the PA's nonlinearity, ensuring that when the pre-distorted signal is transmitted, the PA's output is as close to the ideal, linear signal as possible). Regarding claim 19, as shown in Figure 3, wherein the one or more parameters comprises one or more of: one or more pre-distortion coefficients; an amplitude-to-phase modulation (AM-PM) conversion associated with the first amplifier; or an amplitude-to-amplitude modulation (AM-AM) conversion associated with the first amplifier (paragraph [0040]). Regarding claim 20, claim 20 is a method claim which recites claim features in the method steps similar to the claim features recited in the apparatus claim 1 for the similar reasons described in claim 1 above. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Panseri in view of Ryu et al. (US 2021/0320646 A1), hereinafter “Ryu”. Regarding claim 7, as applied to claims 1 and 6 described above, although Panseri does not explicitly show or teach that a variable resistive element comprises a resistor bank including the features of resistors and switches recited in claim 7, it appears well-known in the art that a variable resistive element can be implemented using a resistor bank consisting of a plurality of branches arranged in parallel, where each branch comprises a resistive element and a switch coupled in series. For example, Ryu illustrates a digitally controllable resistor bank (670) in Figure 6A that includes a set of digitally controllable switches (672) (e.g., T-type series transistors) and resistors that are connectable in series via a respective switch. As shown in Figure 6A, a first row of the digitally controllable resistor bank (670) includes a first resistor, a switch, and a second resistor; a second row of the digitally controllable resistor bank includes a first resistor, a switch, and a second resistor; and an N-th row of the digitally controllable resistor bank includes a first resistor, a switch, and a second resistor (paragraph [0069]). Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art as taught by Tyu to implement Panseri’s variable resistive element (R1) with a resistor bank similar to Ryu’s resistor bank (670) to include a plurality of branches arranged in parallel, wherein each of the plurality of branches comprises a resistive element and a switch coupled in series in order to digitally controlled or switched resistor banks by selectively opening or closing the switches in each parallel branch to create controlled electrical loads to test and verify power systems by converting excess electricity into heat, ensuring they perform reliably under real-world stress, preventing damage, and helping manage renewable energy fluctuations by dissipating surplus power. Allowable Subject Matter Claims 9-10 and 16-17 would be allowable if rewritten to overcome the objection(s) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Claims 16 and 17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Young T. Tse whose telephone number is (571)272-3051. The examiner can normally be reached Mon-Fri 10:30am-7pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh M Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Young T. Tse/Primary Examiner, Art Unit 2632
Read full office action

Prosecution Timeline

Sep 12, 2024
Application Filed
Dec 13, 2025
Non-Final Rejection — §102, §103, §112
Feb 17, 2026
Interview Requested
Feb 24, 2026
Applicant Interview (Telephonic)
Feb 24, 2026
Examiner Interview Summary
Mar 23, 2026
Response Filed
Apr 05, 2026
Final Rejection — §102, §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
98%
With Interview (+8.6%)
2y 7m
Median Time to Grant
Moderate
PTA Risk
Based on 998 resolved cases by this examiner. Grant probability derived from career allow rate.

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