Prosecution Insights
Last updated: August 17, 2026
Application No. 18/883,172

MINIMIZING EFFECTS OF CACHE THRASHING BY ALTERING A PERSISTENCE POLICY FOR NON-TEMPORAL WORKLOADS

Final Rejection §102§103
Filed
Sep 12, 2024
Examiner
OTTO, ALAN
Art Unit
2132
Tech Center
2100 — Computer Architecture & Software
Assignee
International Business Machines Corporation
OA Round
2 (Final)
66%
Grant Probability
Favorable
3-4
OA Rounds
1y 6m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allowance Rate
247 granted / 372 resolved
+11.4% vs TC avg
Strong +18% interview lift
Without
With
+18.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
14 currently pending
Career history
392
Total Applications
across all art units

Statute-Specific Performance

§101
6.6%
-33.4% vs TC avg
§103
52.8%
+12.8% vs TC avg
§102
22.0%
-18.0% vs TC avg
§112
13.3%
-26.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 372 resolved cases

Office Action

§102 §103
Detailed Action The instant application having Application No. 18,883,172 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the arguments filed 3/23/26. Claims 1-25 are pending. NOTICE OF PRE-AIA OR AIA STATUS The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . REJECTIONS BASED ON PRIOR ART Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-6, 8-15, 17-23 and 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tian et al. (U.S. Patent No. 11,609,858), herein referred to as Tian et al. Referring to claim 1, Tian et al. disclose as claimed, a computer-implemented method for minimizing effects of cache thrashing, the method comprising: monitoring cache activity of a workload (see col. 5, lines 24-36, where a bypass predictor may detect whether a working set is thrashing the LLC); identifying a non-temporal workload based on said monitored cache activity of said workload (see col. 5, lines 36-65, where the bypass predictor learns or adapts based on metadata of lines evicted from the L2 cache, for example if the metadata indicates a poor LLC hit ratio, then it predicts a next L2 cast out to be a LLC-bypassable cast out. Also see col. 7, lines 13-23, where based on a hit or miss on a cache line, a reuse-hint bit is set); identifying one or more cache lines associated with said non-temporal workload; and altering a persistence policy for said one or more cache lines associated with said non-temporal workload (see col. 5, lines 10-55 and col. 6, lines 48-60, where a bypass predictor predicts if a cache line has a high or low probability of reuse, and uses a hint bit as well as counters to to indicate and determine whether a cache line should be re-used, which would be altering a persistence policy for that cache line. Also see col. 8, lines 38-50, giving an example of the reuse bit and counters determining whether an LLC is bypassed). Claims 10 and 18 recite similar limitations to claim 1 and would be rejected using the same rationale. As to claim 2, Tian et al. also disclose the method as recited in claim 1, wherein said persistence policy is altered to reduce a tenure of said one or more cache lines (see col. 9, lines 9-20, where a cache line may be downgraded/upgraded or allocated in a different LRU location depending on whether it is predicted to be reused). Claims 11 and 19 recite similar limitations to claim 2 and would be rejected using the same rationale. As to claim 3, Tian et al. also disclose the method as recited in claim 2, wherein said persistence policy is altered to reduce said tenure of said one or more cache lines via setting a particular value in a hint bit (see col. 9, lines 9-20, where a cache line may be downgraded/upgraded or allocated in a different LRU location depending on whether it is predicted to be reused. This is based on the LLC_reuse_hint bit as well as LLC_reuse_hit and counter bits). Claims 12 and 20 recite similar limitations to claim 3 and would be rejected using the same rationale. As to claim 4, Tian et al. also disclose the method as recited in claim 1, wherein said persistence policy is altered to cast-out said one or more cache lines directly to memory (see col. 6, lines 18-30, where the cache controller may manage allocating or bypassing victims from the L2 cache to either the LLC or to main memory). Claims 13 and 21 recite similar limitations to claim 4 and would be rejected using the same rationale. As to claim 5, Tian et al. also disclose the method as recited in claim 1 further comprising: analyzing metrics of said monitored cache activity of said workload (see col. 5, lines 25-55, where the bypass predictor tracks the reuse and dynamically detects whether the working set is thrashing the LLC and predicts it based on the metadata that indicates cache activity such as a poor LLC hit ratio. Also see col. 6, lines 48-67, where cache activity metrics such as reuse hint bits and hit counters are used in prediction). Claims 14 and 22 recite similar limitations to claim 5 and would be rejected using the same rationale. As to claim 6, Tian et al. also disclose the method as recited in claim 5, wherein said metrics of said monitored cache activity of said workload comprise one or more of the following selected from the group consisting of: cache hit/miss ratio, cache miss data sources, fetch/cast-out ratio, and percentage of cast-outs with changed data (see col. 5, lines 44-55, where the cache controller evaluates the LLC hit ratio in determining whether to alter a persistence policy). Claims 15 and 23 recite similar limitations to claim 6 and would be rejected using the same rationale. As to claim 8, Tian et al. also disclose the method as recited in claim 1, wherein said cache activity of said workload is monitored in connection with local caches and peer caches (see col. 5, lines 24-36, where the cache is a 3 level cache hierarchy with an L1, L2 and LLC. See fig. 1, showing the caches being local to processor 105). Claims 17 and 25 recite similar limitations to claim 8 and would be rejected using the same rationale. As to claim 9, Tian et al. also disclose the method as recited in claim 1, wherein said workload streams data from a memory (see col. 1, lines 42-58, where workloads may contain streaming data or non-temporal patterns). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 7, 16 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Tian et al. in view of Komaromy et al. (U.S. Patent Application Publication No. 2013/0117843), herein referred to as Komaromy et al. As to claim 7, Tian et al. disclose the claimed invention except for the method as recited in claim 5, wherein said cache activity of said workload is monitored in connection with a peer cache, wherein said metrics of said monitored cache activity of said workload comprise a cast-in/fetch-hit ratio provided by said peer cache. However, Komaromy et al. disclose wherein said cache activity of said workload is monitored in connection with a peer cache, wherein said metrics of said monitored cache activity of said workload comprise a cast-in/fetch-hit ratio provided by said peer cache (see para. 72, where a miss/hit or a hit/miss ratio is used for analyzing cache performance. As a miss results in data being fetched from storage and entered into the cache, it would be a cast-in and a hit would constitute a fetch-hit. Therefore a miss/hit ratio is equivalent to a cast-in/fetch-hit ratio. See fig. 4, showing a cache memory system with an L1 cache and an L2 cache, and see para. 51-53, where the cache monitor monitors accesses to that cache memory system, which includes peer caches L1 and L2). Tian et al. and Komaromy et al. are analogous art because they are from the same field of endeavor of caching (see Tian et al., abstract and Komaromy et al., abstract, regarding caching). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tian et al. to comprise wherein said cache activity of said workload is monitored in connection with a peer cache, wherein said metrics of said monitored cache activity of said workload comprise a cast-in/fetch-hit ratio provided by said peer cache, as taught by Komaromy et al., in order to more accurately measure cache activity to predict a non-temporal cache line. There are many well known methods to monitor cache activity. It would be obvious to one of ordinary skill in the art to utilize a metric such as cast-in/fetch-hit ratio with Tian et al.’s objective of monitoring cache activity through the use of metrics and performance. Claims 16 and 24 recite similar limitations to claim 7 and would be rejected using the same rationale. Response to Arguments Applicant's arguments, filed 3/23/26, have been fully considered but they are not persuasive. Applicant argues that Tian does not disclose “monitoring cache activity of a workload.” Applicant acknowledges that Tian discloses that the bypass predictor predicts or indicates thrashing and may dynamically detect whether the working set is thrashing the LLC. However, detecting whether a working set is thrashing the LLC is monitoring cache activity of a workload. There is no indication why a working set cannot constitute a workload. In addition, Tian discusses tracking an overall pattern of reuse in the LLC. This is again monitoring cache activity of a workload. Applicant has not defined workload to be any specific function, and therefore must be read in the broadest reasonable interpretation. Applicant further argues that Tian does not disclose “identifying a non-temporal workload based on said monitored cache activity of said workload.” Applicant again argues that there is no specific language of “identifying a non temporal workload.” However, non-temporal in the context of memory operations generally refers to data that is unlikely to be re-used soon. Therefore, Tian’s bypass predictor learning and adapting and determining what L2 line is next likely to be cast out. Tian, col. 7, lines 13-23 even uses a reuse-hint bit. Again, showing that Tian’s bypass predictor is designed to identify non-temporal workloads by having a reuse-hint bit. See col. 5, lines 10-23, where the prediction may indicate to bypass if there is a low probability of reuse. That would indicate a non temporal workload. Again, as workload is not defined in the claims, the broadest reasonable interpretation would be any type of activity or work being done as long as it is associated with a cache line. Tian’s prediction of reuse predicts whether there is a non-temporal workload associated with that cache line. Applicant further argues that there is no language identifying one or more cache lines associated with the non-temporal workload. However, Tian, col. 5, discusses casting out a victim from a cache if the prediction indicates to not bypass (i.e. a high probability or reuse). Therefore, that cache line is associated with a non-temporal workload. In addition, Tian, col. 5, lines 10-55 and col. 6, lines 48-60, shows where a bypass predictor predicts if a cache line has a high or low probability of reuse, and uses a hint bit as well as counters to indicate and determine whether a cache line should be re-used. That again shows that a cache line is associated with a non-temporal workload. Applicant additionally argues that there is no language that discloses altering a persistence policy for the one or more cache lines associated with the non-temporal workload. However, applicant argues that although Tian determines whether a cache is bypassed for a victim block, it doesn’t address the concept of a non-temporal workload. This argument has been addressed above. However, in regards to the persistence policy, Tian uses a hint bit and counters to indicate and determine whether a cache line should be re-used, which would constitute altering a persistence policy for that cache line, which is associated with a non-temporal workload. A cache line that is unlikely to be re-used and has been identified as such was associated with a non-temporal workload. As discussed previously, detecting whether a working set is thrashing the LLC is monitoring cache activity of a workload. And associating that cache line with the non-temporal working set or workload may be accomplished by altering a bit to mark it. CLOSING COMMENTS a. STATUS OF CLAIMS IN THE APPLICATION The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i): a(1) CLAIMS REJECTED IN THE APPLICATION Per the instant office action, claims 1-25 stand rejected. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. b. DIRECTION OF FUTURE CORRESPONDENCES Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALAN OTTO whose telephone number is (571)270-1626. The examiner can normally be reached M-F 8:30AM-5:00PM. Any Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.O/Examiner, Art Unit 2132 /HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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Prosecution Timeline

Sep 12, 2024
Application Filed
Dec 23, 2025
Non-Final Rejection mailed — §102, §103
Mar 13, 2026
Response Filed
Jun 18, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
66%
Grant Probability
84%
With Interview (+18.0%)
3y 5m (~1y 6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 372 resolved cases by this examiner. Grant probability derived from career allowance rate.

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