DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 09/12/2024 have been accepted by the examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 09/12/2024. The information disclosed therein was considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 11-15, & 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Disegni et al (US20210183442).
Regarding claim 1, Disegni discloses a row decoder circuit(FIG 8; [0093]), comprising: at least one input node configured to receive at least one row selection signal(PX, sLX, sLY) and an output node configured for coupling to a word line of a memory device(WL-dx<0>); a first pull-down circuit coupled between the word line and a ground node at ground voltage(110 coupled between WL and ground), the first pull-down circuit configured to selectively couple the word line to the ground node in response to the at least one row selection signal being asserted110 coupling WL to ground in response to at least (PX, sLX, sLY)); a pull-up circuit coupled between the word line and a supply node that provides a selectable supply voltage (126R coupled between WL and Vdd), the pull-up circuit configured to selectively couple the word line to the supply node in response to a deselection signal being de-asserted(Vcomm<0>);
an inverter circuit coupled between the supply node and a shifted ground node that provides a selectable reference voltage (212 between Vdd and 219 and provides shifted ground), the inverter circuit configured to receive as input a control signal from a control node and produce the deselection signal (INT to produce Vcomm<0>);
a current generator circuit configured to source a biasing current to the control node(FIG 8; [0084-0085] discloses 200, 302, 304 configured to source biasing current I1 to INT); and a second pull-down circuit coupled between the control node and the ground node(202, 204, 206, 208 & 210 coupled between INT and ground), the second pull-down circuit configured to selectively couple the control node to the ground node in response to the at least one row selection signal being asserted(INT to ground in response to PX,Slx,sLY), wherein the second pull-down circuit comprises a first cascode n-channel transistor(202) , a second cascode n-channel transistor(206), and at least one selection transistor all having conductive channels arranged in series between the control node and the ground node( 208 & 210 having their conductive channels arrange in series between INT and ground), and wherein the at least one selection transistor is controlled by the at least one row selection signal(PX,sLX, sLY).
However, Disegni does not disclose a cascode p-channel transistor. However, the particular placement of a cascode p-channel transistor device was held to be an obvious matter of design choice. Therefore, Disegni can easily replace the transistor (204) with the cascode p-channel transistor. Please see MPEP 2144.04.
Regarding claim 2, Disegni discloses wherein: the first cascode n-channel transistor has a conductive channel arranged between the control node and a first cascode node(202 between INT and node end of 202); the cascode p-channel transistor has a conductive channel arranged between the first cascode node and a second cascode node(204 between end of 202 and end of 204); the second cascode n-channel transistor has a conductive channel arranged between the second cascode node and a third cascode node(206 between end of 204 and end of 206); and the at least one selection transistor has a conductive channel arranged between the third cascode node and the ground node (208 210 between end of 206 and ground).
Regarding claim 11, Disegni discloses further comprising a memory control circuit configured to: during a read operation of the memory device(FIG 8; [0020 & 0083]), set the selectable supply voltage to a first supply value and set the selectable reference voltage to the ground voltage(shifted ground); and during a write operation of the memory device, set the selectable supply voltage to a second supply value that is higher than the first supply value, and set the selectable reference voltage to half of the second supply value(shifting Vdd, at a supply voltage e.g., equal to 1.8V in the reading step and 4.8V in writing step).
Regarding claim 12, Disegni discloses wherein the first supply value is equal to 2 V and the second supply value is equal to 4.8 V (FIG 8; [0020 & 0083] discloses shifting Vdd, at a supply voltage e.g., equal to 1.8V in the reading step and 4.8V in writing step).
Regarding claim 13, Disegni discloses a method of operating a row decoder circuit comprising at least one input node(FIG 8; [0098]; PX, sLX,sLY), an output node for a word line of a memory device(WL-dx<0>), a first pull-down circuit coupled between the word line and a ground node at ground voltage(110 coupled between WL and ground), a pull-up circuit coupled between the word line and a supply node(126R coupled between WL and Vdd), an inverter circuit coupled between the supply node and a shifted ground node (212 between Vdd and 219 and provides shifted ground), and a second pull-down circuit coupled between a control node and the ground node(202, 204, 206, 208 & 210 coupled between INT and ground), the second pull-down circuit comprising a first cascode n-channel transistor(202), a second cascode n-channel transistor(206), and at least one selection transistor all having conductive channels arranged in series between the control node and the ground node( 208 & 210 having their conductive channels arrange in series between INT and ground), the method comprising: receiving, by the at least one input node, at least one row selection signal; selectively coupling, by the first pull-down circuit, the word line to the ground node in response to the at least one row selection signal being asserted(10 coupling WL to ground in response to at least (PX, sLX, sLY); selectively coupling, by the pull-up circuit, the word line to the supply node in response to a deselection signal being de-asserted(Vcomm<0>); receiving, at an input of the inverter circuit, a control signal from the control node; producing, at an output of the inverter circuit, the deselection signal(INT to produce Vcomm<0>);; sourcing, by a current generator, a biasing current to the control node FIG 8; [0084-0085] discloses 200, 302, 304 configured to source biasing current I1 to INT); and selectively coupling, by the second pull-down circuit, the control node to the ground node in response to the at least one row selection signal being asserted(INT to ground in response to PX,Slx,sLY), the selectively coupling the control node to the ground node comprising controlling, by the at least one row selection signal, the at least one selection transistor(PX,sLX, sLY).
However, Disegni does not disclose a cascode p-channel transistor. However, the particular placement of a cascode p-channel transistor device was held to be an obvious matter of design choice. Therefore, Disegni can easily replace the transistor (204) with the cascode p-channel transistor. Please see MPEP 2144.04.
Regarding claim 14, Disegni discloses further comprising: providing, by the supply node, a selectable supply voltage; and providing, by the shifted ground node, a selectable reference voltage (FIG 8;212 between Vdd and 219 and provides shifted ground).
Regarding claim 15, Disegni discloses further comprising a memory control circuit configured to: during a read operation of the memory device, set the selectable supply voltage to a first supply value and set the selectable reference voltage to the ground voltage; and during a write operation of the memory device, set the selectable supply voltage to a second supply value that is higher than the first supply value, and set the selectable reference voltage to half of the second supply value FIG 8; [0020 & 0083] discloses shifting Vdd, at a supply voltage e.g., equal to 1.8V in the reading step and 4.8V in writing step).
Allowable Subject Matter
Claims 18-20 are allowed.
Claims 3-10 & 16-17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Keeth et al (US7969810 FIG 2-3; discloses pulldown, pullup and inverters circuits).
Behera et al (US20110063893 FIG 5; discloses WL, pull up and pull-down circuits).
Lee et al (US7391670 FIG 3-5; discloses first and second signal generator and inverters).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUNA A TECHANE/Primary Examiner, Art Unit 2827