DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to communication(s) filed on 09/12/2024. Claims 1-12 have been examined and are pending in this application.
Information Disclosure Statement
The information disclosure statements (IDSs) were submitted on 04/02/2025 and 09/12/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Nakazumi US 2018/0275911 (“Nakazumi”).
As per independent claim 1, Nakazumi teaches A method for performing data segregation in a storage device (“a method of distinguishing the hot data from the cold data … will be described.” Para 0056), comprising:
receiving, by the storage device, an Input-Output (I-O) from a host system (“The memory system 1 may receive an access request (e.g., a read request and a write request) from the host 2.” Para 0029 and FIG. 1), the I-O comprising data and information on data placement by the host system in a placement handle of a plurality of placement handles of the storage device (“Each access request includes a logical address [i.e., placement handle] indicating an access destination. The logical address indicates a location in a logical address space provided to the host 2 by the memory system 1. The memory system 1 receives writing target data along with the write request.” Para 0029 and FIG. 1);
determining, by the storage device, whether an overwrite count of the data of the I-O placed by the host system in the placement handle is different from an average overwrite count of data in the placement handle of the storage device upon receiving the I-O (“A rewriting frequency of each piece of data transmitted from the host 2 to the memory system 1 may not be uniform for each piece of data in some cases. In other words, periods of being updated may be different depending on logical addresses.” Para 0051. “FIG. 3B illustrates valid data ratios when hot data and cold data are stored being mixed in the same block 22.” Para 0052);
grouping, by the storage device, one or more pages corresponding to the data of the I-O placed by the host system in the placement handle to another placement handle of the plurality of placement handles that matches the overwrite count of the data of the I-O placed by the host system based on the determination of the overwrite count of the data of the I-O placed by the host system in the placement handle being different from the average overwrite count of data in the placement handle of the storage device during an internal operation (“FIG. 3A illustrates valid data ratios when hot data and cold data are separately stored in different blocks 22.” Para 0052. “In the relocating process, the CPU 11 relocates the hot data and the cold data to the blocks 22 different from each other.” Para 0055);
updating, by the storage device, a log page to record the grouping of the one or more pages (“The CPU 11 updates the translation information 131 when the user data 23 transmitted from the host 2 is written on the NAND memory 20, and when the valid data is written on the NAND memory 20 in the relocating process.” Para 0069).
The claimed invention discloses “overwrite count”. The Examiner mapped the term to “rewriting frequency” described in paragraph [0051] of Nakazumi. That is, in the first embodiment, Nakazumi does not explicitly teach “overwrite count” in the first embodiment.
However, in the third embodiment, Nakazumi teaches “a hot data relocating writing counter 1301” and “a cold data relocating writing counter 1302”, para 0162 and FIG. 20. It is noted that in NAND memory of Nakazumi, writing is the same as overwriting since data is written or overwritten out-of-place. Therefore, the hot and cold writing counters of Nakazumi count writes or overwrites or rewrites.
Hence, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Nakazumi with “overwrite count”. The motivation would be that when hot and cold data are separately stored, a data block with a smaller valid data ratio is generated, para 0054 of Nakazumi, which improves write amplification as would be recognized by those of ordinary skill in the art.
As per dependent claim 4, Nakazumi discloses the method of claim 1. Nakazumi teaches wherein prior to receiving the I-O by the storage device, the method comprising: placing, by the host system, the information on data placement in the I-O (“Each access request includes a logical address indicating an access destination. The logical address indicates a location in a logical address space provided to the host 2 by the memory system 1. The memory system 1 receives writing target data along with the write request.” Para 0029 and FIG. 1).
As per dependent claim 5, Nakazumi discloses the method of claim 1. Nakazumi teaches wherein the log page comprises at least one of an updated logical block address of the data, a size of the data, and a hotness of the data (“The CPU 11 updates the translation information 131 when the user data 23 transmitted from the host 2 is written on the NAND memory 20, and when the valid data is written on the NAND memory 20 in the relocating process.” Para 0069).
As per dependent claim 6, Nakazumi discloses the method of claim 1. Nakazumi teaches wherein the information on data placement comprises a logical block address of the data and size of the data (“Each access request includes a logical address indicating an access destination. The logical address indicates a location in a logical address space provided to the host 2 by the memory system 1. The memory system 1 receives writing target data along with the write request.” Para 0029 and FIG. 1).
As per claims 7 and 10-12, these claims are respectively rejected based on arguments provided above for similar rejected claims 1 and 4-6. See FIG. 1 of Nakazumi for a processor and a memory.
Claims 2-3 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Nakazumi in view of Gorobets et al. US 2013/0024609 (“Gorobets”).
As per dependent claim 2, Nakazumi discloses the method of claim 1. Nakazumi may not explicitly disclose, but in an analogous art in the same field of endeavor, Gorobets teaches further comprising: generating, by the host system, a probability matrix based on data attributes (“A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations.” Para 0117) and information present in the log page (“Temperature as a function of time stamp and write count.” Para 0152);
placing, by the host system controlling the storage device, the data of the I-O in one of the plurality of placement handles of the storage device based on the probability matrix (“STEP 740: Ranking each logical group stored in the SLC portion by a temperature, where a higher temperature indicates a higher probability the logical group will suffer subsequent rewrites due to garbage collection operations.” Para 0202 and FIG. 20).
Given the teaching of Gorobets, it would have been obvious to a person of ordinary skill in the art before the effective filing data of the claimed invention to further modify the scope of the invention of Nakazumi with “further comprising: generating, by the host system, a probability matrix based on data attributes and information present in the log page; and placing, by the host system controlling the storage device, the data of the I-O in one of the plurality of placement handles of the storage device based on the probability matrix”. The motivation would be that parallel programming disclosed by the invention improves read and program performance, para 0053 of Gorobets.
As per dependent claim 3, Nakazumi in combination with Gorobets discloses the method of claim 2. Nakazumi teaches wherein the data attributes comprise at least one of a module identifier of an application, an average input-output size, an average overwrite rate (“an average value of the erase counts” para 0098), an average block size, a read-write ratio, and sequentiality of input-output access.
As per dependent claims 8-9, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 2-3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZUBAIR AHMED whose telephone number is (571)272-1655. The examiner can normally be reached 7:30AM - 5:00PM EST.
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132