Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in thefile.
Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 11-13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fujino et al. (US20200364002) in view of Liao (US 20080205159 A1).
Regarding claims 1, 13, and 20: Fujino discloses a semiconductor storage device (1, FIG. 1) comprising: a memory cell (MC, FIG. 3) that includes a switching element (select transistor 31, FIG. 3) and a variable resistance element (variable-resistance element 30, FIG. 3); and a control circuit (12, FIG. 2) configured to, as part of performing an overall read operation (control circuit 12 controls read and write circuit 15, par. 67, FIG. 2): perform a first read operation (S11, FIG. 6) on the memory cell to detect a first voltage and determine first data stored in the memory cell from the detected first voltage (par. 65), perform a first write operation (S12, FIG. 6) on the memory cell after the first read operation to write second data to the memory cell (par. 66), perform a second read operation (S13, FIG. 6) on the memory cell after the first write operation to detect a second voltage and determine the second data stored in the memory cell from the detected second voltage (par. 67), compare the first data and the second data based on the first voltage and the second voltage (par. 68) to determine a value (S14, FIG. 6) of the first data, and perform a sequence of operations when the first data and the second data are different (YES branch of S23, FIG. 7).
Fujino does not disclose a semiconductor device comprising: the sequence of operations including a second write operation on the memory cell to write the first data to the memory cell, and a verify read operation performed on the memory cell after the second write operation that detects a third voltage and determines third data stored in the memory cell from the detected third voltage, compare either the first data and the third data based on the first voltage and the third voltage or the second data and the third data based on the second voltage and the third voltage, end the overall read operation when the first data and the third data are the same or when the second data and the third data are different, and repeat the sequence of operations when the first data and the third data are different or when the second data and the third data are the same.
Liao does disclose a verification process of memory comprising: the sequence of operations including a second write operation (program process 202 includes write operation, par. 14, FIG. 2) on the memory cell to write the first data to the memory cell, and a verify read operation (verification process 204, par. 14, FIG. 2) performed on the memory cell after the second write operation that detects a third voltage and determines third data stored in the memory cell from the detected third voltage (verification process includes reading voltage status of the memory cell for verify, par. 14), compare either the first data and the third data based on the first voltage and the third voltage (verification process includes comparing status voltage of verification result with the expected voltage from previous program operation, par. 14) or the second data and the third data based on the second voltage and the third voltage, end the overall read operation when the first data and the third data are the same (YES path of 206 to END, upon determining the data is successfully the same and thus not needed to be worked upon any longer, par. 14, FIG. 2) or when the second data and the third data are different, and repeat the sequence of operations when the first data and the third data are different (NO path of 206, upon determining the data is different (not success) and thus need to be repeated upon, par. 14, FIG. 2) or when the second data and the third data are the same.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Fujino with the operation method of Liao to allow the system to have the looping program sequence to monitor and program the memory cell.
Regarding claim 11: Fujino discloses a semiconductor storage device (1, FIG. 1) comprising: a variable resistance element (30, FIG. 4) includes a first ferromagnetic layer (storage layer 32 is a ferromagnetic later, par. 50, FIG. 4), a second ferromagnetic layer (reference layer 34 is a ferromagnetic layer, par 52, FIG. 4), and an insulating layer (tunnel barrier layer 33 is a nonmagnetic insulating film, par. 51, FIG. 4) between the first ferromagnetic layer and the second ferromagnetic layer (layer 33 in between ferromagnetic layers 32 and 34, par. 48, FIG. 4).
Regarding claim 12: Fujino discloses a semiconductor storage device (1, FIG. 1) comprising: a switching element is a two-terminal switching element (memory cell MC may be configured with a two-terminal switching element, par. 106).
Claim(s) 2-3 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Fujino et al. (US20200364002) in view of Liao (US 20080205159 A1), in further view of Izumi et al. (US 20190189218 A1).
Regarding claims 2 and 14: Fujino and Liao do not disclose a control circuit of the semiconductor device further configured to: vary a program voltage applied to the memory cell in the second write operation depending on how many times the sequence of operations is performed.
Izumi does disclose a semiconductor memory device (10, FIG. 1) configured to vary a program voltage (program voltage VPGM) applied to the memory cell (applied to control gate of memory cell transistor MT, par. 72) in the second write operation (second write S14, FIG. 6) depending on how many times the sequence of operations is performed (program voltage VPGM is stepped up with each program loop repeated, par 71-72 and 155).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Fujino and Liao with the configuration of Izumi to allow the system to alter the program voltage as the program loop repeats to account for each iteration of programming.
Regarding claims 3 and 15: Fujino and Liao do not disclose a control circuit of the semiconductor device further configured to: vary an amount of current caused to flow in the memory cell in the second write operation depending on how many times the sequence of operations is performed.
Izumi does disclose a semiconductor memory device (10, FIG. 1) configured to vary an amount of current caused to flow in the memory cell (varying program voltage VPGM via incremental step pulse program (ISPP) in par. 71-72, it is inherent that the current flowing through the memory cell will also vary by an amount) in the second write operation depending on how many times the sequence of operations is performed.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Fujino and Liao with the configuration of Izumi to allow the system to alter the program voltage as the program loop repeats to account for each iteration of programming.
Claim(s) 4 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Fujino et al. (US20200364002) in view of Liao (US 20080205159 A1), in further view of Parker (US 6343033 B1).
Regarding claims 4 and 16: Fujino and Liao do not disclose a control circuit of the semiconductor device further configured to: vary a pulse width of a program voltage applied to the memory cell in the second write operation depending on how many times the sequence of operations is performed.
Parker does disclose a memory programming with variable pulse width comprising: vary a pulse width of a program voltage (varying pulse widths during programming of memory cell via applying secondary pulses to initial pulse 304-306, FIG. 3) applied to the memory cell in the second write operation depending on how many times the sequence of operations is performed (Cell Not Programmed route of 306 for program loop, FIG. 3).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Fujino and Liao with the configuration of Parker to allow the system to alter the program voltage width as the program loop repeats to account for each iteration of programming, such as reducing programming time (col. 1 ll. 60-63 and col. 2 ll. 18-27).
Claim(s) 5, 7, 10, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Fujino et al. (US20200364002) in view of Liao (US 20080205159 A1), in further view of Shibata et al. (US 20210104274 A1).
Regarding claims 5 and 17: Fujino and Liao do not disclose a control circuit of the semiconductor device further configured to: consecutively perform the verify read operation in an nth round (n is an integer not less than 1) of performing the sequence of operations and the second write operation in an (n+1)th round of performing the sequence of operations.
Shibata does disclose a semiconductor memory device (FIG. 2) configured to consecutively perform the verify read operation (verify operation S30, FIG. 9) in an nth round (n is an integer not less than 1) (rounds determined by counter PC beginning at 1 S27, FIG. 9) of performing the sequence of operations (repeating sequence between YES path of S37 and S27, FIG. 9) and the second write operation in an (n+1)th (S27 program write, PC is incremented by 1 prior thus (PC+1)th round, par. 188, FIG. 9) round of performing the sequence of operations.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Fujino and Liao with the configuration of Shibata to allow the operation loop to perform the desired actions as the claimed invention.
Regarding claims: 7 and 18: Fujino and Liao do not disclose a control circuit of the semiconductor device further configured to: consecutively perform the second read operation and the second write operation of a first round of the sequence of operations.
Shibata does disclose a semiconductor memory device (FIG. 2) configured to consecutively perform the second read operation (internal read S24, FIG. 9) and the second write operation (write in program S27, FIG. 9) of a first round of the sequence of operations (S24-S27 first performed before PC increments past first iteration, FIG. 9).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Fujino and Liao with the configuration of Shibata to allow the operation loop to perform the desired actions as the claimed invention.
Regarding claims 10 and 19: Fujino and Liao do not disclose a control circuit of the semiconductor device further configured to: end the overall read operation based on an mth round (m is an integer not less than 2) of the sequence of operations having been performed.
Shibata does disclose a semiconductor memory device (FIG. 2) configured to end the overall read operation based on an mth round (m is an integer not less than 2) of the sequence of operations having been performed (end of sequence S37 checks counter PC against maximum number of program loops allowed, going to END if PC exceeds the maximum allowed number, FIG. 9).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Fujino and Liao with the configuration of Shibata to allow the system to finish the sequence loop when a maximum allowable number of iterations has occurred like the claimed invention.
Claim(s) 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Fujino et al. (US20200364002) in view of Liao (US 20080205159 A1), in further view of Shibata et al. (US 20210104274 A1), in further view of Mathur et al. (US 20160111471 A1).
Regarding claims 6 and 8: Fujino, Liao, and Shibata do not disclose the switching element of the memory cell is a snap-back selector.
Mathur does disclose selector elements that can be suitable for memory device wherein the switching element (selector element 725 of memory element, FIG. 7) is a snap-back selector (selector element may exhibit snapback phenomena, par. 99-100).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Fujino, Liao, and Shibata with the configuration of Mathur to allow the memory device to account for the decrease in performance due to snapback to ensure reliable performance.
Allowable Subject Matter
Claim(s) 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: a direction in which the control circuit applies voltage to the memory cell in each of the first read operation, the second read operation, and the verify read operation is opposite to a direction in which the control circuit applies voltage to the memory cell in the first write operation as in claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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