DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-6 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a mathematical algorithm using mathematical calculations to detect, count, compare and correct a number of errors in an abstract data block structure depending on the number of errors without significantly more. The claim(s) recite(s) recites various functional steps for implementing the mathematical algorithm for detecting, counting, and correcting errors. This judicial exception is not integrated into a practical application because claim 1 does not recite any practical application (the method steps do not require any system and/or any structural element that when combined with the abstract algorithm raises the level to a practical application). Furthermore, the processor in claim 6 can be a general-purpose processor which is insufficient to raise the level to a practical application. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because claim 1 does not recite any structural element that when combined with the abstract algorithm raises the level to a practical application. Furthermore, the processor in claim 6 can be a general-purpose processor which is insufficient to raise the level to a practical application.
Claim 4 in the Applicant’s specification teaches that the data block arises after read out from a storage device and a transmission of the original data block.
For the purposes of advancing prosecution, the Examiner suggests that the Applicant inserts the following limitation as the first limitation after “comprising:” in the first line of claim 1: --receiving a transmitted signal comprising a data block after read out from a storage device--.
As per claim 6:
the Examiner suggests deleting the first limitation “receive a data block to be corrected” and replacing it with --receive a transmitted signal comprising a data block to be corrected after read out from a storage device--.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20190089379 A1 is directed to A method for decoding forward error correction codes, the method comprising: decoding a plurality of component, the plurality of component codes comprising code symbols, for which at least one code symbol is involved in multiple component codes; and analyzing the decoding of each of the plurality of component codes to generate an outcome, wherein analyzing the decoding of each of the plurality of component codes comprises: estimating at least one possible error location; storing information related to the at least one possible error location; storing state information; and updating the state information based on: information related to the generated outcome; and a previous version of the state information; and, is a good teaching reference.
US 20180269905 A1 is directed to a system for reduced-latency decoding, comprising: a memory accessible via a memory channel; an encoder module configured to encode a data block in a codeword, the data block accessed from the memory via the memory channel; and a reduced-latency decoder module configured to: maintain in the memory a first decoding state and a second decoding state associated with decoding a first constituent codeword according to a first decoding procedure and a second decoding procedure, respectively, wherein: the first constituent codeword is one of a plurality of constituent codewords that constitute the codeword, a data bit of the codeword is protected by the first constituent codeword and by at least a second constituent codeword of the codeword; and in an iteration to decode the codeword according to the first decoding procedure: prior to decoding the first constituent codeword according to the first decoding procedure, determine whether the first decoding state indicates a decoding failure, and if the first decoding state indicates the decoding failure, lower a decoding latency by skipping the decoding of the first constituent codeword according to the first decoding procedure, or if the first decoding state does not indicate the decoding failure: decode the first constituent codeword according to the first decoding procedure, wherein the decoding of the first constituent codeword according to the first decoding procedure at least flips the data bit common with the second constituent codeword to correct an error, and update in the memory a decoding state of the second constituent codeword based on the flipping of the data bit, the decoding state associated with decoding the second constituent codeword according to the first decoding procedure; and, is a good teaching reference.
US 6272659 B1 is directed to An error correction code (ECC) processor for correcting errors in binary data of an ECC codeword, including a plurality of ECC redundancy symbols for correcting a maximum number of correctable errors in the ECC codeword, read from a disc storage medium, the ECC codeword comprising a first and a second set of intersecting ECC codewords of a multi-dimensional code wherein the error correction code processor processes the first and second sets of ECC codewords in iterative error correction passes, the ECC processor comprising; and, is a good teaching reference.
US 5589994 A is directed to A method of copying compressed digital data from a first medium to a second medium, comprising the steps of: (a) reading, from said first medium, compressed digital data comprising codewords having check fields and flags, said flags identifying codewords with uncorrected errors; (b) using said check fields to correct errors in said codewords; (c) using said check fields to detected uncorrectable errors in said codewords; (d) updating said flags to identify codewords in which uncorrectable errors were detected in said step (c); and (e) recording said compressed digital data as read in said step (a) and corrected in said step (b) on said second medium, together with the check fields used in said steps (b) and (c) and said flags as updated in said step (d); and, is a good teaching reference.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D TORRES whose telephone number is (571)272-3829. The examiner can normally be reached Monday-Friday 10-7 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH D TORRES/ Primary Examiner, Art Unit 2112