DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 9/12/2024 have been considered by the examiner.
Claim Objections
Claims 4 and 15 are objected to because of the following informalities:.
Regarding claim 4: there is a superfluous space at the end of the claim (i.e. “bank .” which should be “”
Regarding claim 15: the claim is interpreted and objected to for the same reasons as set forth in claim 4.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1:
A) line 3 includes “adding a new node to the first listlet as a new tail node” which implies adding a new node as a new tail node (e.g. first in first out), while line 4 includes “replacing a tail node of the first listlet with the new tail node” which implies both enqueing the new node and dequeing the tail node prior to adding the new node (e.g. last in first out). Further, the precise intention/relationship between “tail node” and “new tail node”, not particularly limited (e.g. both “tail node” and “new tail node” being the same), is also ambiguous. Thus, in view of the above, whether the intent includes some implied sequence/step, the intent is somehow similar to last in first out, or something else, is unclear. Examination continued on the assumption some missing step in first in first out, enqueuing/dequeueing, and/or may include pointers inadvertently omitted, as opposed to new matter / written description issues being introduced.
B) lines 5-6 includes idiomatic issues “determining that a second listlet of the master linked list that includes a tail node of the master linked list” which is ambiguous as to whether “second listlet” or “second listlet includes a tail node” is determined. Examination continued on the assumption the limitation is merely somehow determining a tail node (e.g. where to add a new node).
Regarding claim 2: the claim, ultimately dependent upon claim 1, is interpreted and rejected for the same reason as set forth in claim 1.
Regarding claim 3: the claim, ultimately dependent upon claim 1, is interpreted and rejected for the same reason as set forth in claim 1.
Regarding claim 4: the claim, ultimately dependent upon claim 1, is interpreted and rejected for the same reason as set forth in claim 1. Further, lines 4-5 includes “replacing the tail node of the first listlet with the new tail node by moving the tail node of the first listlet to a memory bank” which, similar to claim 1, implies both enqueing the new node and dequeing the tail node prior to adding the new node, and does not further provide additional clarity of claim 1. Additionally, the precise intention/relationship between “tail node” and “new tail node”, not particularly limited (e.g. both “tail node” and “new tail node” being the same), does not provide additional clarity. Thus, in view of the above, whether the intent is similar to enqueing a new node and updating a tail pointer, the intent includes an omitted sequence/step, the intent is somehow similar to last in first out, or something else, is unclear. Examination continued on the assumption first in first out, enqueuing/dequeueing, and/or may include pointers inadvertently omitted, as opposed to new matter / written description issues being introduced.
Regarding claim 5: the claim, ultimately dependent upon claim 1, is interpreted and rejected for the same reason as set forth in claim 1.
Regarding claim 6: the claim, ultimately dependent upon claim 1, is interpreted and rejected for the same reason as set forth in claim 1.
Regarding claim 7: the claim, ultimately dependent upon claim 1, is interpreted and rejected for the same reason as set forth in claim 1.
Regarding claim 8: the claim, ultimately dependent upon claim 1, is interpreted and rejected for the same reason as set forth in claim 1.
Regarding claim 9: the claim, ultimately dependent upon claim 1, is interpreted and rejected for the same reason as set forth in claim 1.
Regarding claim 10: the claim, ultimately dependent upon claim 1, is interpreted and rejected for the same reason as set forth in claim 1.
Regarding claim 11: the claim, ultimately dependent upon claim 1, is interpreted and rejected for the same reason as set forth in claim 1.
Regarding claim 12: the claim is interpreted and rejected for the same reason as set forth in claim 1.
Regarding claim 13: the claim is interpreted and rejected for the same reason as set forth in claim 2.
Regarding claim 14: the claim is interpreted and rejected for the same reason as set forth in claim 3.
Regarding claim 15: the claim is interpreted and rejected for the same reason as set forth in claim 4.
Regarding claim 16: the claim is interpreted and rejected for the same reason as set forth in claim 5.
Regarding claim 17: the claim is interpreted and rejected for the same reason as set forth in claim 6.
Regarding claim 18: the claim is interpreted and rejected for the same reason as set forth in claim 7.
Regarding claim 19: the claim is interpreted and rejected for the same reason as set forth in claim 8.
Regarding claim 20: the claim is interpreted and rejected for the same reason as set forth in claim 9.
The examiner respectfully recommends further amendments to clearly specify sequence using language such as -after adding-, -in response to adding-, -new/old-, -previous/before/prior to-, -after/subsequent to-, etc., and explicitly claiming features intended to be included to obviate broad interpretation, new matter / written description issues, and/or indefinite issues, by using language such as, for example -included/stored in- as opposed to -of-. The examiner notes alternative rejections have been provided in view of the above indefinite issues.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 8 of U.S. Patent No. 12,120,037 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because take an example of comparing claim 1 of the pending application and claim 1 of U.S. Patent No. 12,120,037 B2:
18/883,513
US 12,120,037 B2
Claim 1 [*notwithstanding indefinite issues]: A method comprising:
Claim 1: A method comprising: [*limitations not required in 18/883,513 omitted]
enqueuing a data packet to a first listlet of a master linked list by:
... push a first data packet ... to a master linked list ...;
pushing the first data packet ... to the master linked list ...;
[*pushing being “enqueuing”]
adding a new node to the first listlet as a new tail node; and
adding a first new node to a first tail node of the first listlet ...;
[*tail node of first listlet is the tail node of the master linked list]
replacing a tail node of the first listlet with the new tail node;
[*indefinite]
removing a first previous node of the first listlet ...;
[*adding new node and removing previous tail node being “replacing”]
determining that a second listlet of the master linked list that includes a tail node of the master linked list;
[*indefinite]
determining, ..., that the second listlet includes a tail of the master linked list;
setting a next listlet identifier of the tail node of the master linked list to identify the first listlet; and
setting a next listlet identifier of a tail node of the second listlet to identify the first listlet; and
[*tail node of first listlet is the tail node of the master linked list]
updating a tail identifier of the master linked list from identifying the second listlet to identifying the first listlet.
... updating the tail identifier of the master linked list ... from identifying the second listlet to identifying the first listlet.
Regarding claim 12, the claim corresponds to claim 8.
Claims 1 and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 and 14 of U.S. Patent No. 10,652,163 B2 in view of Liu et al. (US 2015/0082319 A1) hereinafter Liu. Take an example of comparing claim 1 of the pending application and claim 7 of U.S. Patent No. 10,652,163 B2:
18/883,513
US 10,652,163 B2
Claim 1 [*notwithstanding indefinite issues]: A method comprising:
Claim 1: A method comprising: [*limitations not required in 18/883,513 omitted]
Claim 6: The method of claim 1 [*limitations not required in 18/883,513 omitted]
Claim 7: The method of claim 6 [*limitations not required in 18/883,513 omitted]
enqueuing a data packet to a first listlet of a master linked list by:
push a second data packet to the master linked list;
[*pushing being “enqueuing”]
adding a new node to the first listlet as a new tail node; and
enqueueing the second data packet to the first listlet,
[*tail node of first listlet is the tail node of the master linked list;
**enqueueing being “adding”]
replacing a tail node of the first listlet with the new tail node;
[*indefinite]
...
determining that a second listlet of the master linked list that includes a tail node of the master linked list;
[*indefinite]
determining, ..., that the second listlet includes the tail of the master linked list;
setting a next listlet identifier of the tail node of the master linked list to identify the first listlet; and
setting a next listlet identifier of a tail node of the second listlet to identify the first listlet; and
[*tail node of first listlet is the tail node of the master linked list]
updating a tail identifier of the master linked list from identifying the second listlet to identifying the first listlet.
updating the master linked list tail identifier to identify the first listlet instead of the first listlet.
While a node being enqueued to a FIFO queue is pushed to the FIFO queue to become the tail node of the FIFO queue, US 10,652,163 B2 claim 1 does not explicitly teach “replacing a tail node of the first listlet with the new tail node”.
Liu teaches enqueueing a new node to a queue, where the new node is added after a current tail node at the end of the queue, the new node then becomes [replaces] the new tail node (para. 31).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Liu with that of US 10,652,163 B2. The motivation for doing so would have been US 10,652,163 B2’s network devices implementing a master linked list using multiple banks of memory (col. 2 lines 1-20) along with Liu’s parallel scheduling (para. [17, 42]) improves efficiency by enabling high performance traffic scheduling and alleviating memory access latencies employing linked lists.
Regarding claim 12, the claim corresponds to claim 14.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 11-14, and 17 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Cheng et al. (US 2012/0163396 A1, made of record in the IDS of 9/12/2024) hereinafter Cheng.
Regarding claim 1, Cheng teaches a method (during enqueue; para. 39) comprising: enqueueing a data packet (frame arrives at queue 202 and distributed to sub-queues; para. 39 and Fig. 2) to a first listlet (frame pushed into first sub-queue 210 [listlet]; para. 39 and Fig. 2) of a master linked list (queue divided into sub-queues; para. 38, sub-queues implemented using linked lists and stored; para. [10-11, 37]) by adding a new node to the first listlet as a new tail node (tail pointer pointing to last node; para. 37, frame 4 being last arrived added as tail to sub-queue 210; para. 38-39 and Fig. 2); and replacing a tail node of the first listlet with the new tail node (sub-queue 210 includes frame 0, new node added and tail pointer pointing to last node [replacing tail node]; para. 37-38 and Fig. 2); determining that a second listlet of the master linked list that includes a tail node of the master linked list (queue management includes [determining] enqueuing incoming frame to sub-queue [arbitrary / second] following round-robin sequence; para. [13, 39]); setting a next listlet identifier of the tail node of the master linked list to identify the first listlet (after enqueuing/pushing frame [tail] to sub-queue 216, queue-select/sub-queue counter [identifier] keeps track where incoming frame will be stored [next listlet]; para. 39); and updating a tail identifier of the master linked list from identifying the second listlet to identifying the first listlet (after enqueuing/pushing frame 3 [tail] to sub-queue 216 [previous tail of master linked list], next frame 4 added to sub-queue 210, queue-select/sub-queue counter [identifier] keeps track [updates] where incoming frame will be stored [identifying next listlet]; para. 39).
Regarding claim 2, Cheng teaches the limitation of previous claim 1.
Cheng further teaches wherein the enqueuing the data packet to the first listlet is based on a specified enqueue order (enqueueing sub-queues in round-robin fashion, after enqueueing, counter for enqueueing next frame incremented [specified enqueue order]; para. [13, 39]).
Regarding claim 3, Cheng teaches the limitation of previous claim 1.
Cheng further teaches wherein the enqueuing the data packet to the first listlet is based on a predetermined round robin order (enqueueing sub-queues in round-robin fashion; para. [13, 39]).
Regarding claim 6, Cheng teaches the limitation of previous claim 1.
Cheng further teaches receiving a request to dequeue a second data packet (dequeue selected [requested] queue, dequeue request; para. [41-43, 50]); determining from a head identifier of the master linked list that a third listlet includes a head of the master linked list (queue-select/sub-queue counter determines sub-queue to be dequeued; para. [40, 47], popped data in FIFO in round robin fashion; para. [13, 39, 42], frames distributed in round-robin fashion; para. [13, 39]); dequeueing a head node from the third listlet (queue manager pops current head frame; para. 41, popped data in FIFO in round robin fashion; para. [13, 39, 42], frames distributed in round-robin fashion; para. [13, 39]); and updating the head identifier of the master linked list from identifying the third listlet to identifying the second listlet (queue-select/sub-queue counter updated to point to next sub-queue to be dequeued; para. [40, 47]).
Regarding claim 11, Cheng teaches the limitation of previous claim 1.
Cheng further teaches wherein the master linked list is formed by a plurality of listlets (queue divided into sub-queues; para. 38, sub-queues implemented using linked lists and stored; para. [10-11, 37]).
Regarding claim 12, the claim is interpreted and rejected for the same reason as set forth in claim 1, including system (system; para. 29 and Fig. 1) at least one processor (chip implementing queueing system, including circuits field-programmable gate array; para. [48, 55] and Fig. 4); and at least one memory storing instructions which when executed by the at least one processor (memory storing code for use by computer system; para. 55 and Fig. 4).
Regarding claim 13, the claim is interpreted and rejected for the same reason as set forth in claim 2.
Regarding claim 14, the claim is interpreted and rejected for the same reason as set forth in claim 3.
Regarding claim 17, the claim is interpreted and rejected for the same reason as set forth in claim 6.
Claim(s) 1-9 and 11-20 is/are (alternatively) rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Figueira (US 2006/0031643 A1, made of record in the IDS of 9/12/2024) hereinafter Figueira.
Regarding claim 1, Figueira teaches a method (first in first out (FIFO) implemented using linked lists and formed by interleaved linked lists; para. 51) comprising: enqueueing a data packet to a first listlet of a master linked list (FIFO implemented using linked lists [master] and formed by interleaved linked lists [listlet]; para. 51, enqueue operation; para. [44, 56-57] and Figs. [6A-6B, 9], storing incoming packets; para. 30 and Fig. 8) by adding a new node to the first listlet as a new tail node (data written to tail; para. [35-36, 41]); and replacing a tail node of the first listlet with the new tail node (data written to tail; para. [35-36, 41], tail of FIFO is changed at end of enqueuing; para. 44); determining that a second listlet of the master linked list that includes a tail node of the master linked list (when enqueue operation performed [determining], next_enqueue register updated to point to next linked list [from linked_list_0 to linked_list_1, from linked_list_1 to linked_list_2, from linked_list_2 to linked_list_0]; para. 57 and Figs. [6A-6B, 9], FIFO implemented using linked lists and formed by interleaved linked lists; para. 51); setting a next listlet identifier of the tail node of the master linked list to identify the first listlet (when enqueue operation performed, next_enqueue register updated to point to next linked list [from linked_list_2 to linked_list_0]; para. 57 and Figs. [6A-6B, 9]); and updating a tail identifier of the master linked list from identifying the second listlet to identifying the first listlet (when enqueue operation performed [determining], next_enqueue register updated to point to next linked list [from linked_list_2 to linked_list_0]; para. 57 and Figs. [6A-6B, 9], FIFO implemented using linked lists and formed by interleaved linked lists; para. 51).
Regarding claim 2, Figueira teaches the limitation of previous claim 1.
Figueira further teaches wherein the enqueuing the data packet to the first listlet is based on a specified enqueue order (queue service policy implemented in first-in-first-out (FIFO); para. [29, 31] and Figs. 8-9).
Regarding claim 3, Figueira teaches the limitation of previous claim 1.
Figueira further teaches wherein the enqueuing the data packet to the first listlet is based on a predetermined round robin order (FIFO scheduling policy includes round robin; para. [34, 63]).
Regarding claim 4, Figueira teaches the limitation of previous claim 1.
Figueira further teaches linking the tail node of the first listlet to point to the new node of the first listlet (newly enqueued data pointed to by previous final data; para. [42, 44, 57] and Figs. [4, 6A-6B, 9]); and replacing the tail node of the first listlet with the new tail node by moving the tail node of the first listlet to a memory bank (data written to tail; para. [35-36, 41], tail of FIFO is changed at end of enqueuing; para. 44, memory banks configured to include queues performing enqueue/dequeue operations; para. 32-33).
Regarding claim 5, Figueira teaches the limitation of previous claim 1.
Figueira further teaches accessing the tail identifier of the master linked list from a cache (tail_fifo [tail identifier] implemented as register; para. 35, tail_fifo contains last memory of FIFO; para. 41), wherein the tail identifier of the master linked list identifies a listlet that includes the tail node of the master linked list (tail_fifo contains last memory of FIFO; para. 41, FIFO implemented using linked lists [master] and formed by interleaved linked lists [listlet]; para. 51).
Regarding claim 6, Figueira teaches the limitation of previous claim 1.
Figueira further teaches receiving a request to dequeue a second data packet (dequeue operation issued; para. 37); determining from a head identifier of the master linked list that a third listlet includes a head of the master linked list (next_dequeue register [head identifier] identifies link list [third listlet] to perform dequeuing [head of master link list]; para. 54-55 and Fig. 8); dequeueing a head node from the third listlet (dequeue operation performed on linked list pointed to by next_dequeue; para. 54-56 and Fig. 8); and updating the head identifier of the master linked list from identifying the third listlet to identifying the second listlet (next_dequeue updated to point to the next linked list [from linked_list_0 to linked_list_1, from linked_list_1 to linked_list_2, from linked_list_2 to linked_list_0]; para. 55 and Fig. 8).
Regarding claim 7, Figueira teaches the limitation of previous claim 6.
Figueira further teaches wherein a cache stores heads and tails of a plurality of listlets (each link list of FIFO includes its own head_fifo and tail_fifo registers; para. 53 and Fig. 8), the head identifier of the master linked list (head_fifo [tail identifier] implemented as register; para. 35, head_fifo contains first memory of FIFO; para. 41), and the tail identifier of the master linked list (tail_fifo [tail identifier] implemented as register; para. 35, tail_fifo contains last memory of FIFO; para. 41).
Regarding claim 8, Figueira teaches the limitation of previous claim 6.
Figueira further teaches wherein the master linked list is stored via a plurality of memory banks (memory for FIFO implemented in multiple memory banks; para. 31-32).
Regarding claim 9, Figueira teaches the limitation of previous claim 6.
Figueira further teaches wherein the head node includes a pointer to another node of the third listlet (pointer field in data structure used to address next location for next node in [same/third] linked list; para. 40 and Figs. [6A-6B, 7A-7B, 8]).
Regarding claim 11, Figueira teaches the limitation of previous claim 1.
Figueira further teaches wherein the master linked list is formed by a plurality of listlets (FIFO implemented using linked lists [master] and formed by interleaved linked lists [listlet]; para. 51).
Regarding claim 12, the claim is interpreted and rejected for the same reason as set forth in claim 1, including system (system; para. 07 and Figs. 11-12) at least one processor (processor; para. 66); and at least one memory storing instructions which when executed by the at least one processor (memory storing program instructions executed on a processor; para. 66).
Regarding claim 13, the claim is interpreted and rejected for the same reason as set forth in claim 2.
Regarding claim 14, the claim is interpreted and rejected for the same reason as set forth in claim 3.
Regarding claim 15, the claim is interpreted and rejected for the same reason as set forth in claim 4.
Regarding claim 16, the claim is interpreted and rejected for the same reason as set forth in claim 5.
Regarding claim 17, the claim is interpreted and rejected for the same reason as set forth in claim 6.
Regarding claim 18, the claim is interpreted and rejected for the same reason as set forth in claim 7.
Regarding claim 19, the claim is interpreted and rejected for the same reason as set forth in claim 8.
Regarding claim 20, the claim is interpreted and rejected for the same reason as set forth in claim 9.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Zhou et al. (US 8,442,063 B1, made of record in the IDS of 9/12/2024) hereinafter Zhou.
Regarding claim 10, Cheng teaches the limitation of previous claim 6.
While Cheng discloses sub-queues having head pointer, Cheng does not explicitly disclose wherein the head node includes another listlet identifier that identifies another one of a plurality of listlets that includes a new head of the master linked list.
However, in the same field of endeavor, Zhou teaches wherein the head node includes another listlet identifier that identifies another one of a plurality of listlets (head of linked list includes interleave indicator [identifies another linked list]; col. 5 lines 50-54 and Fig. 1) that includes a new head of the master linked list (hybrid queue including multiple subqueues, subqueues include interleave indicator identifies subqueue including head of hybrid queue; col. 4 lines 17-20, after element 106 dequeued, indicator points to another linked list that includes [new] head of hybrid queue [master linked list]; col. 8 lines 40-51 and Fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the technique of Utley to the system of Cheng, where Cheng’s increased throughput using multiple sub-queues (para. 38) along with Zhou’s efficient and scalable scheduling of multicast and unicast traffic (col. 2 lines 31-38) improves the system by minimizing overhead.
Claim(s) 10 is/are (alternatively) rejected under 35 U.S.C. 103 as being unpatentable over Figueira in view of Ni (US 2002/0124149 A1, made of record in the IDS of 9/12/2024) hereinafter Ni.
Regarding claim 10, Figueira teaches the limitation of previous claim 6.
Figueira does not explicitly disclose wherein the head node includes another listlet identifier that identifies another one of a plurality of listlets that includes a new head of the master linked list.
However, in the same field of endeavor, Ni teaches wherein the head node includes another listlet identifier that identifies another one of a plurality of listlets that includes a new head of the master linked list (link list structure configured to include multiple independent linked list, each link list assigned to an associated memory bank; para. [11, 13], pointer of data packet indicates another bank [another listlet]; para. [para. 43, 47-48] and Figs. 2A-2B, queueing scheme based on round robin [new head]; para. 51).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the technique of Ni to the system of Figueira, where Figueira’s multiple interleaved linked lists (para. 07) along with Ni’s multiple independent link list exclusively assigned to memory bank (para. 11) improves the system by avoiding successive reads/writes from same bank, thereby reducing stall cycles.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Utley (US 2005/0086416 A1) discloses a processor with multiple linked list storage feature.
Agrawal et al. (US 2011/0228795 A1) discloses multi-bank queuing architecture for higher bandwidth on-chip memory buffer.
Jones et al. (US 2013/0198480 A1) discloses parallel dynamic memory allocation using a lock-free FIFO.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE L PEREZ whose telephone number is (571) 270-7348. The examiner can normally be reached M-F 11 am - 3 pm.
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/JOSE L PEREZ/Examiner, Art Unit 2474
/Michael Thier/Supervisory Patent Examiner, Art Unit 2474
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