DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6-7, 11-12, 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Furuta U.S. Patent Application Publication US2006/0161822A1.
As per claim 1, Furuta teaches a method comprising: allocating a first storage for dynamically storing error entries (¶ 0026, 0034, 0060, RAM); allocating a second storage for statically storing a plurality of records, wherein each record of the one or more records is associated with a hardware structure of the plurality of hardware structures of an integrated circuit (¶ 0026, 0031, 0062, NVRAM); receiving an error entry associated with an error event of a first hardware structure of the one or more first hardware structures (¶ 0033-0034); storing the error entry in a location of the first storage (¶ 0034); and updating a first record of the plurality records, wherein the first record is associated with the first hardware structure (¶ 0031), and wherein updating the first record comprises modifying the first record to indicate the location of the error entry in the first storage (¶ 0054).
As per claim 2, Furuta teaches the method of claim 1, wherein: each stored error entry includes: an address field (Fig. 4, ¶ 0051); an information field (¶ 0034); and a timestamp field (¶ 0035); and each record (¶ 0044, wherein an error record is acquired) includes; a control field (¶ 0042, 0048, wherein a compression command is added to the header); a status field (¶ 0035, “65a”); and an internal field (¶ 0035, “65c”).
As per claim 6, Furuta teaches the method of claim 1, wherein the error entry is a first error entry, and the method further comprises: determining that the first storage is not full; and determining an available location in the first storage (¶ 0026, 0034, 0060).
As per claim 7, Furuta teaches the method of claim 1, further comprises: receiving a read associated with the first record; and performing a read operation (¶ 0031, wherein the compression component reads the record in RAM).
As per claim 11, Furuta teaches an integrated circuit comprising: a first storage; and processing circuitry configured to: allocate the first storage for dynamically storing error entries; allocate second storage for statically storing a plurality of records, wherein each record of the plurality of records is associated with a hardware structure of a plurality of hardware structures of an integrated circuit; receive an error entry associated with an error event of a first hardware structure of the plurality of hardware structures; store the error entry in a location of the first storage; and update a first record of the plurality of records, wherein the first record is associated with the first hardware structure (¶ 0026, 0034, 0060, 0031, 0062, 0033-0034, 0031, see claim 1), and wherein updating the first record comprises modifying the first record to indicate the location of the error entry in the first storage (¶ 0054).
As per claim 12, Furuta teaches the integrated circuit of claim 11, wherein the processing circuitry is further to: receive a read associated with the first record; and perform a read operation (¶ 0031).
As per claim 16, Furuta teaches a computer system comprising: a first storage; a second storage; and processing circuitry configured to: allocate the first storage for dynamically storing error entries; allocate the second storage for statically storing one or more records, wherein each record of the one or more records is associated with a hardware structure of one or more hardware structures of an integrated circuit; receive an error entry associated with an error event of a hardware structure of the plurality of hardware structures; store the error entry in a location of the first storage; and update a first record of the plurality of records, wherein the first record is associated with the first hardware structure (¶ 0026, 0034, 0060, 0031, 0062, 0033-0034, 0031, see claim 1), and wherein updating the first record comprises modifying the first record to indicate the location of the error entry in the first storage (¶ 0054).
As per claim 17, Furuta teaches the computer system of claim 16, wherein the processing circuitry is further to: receive a read associated with the first record; and perform a read operation (¶ 0031).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furuta in view of Storm U.S. Patent Application Publication US2023/0195556A1.
As per claim 4, Furuta teaches the method of claim 1. Storm teaches wherein the error entry is a first error entry, and the method further comprises: determining that the first storage is full; and determining the location to be the location of a second error entry stored in the first storage (¶ 0058). It would have been obvious to one of ordinary skill in the art to use the process of Storm in the process of Furuta. One of ordinary skill in the art would have been motivated to use the process of Storm in the process of Furuta because using the process of Storm would yield the predictable result of saving space on a memory for error recordation, an explicit desire of Furuta.
As per claim 5, Storm teaches the method of claim 4, wherein said storing the error entry in the location comprises: overwriting the second error entry (¶ 0058).
Allowable Subject Matter
Claims 3, 8-10, 13-15, 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
8. Applicant's arguments filed 4/15/26 have been fully considered but they are not persuasive.
The applicant has argued that the newly amended claim language overcomes the cited art. The examiner respectfully disagrees. Furuta teaches, in paragraphs 0052-0055, wherein error information is received and is determined if it is the first error information. If it is not the first, then the existing error record is updated with the new information, which can include the location of said error (see paragraph 0036). In paragraph 0055, Furuta then teaches this newly updated error record is then substituted in the NVRAM error records in place of the existing record. The examiner interprets this as teaching the new language.
Conclusion
9. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER S MCCARTHY whose telephone number is (571)272-3651. The examiner can normally be reached Monday-Friday 8:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571)272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER S MCCARTHY/Primary Examiner, Art Unit 2113
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