DETAILED ACTION
This action is responsive to the amendments filed 30 Jul 2026. Claims 1-20 are pending. Claims 1, 12 and 16 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed 30 Jul 2026 has been entered. Claims 1-20 are currently pending in the application.
Notice of Foreign Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Application Title
In accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the application. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
“MEMORY MODULE WITH MODE REGISTER TO INDICATE OPERATION IN MIRROR MODE”
No action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Response to Arguments
Applicant’s arguments filed on 30 Jul 2026 have been fully considered. Applicant’s arguments are not persuasive in regards to the 35 USC § 103 rejections as the claims are currently written. Arguments and corresponding examiner’s responses are shown below for independent Claim 1. The same arguments are valid for the similar features of the other independent claims.
Argument 1: The applicant states “Kim does not teach or suggest that the first command has command/address bits that are “swapped” relative to a second command. Kim merely teaches that a TMRS or MR command is issued to set the mirroring mode, for example, as described in the above paragraphs of Kim.”
Response 1: A new reference, Lee (U.S. Patent Application Publication 2020/0335139) has been cited to teach this limitation.
Allowable Subject Matter
Claims 5 – 11, 15, 16, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 2, 12 – 14, and 17 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, et al, U.S. Patent Application Publication 2021/0104291 (“Kim”) in view of Lee, et al, U.S. Patent Application Publication 2020/0335139 (“Lee”).
Regarding claim 1, Kim teaches:
(Currently Amended) A memory module comprising: a circuit board comprising a plurality of signal lines to which a command is applied; and a first memory device mounted on a first surface of the circuit board, connected to the plurality of signal lines, comprising a first mode register, and configured to: (Kim, fig 5, 25, 26, “[0053] FIG. 5 is a diagram illustrating a memory 100 … an address buffer 150, a control logic 160, an input/output circuit 170, a read failure indicator 180, and a mirroring mode activation signal generator 190. [0060] The control logic 160 may be implemented to control the overall operation of the memory 100. … The control logic 160 may include a refresh control circuit 161, a command decoder 162, and a mode register circuit (MRC)163. [0143] FIG. 25 is a diagram illustrating a mobile device 3000 [0152] In an example embodiment, the storage device 3300 may be… Chip On Board (COB), [0159] FIG. 26 is a diagram illustrating a computing system 4000 … connected to a system bus 4001, a memory device 4210 or a storage device 4220 connected to the system bus 4001,”; a system with a memory system 100, the memory system comprising a controller, a mirroring mode activation signal generator, and a mode register circuit MRC 163; the memory can be part of either a device 3000 or device 4000 with on a circuit board and comprising plurality of data bus lines between components).
operate in a standard mode or a mirrored mode, based on a value set in the first mode register, (Kim, fig 5,, “[0041] When the mirroring mode is not applied, as illustrated in FIG. 1, the memory system may fully operate the Channels and the DIMMs [0008] an operating method of a memory may include setting a mirroring mode, writing the same data to a first memory area of the memory area and a second memory area of the memory [0063] Further, the mode register circuit (MRC) 163 may include a register that sets a mirroring mode for performing an on-die mirroring operation. In FIG. 5, the on-die mirroring mode may be set by the mode register set (MRS), but it should be understood that the present inventive concepts may be not limited thereto.”; a memory that can operate in two modes: normal operation without mirroring data; and mirroring data to memory areas; the system includes a mode register 163 that sets the normal or mirroring mode for the memory).
set a value corresponding to the mirrored mode in the first mode register, based on a first command applied to the plurality of signal lines, (Kim, fig 5, “[0063] The mode register circuit (MRC) 163 may set an internal mode register in response to a Mode Register Set (MRS)… Further, the mode register circuit (MRC) 163 may include a register that sets a mirroring mode for performing an on-die mirroring operation.[0064] The on-die mirroring mode of the present inventive concepts may be set by data received through at least one dedicated or predetermined pin.”; that a value in the MRC 163 may set the mirror or normal operation; that the mirroring mode may be set by receiving data (i.e. a bit) through predetermined pin).
Kim does not explicitly teach wherein a first logic value of a first command/address (CA) bit and a second logic value of a second CA bit of a second command are respectively swapped to the second CA bit and the first CA bit of the first command..
Lee teaches wherein a first logic value of a first command/address (CA) bit and a second logic value of a second CA bit of a second command are respectively swapped to the second CA bit and the first CA bit of the first command. (Lee, fig 5, 15, “[0064] The on-die mirroring mode of the present inventive concepts may be set by data received through at least one dedicated or predetermined pin. In an example embodiment, the on-die mirroring operation may be activated by setting a test mode register set (TMRS) through Basic Input/Output System (BIOS) settings in the system. [0106] The memory controller 200 may generate test mode register set (TMRS)/mode register (MR) setting information for the on-die mirroring operation of the memory 100 (Sll). The TMRS/MR setting information may be transmitted from the memory controller 200 to the memory 100. [0107] The memory 100 may receive the TMRS/MR setting information, and may set an on-die mirroring mode (S20).”; a memory controller 200 issues a “test mode register set” command; the command is received at the memory block 100; the mode register command has at least two states and is changed by the Command/Address TMRS command: one state (not using mirroring) to a second state (set on-die mirroring mode)).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to Kim before the effective filing date of the claimed invention in order to teach operations for memory systems. The teachings of Lee, in the same or in a similar field of endeavor with Kim, can combine Lee’s explicit swapping of control bits in a mode with simply operating in different modes The two different methods of indicating mode operation merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 2, Kim, as modified by Lee, teaches the memory module of claim 1.
Kim further teaches:
wherein the first memory device is further configured to: operate in the standard mode, based on a default value set in the first mode register; and (Kim, fig 5, “[0118] In a case of data centers or vehicles in which reliability may be important in system applications, the on-die mirroring operation may be performed at the beginning. … For example, the system may not use half of the DRAM capacity as a default at the beginning, may monitor application and memory status ( e.g., duration, or frequency of failures), and may activate the on-die mirroring operation if desired to ensure system stability.”; a system that can operate with the mirroring mode as default or normal mode as a default).
set the value corresponding to the mirrored mode in the first mode register based on the first command applied to the plurality of signal lines in the standard mode. (Kim, fig 5, 15, “[0064] The on-die mirroring mode of the present inventive concepts may be set by data received through at least one dedicated or predetermined pin. In an example embodiment, the on-die mirroring operation may be activated by setting a test mode register set (TMRS) through Basic Input/Output System (BIOS) settings in the system. [0106] The memory controller 200 may generate test mode register set (TMRS)/mode register (MR) setting information for the on-die mirroring operation of the memory 100 (Sll). The TMRS/MR setting information may be transmitted from the memory controller 200 to the memory 100. [0107] The memory 100 may receive the TMRS/MR setting information, and may set an on-die mirroring mode (S20).”; a memory controller 200 issues a “test mode register set” command; the command is received at the memory block 100; the mode register command has at least two states and is changed by the Command/Address TMRS command: one state (not using mirroring) to a second state (set on-die mirroring mode)).
Regarding claim 12, Kim teaches:
(Currently Amended) A memory system comprising: a memory module comprising a first memory device mounted on a first surface of a circuit board; and a memory controller operatively connected to the memory module, wherein the first memory device comprises a first mode register and is configured to …wherein the circuit board comprises a plurality of signal lines connected to the first memory device,… (Kim, fig 5, 25, 26, “[0053] FIG. 5 is a diagram illustrating a memory 100 … an address buffer 150, a control logic 160, an input/output circuit 170, a read failure indicator 180, and a mirroring mode activation signal generator 190. [0060] The control logic 160 may be implemented to control the overall operation of the memory 100. … The control logic 160 may include a refresh control circuit 161, a command decoder 162, and a mode register circuit (MRC)163. [0143] FIG. 25 is a diagram illustrating a mobile device 3000 [0152] In an example embodiment, the storage device 3300 may be… Chip On Board (COB), [0159] FIG. 26 is a diagram illustrating a computing system 4000 … connected to a system bus 4001, a memory device 4210 or a storage device 4220 connected to the system bus 4001,”; a system with a memory system 100, the memory system comprising a controller, a mirroring mode activation signal generator, and a mode register circuit MRC 163; the memory can be part of either a device 3000 or device 4000 with on a circuit board and comprising plurality of data bus lines between components).
operate in a standard mode or a mirrored mode based on a value stored in the first mode register, (Kim, fig 5,, “[0041] When the mirroring mode is not applied, as illustrated in FIG. 1, the memory system may fully operate the Channels and the DIMMs [0008] an operating method of a memory may include setting a mirroring mode, writing the same data to a first memory area of the memory area and a second memory area of the memory [0063] Further, the mode register circuit (MRC) 163 may include a register that sets a mirroring mode for performing an on-die mirroring operation. In FIG. 5, the on-die mirroring mode may be set by the mode register set (MRS), but it should be understood that the present inventive concepts may be not limited thereto.”; a memory that can operate in two modes: normal operation without mirroring data; and mirroring data to memory areas; the system includes a mode register 163 that sets the normal or mirroring mode for the memory).
wherein the memory controller is configured to apply, to the plurality of signal lines, a first command for setting a value corresponding to the mirrored mode in the first mode register, (Kim, fig 5, “[0063] The mode register circuit (MRC) 163 may set an internal mode register in response to a Mode Register Set (MRS)… Further, the mode register circuit (MRC) 163 may include a register that sets a mirroring mode for performing an on-die mirroring operation.[0064] The on-die mirroring mode of the present inventive concepts may be set by data received through at least one dedicated or predetermined pin.”; that a value in the MRC 163 may set the mirror or normal operation; that the mirroring mode may be set by receiving data (i.e. a bit) through predetermined pin).
Kim does not explicitly teach wherein a first logic value of a first command/address (CA) bit and a second logic value of a second CA bit of a second command are respectively swapped to the second CA bit and the first CA bit of the first command..
Lee teaches wherein a first logic value of a first command/address (CA) bit and a second logic value of a second CA bit of a second command are respectively swapped to the second CA bit and the first CA bit of the first command. (Lee, fig 5, 15, “[0064] The on-die mirroring mode of the present inventive concepts may be set by data received through at least one dedicated or predetermined pin. In an example embodiment, the on-die mirroring operation may be activated by setting a test mode register set (TMRS) through Basic Input/Output System (BIOS) settings in the system. [0106] The memory controller 200 may generate test mode register set (TMRS)/mode register (MR) setting information for the on-die mirroring operation of the memory 100 (Sll). The TMRS/MR setting information may be transmitted from the memory controller 200 to the memory 100. [0107] The memory 100 may receive the TMRS/MR setting information, and may set an on-die mirroring mode (S20).”; a memory controller 200 issues a “test mode register set” command; the command is received at the memory block 100; the mode register command has at least two states and is changed by the Command/Address TMRS command: one state (not using mirroring) to a second state (set on-die mirroring mode)).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to Kim before the effective filing date of the claimed invention in order to teach operations for memory systems. The teachings of Lee, in the same or in a similar field of endeavor with Kim, can combine Lee’s explicit swapping of control bits in a mode with simply operating in different modes The two different methods of indicating mode operation merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 13, Kim, as modified by Lee, teaches (Currently Amended) The memory system of claim 12.
Kim further teaches:
wherein the first memory device further comprises a plurality of pins connected to the plurality of signal lines, and wherein the first memory device is further configured to: operate in the standard mode, based on a default value set in the first mode register; and (Kim, fig 5, “[0118] In a case of data centers or vehicles in which reliability may be important in system applications, the on-die mirroring operation may be performed at the beginning. … For example, the system may not use half of the DRAM capacity as a default at the beginning, may monitor application and memory status ( e.g., duration, or frequency of failures), and may activate the on-die mirroring operation if desired to ensure system stability.”; a system that can operate with the mirroring mode as default or normal mode as a default).
based on the first command applied to the plurality of signal lines in the standard mode, receive, through the plurality of pins, the second command, andset the value corresponding to the mirrored mode in the first mode register. (Kim, fig 5, 15, “[0064] The on-die mirroring mode of the present inventive concepts may be set by data received through at least one dedicated or predetermined pin. In an example embodiment, the on-die mirroring operation may be activated by setting a test mode register set (TMRS) through Basic Input/Output System (BIOS) settings in the system. [0106] The memory controller 200 may generate test mode register set (TMRS)/mode register (MR) setting information for the on-die mirroring operation of the memory 100 (Sll). The TMRS/MR setting information may be transmitted from the memory controller 200 to the memory 100. [0107] The memory 100 may receive the TMRS/MR setting information, and may set an on-die mirroring mode (S20).”; a memory controller 200 issues a “test mode register set” command; the command is received at the memory block 100; the mode register command has at least two states and is changed by the Command/Address TMRS command: one state (not using mirroring) to a second state (set on-die mirroring mode)).
Regarding claim 14, Kim, as modified by Lee, teaches the memory system of claim 12.
Kim further teaches wherein the memory controller is included in test equipment for the memory module. (Kim, fig 5, “[0064] The on-die mirroring mode of the present inventive concepts may be set by data received through at least one dedicated or predetermined pin. In an example embodiment, the on-die mirroring operation may be activated by setting a test mode register set (TMRS) through Basic Input/Output System (BIOS) settings in the system”; that the mode setting information can be a subset of the chip “test mode register set”, or test equipment).
Regarding claim 17, Kim teaches:
(Currently Amended) A method of a memory module comprising a first memory device mounted on one surface of a circuit board, the method comprising: operating, at the first memory device, in a standard mode, based on a default value set in a first mode register in the first memory device; … , wherein the circuit board comprises the plurality of signal lines,… (Kim, fig 5, 25, 26, “[0053] FIG. 5 is a diagram illustrating a memory 100 … an address buffer 150, a control logic 160, an input/output circuit 170, a read failure indicator 180, and a mirroring mode activation signal generator 190. [0060] The control logic 160 may be implemented to control the overall operation of the memory 100. … The control logic 160 may include a refresh control circuit 161, a command decoder 162, and a mode register circuit (MRC)163. [0143] FIG. 25 is a diagram illustrating a mobile device 3000 [0152] In an example embodiment, the storage device 3300 may be… Chip On Board (COB), [0159] FIG. 26 is a diagram illustrating a computing system 4000 … connected to a system bus 4001, a memory device 4210 or a storage device 4220 connected to the system bus 4001,”; a system with a memory system 100, the memory system comprising a controller, a mirroring mode activation signal generator, and a mode register circuit MRC 163; the memory can be part of either a device 3000 or device 4000 with on a circuit board and comprising plurality of data bus lines between components).
setting a value corresponding to a mirrored mode in the first mode register, based on a first command applied to a plurality of signal lines connected to the first memory device; and (Kim, fig 5,, “[0041] When the mirroring mode is not applied, as illustrated in FIG. 1, the memory system may fully operate the Channels and the DIMMs [0008] an operating method of a memory may include setting a mirroring mode, writing the same data to a first memory area of the memory area and a second memory area of the memory [0063] Further, the mode register circuit (MRC) 163 may include a register that sets a mirroring mode for performing an on-die mirroring operation. In FIG. 5, the on-die mirroring mode may be set by the mode register set (MRS), but it should be understood that the present inventive concepts may be not limited thereto.”; a memory that can operate in two modes: normal operation without mirroring data; and mirroring data to memory areas; the system includes a mode register 163 that sets the normal or mirroring mode for the memory).
operating, at the first memory device, in the mirrored mode, based on the value corresponding to the mirrored mode set in the first mode register, (Kim, fig 5, “[0063] The mode register circuit (MRC) 163 may set an internal mode register in response to a Mode Register Set (MRS)… Further, the mode register circuit (MRC) 163 may include a register that sets a mirroring mode for performing an on-die mirroring operation.[0064] The on-die mirroring mode of the present inventive concepts may be set by data received through at least one dedicated or predetermined pin.”; that a value in the MRC 163 may set the mirror or normal operation; that the mirroring mode may be set by receiving data (i.e. a bit) through predetermined pin).
Kim does not explicitly teach wherein a first logic value of a first command/address (CA) bit and a second logic value of a second CA bit of a second command are respectively swapped to the second CA bit and the first CA bit of the first command..
Lee teaches wherein a first logic value of a first command/address (CA) bit and a second logic value of a second CA bit of a second command are respectively swapped to the second CA bit and the first CA bit of the first command. (Lee, fig 5, 15, “[0064] The on-die mirroring mode of the present inventive concepts may be set by data received through at least one dedicated or predetermined pin. In an example embodiment, the on-die mirroring operation may be activated by setting a test mode register set (TMRS) through Basic Input/Output System (BIOS) settings in the system. [0106] The memory controller 200 may generate test mode register set (TMRS)/mode register (MR) setting information for the on-die mirroring operation of the memory 100 (Sll). The TMRS/MR setting information may be transmitted from the memory controller 200 to the memory 100. [0107] The memory 100 may receive the TMRS/MR setting information, and may set an on-die mirroring mode (S20).”; a memory controller 200 issues a “test mode register set” command; the command is received at the memory block 100; the mode register command has at least two states and is changed by the Command/Address TMRS command: one state (not using mirroring) to a second state (set on-die mirroring mode)).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to Kim before the effective filing date of the claimed invention in order to teach operations for memory systems. The teachings of Lee, in the same or in a similar field of endeavor with Kim, can combine Lee’s explicit swapping of control bits in a mode with simply operating in different modes The two different methods of indicating mode operation merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 18, Kim, as modified by Lee, teaches (Currently Amended) The method of claim 17.
Kim further teaches further comprising storing, in a nonvolatile memory region, (Kim, fig 5, “[0118] In a case of data centers or vehicles in which reliability may be important in system applications, the on-die mirroring operation may be performed at the beginning. … For example, the system may not use half of the DRAM capacity as a default at the beginning, may monitor application and memory status ( e.g., duration, or frequency of failures), and may activate the on-die mirroring operation if desired to ensure system stability.”; a system that can operate with the mirroring mode as default or normal mode as a default).
Regarding claim 19, Kim, as modified by Lee, teaches the method of claim 18.
Kim further teaches further comprising changing the default value stored in the nonvolatile memory region of the first memory device to the value corresponding to the mirrored mode set in the first mode register. (Kim, fig 5, 15, “[0064] The on-die mirroring mode of the present inventive concepts may be set by data received through at least one dedicated or predetermined pin. In an example embodiment, the on-die mirroring operation may be activated by setting a test mode register set (TMRS) through Basic Input/Output System (BIOS) settings in the system. [0106] The memory controller 200 may generate test mode register set (TMRS)/mode register (MR) setting information for the on-die mirroring operation of the memory 100 (Sll). The TMRS/MR setting information may be transmitted from the memory controller 200 to the memory 100. [0107] The memory 100 may receive the TMRS/MR setting information, and may set an on-die mirroring mode (S20).”; a memory controller 200 issues a “test mode register set” command; the command is received at the memory block 100; the mode register command has at least two states and is changed by the Command/Address TMRS command: one state (not using mirroring) to a second state (set on-die mirroring mode)).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, as modified by Lee, in view of Seo, et al, U.S. Patent Application Publication 2014/0241099 (“Seo”).
Regarding claim 3, Kim, as modified by Lee, teaches (Currently Amended) The memory module of claim 2.
Kim teaches wherein the first memory device further comprises a nonvolatile memory region configured to store a value to be set, during a power-up operation, in the first mode register, and (Kim, fig 5, 15, “[0064] The on-die mirroring mode of the present inventive concepts may be set by data received through at least one dedicated or predetermined pin. In an example embodiment, the on-die mirroring operation may be activated by setting a test mode register set (TMRS) through Basic Input/Output System (BIOS) settings in the system. [0106] The memory controller 200 may generate test mode register set (TMRS)/mode register (MR) setting information for the on-die mirroring operation of the memory 100 (Sll). The TMRS/MR setting information may be transmitted from the memory controller 200 to the memory 100. [0107] The memory 100 may receive the TMRS/MR setting information, and may set an on-die mirroring mode (S20).”; a memory controller 200 issues a “test mode register set” command; the command is received at the memory block 100; the mode register command has at least two states and is changed by the Command/Address TMRS command: one state (not using mirroring) to a second state (set on-die mirroring mode)).
Kim, as modified by Lee, does not explicitly teach wherein the nonvolatile memory region is configured to store the default value..
Seo teaches wherein the nonvolatile memory region is configured to store the default value. (Seo, fig 1, 2, “[0055] The nonvolatile memory 1310 may include one of various nonvolatile memories such as a read only memory (ROM), a programmable ROM (PROM),… The nonvolatile memory 1310 may store various information needed for an operation of the semiconductor memory device 1100. For example, the nonvolatile memory 1310 may store information for setting mode registers of the memory chips 1101 to 110n of the semiconductor memory device 1100.”; that values stored in a mode register can be ROM or NVM).
In view of the teachings of Seo it would have been obvious for a person of ordinary skill in the art to apply the teachings of Seo to Kim before the effective filing date of the claimed invention in order to teach memory operations. The teachings of Seo, in the same or in a similar field of endeavor with Kim, can combine explicitly programmable mode register with Kim’s implied programmable mode register. The two mode registers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 4, Kim, as modified by Lee and Seo, teaches the memory module of claim 3.
Kim further teaches wherein, based on the value corresponding to the mirrored mode being set in the first mode register based on the first command, the first memory device is further configured to (Kim, fig 5, 15, “[0064] The on-die mirroring mode of the present inventive concepts may be set by data received through at least one dedicated or predetermined pin. In an example embodiment, the on-die mirroring operation may be activated by setting a test mode register set (TMRS) through Basic Input/Output System (BIOS) settings in the system. [0106] The memory controller 200 may generate test mode register set (TMRS)/mode register (MR) setting information for the on-die mirroring operation of the memory 100 (Sll). The TMRS/MR setting information may be transmitted from the memory controller 200 to the memory 100. [0107] The memory 100 may receive the TMRS/MR setting information, and may set an on-die mirroring mode (S20).”; a memory controller 200 issues a “test mode register set” command; the command is received at the memory block 100; the mode register command has at least two states and is changed by the Command/Address TMRS command: one state (not using mirroring) to a second state (set on-die mirroring mode)).
Seo teaches change the default value stored in the nonvolatile memory region to the value corresponding to the mirrored mode. (Seo, fig 1, 2, “[0066] In the event that the program circuit 180 is a mode register, scramble information SI of memory chips 1101 to 11 On may be stored at a nonvolatile memory 1310 or otherwise generated in the memory controller 1300.”; that default values stored in a nonvolatile mode register can be changed).
In view of the teachings of Seo it would have been obvious for a person of ordinary skill in the art to apply the teachings of Seo to Kim before the effective filing date of the claimed invention in order to teach memory operations. The teachings of Seo, in the same or in a similar field of endeavor with Kim, can combine explicitly programmable mode register with Kim’s implied programmable mode register. The two mode registers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
