Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Arguments and amendments filed 11/19/2025 have been examined.
Claims 1, 3, 4, 7, 8, 10, 11, 15 and 18-20 have been amended;
and claims 5 and 6 have been canceled.
Thus, in this Office Action, Claims 1-4, 7-20 are currently pending.
This Office Action is Final.
Response to Arguments
Applicant's arguments filed regarding rejections under 35 USC 101 have been fully considered but they are not persuasive.
As to the argument: “Claims 1-20 are rejected under 35 USC § 101 as being directed to an abstract idea. To the extent the § 101 rejection remains applicable to the claims, as amended, Applicant respectfully traverses the rejection. Applicant amended claim 1 to recite a tangible practical application (i.e., "wherein each of the plurality of first wirings outputs a voltage level corresponding to a similarity between each of the plurality of pieces of first data and the second data"). Accordingly, Applicant respectfully submits that the claims recite patent eligible subject matter and requests that the rejection of claims 1-20 under 35 USC § 101 be withdrawn.”
The Examiner respectfully disagrees.
Applicant asserts that: “Applicant amended claim 1 to recite a tangible practical application (i.e., "wherein each of the plurality of first wirings outputs a voltage level corresponding to a similarity between each of the plurality of pieces of first data and the second data")”; however, simply nowhere does Applicant describe or explain how the generic “similarity” mentioned in claim is determined.Applicant asserts that the inventions direction towards “wherein each of the plurality of first wirings outputs a voltage level corresponding to a similarity between each of the plurality of pieces of first data and the second data” implies that the claims recite a “tangible practical application”; however, the test is not whether the claim is confined to a particular field of use or technological environment, see Intellectual Ventures ILLC v. Capital One Bank (USA), 792 F.3d 1363, 1366 (Fed. Cir. 2015) (“[a]n abstract idea does not become nonabstract by limiting the invention to a particular field of use or technological environment”). The relevant question, even at the first step of the Mayo/Alice analysis, is “whether the claims are directed to an improvement in computer functionality versus being directed to an abstract idea.” Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335 (Fed. Cir. 2016).
Here, the invention uses computer technology, but the Specification describes the claimed
solution as a scheme in collecting, storing and managing electronic records over time (see for
example specification para. [0048] “the cluster division unit 11 in the controller 3 performs
clustering for equally dividing the first data K into two clusters, while overlapping some of the plurality of pieces of first data K, and stores the first data K and the corresponding label in the storage unit 2 for each cluster (step S2).”). And collecting, storing, and organizing information describes the abstract idea to which Appellants’ claims are directed, not an improvement in computer technology. Erie Indemnity Co., 850 F.3d at 1328 (“the heart of the claimed invention lies in creating and using an index to search for and retrieve data ... an abstract concept”).
Thus, as the test for patent eligibility is not whether the claim is confined to a particular field of
use or technological environment, (see, again Intellectual Ventures ILLC v. Capital One Bank
(USA)), the Examiner is unconvinced the claims are directed to eligible subject matter and thus
this argument is moot.
Applicant’s arguments with respect to claim(s) and the prior art rejection under 35 USC 103 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4, 7-20 are rejected under 35 U.S.C. 101 because the claimed invention is
directed to an abstract idea without significantly more.
Claim 1 recites: (Step 2a, Prong One)
calculating a centroid value of distributed clusters.
The limitation of calculating a centroid value of distributed clusters, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting a generic processing circuitry, nothing in the claim element precludes the step from practically being performed in the mind. For example, but for the processing circuitry language, “calculating” in the context of this claim encompasses the user manually determining/calculating generic “centroid values” of generic clusters using generic “calculating” steps. Similarly, the limitation(s) of transmitting; transmitting; outputting; distributing; comparing; comparing/selecting, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. For example, but for the processing circuitry language, transmitting; transmitting; outputting; distributing; comparing; comparing/selecting in the context of this claim encompasses the user manually receiving generic “distributions” of generic data in generic lusters and preforming generic comparisons of centers and pieces of data to select generic similar data steps. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas (concepts performed in the human mind (including an observation, evaluation, judgment, opinion)).
Further, these concepts also recite “Certain Methods of Organizing Human Activity”; (such as
commercial or legal interactions (including agreements in the form of contracts; legal
obligations; advertising, marketing or sales activities or behaviors; business relations) where
performing generic comparing steps of generic clusters of data using generic calculations to find generically similar data is a method of human activity in commercial or legal interactions.
Accordingly, the claim recites an abstract idea.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites one additional element – using a processing circuitry/ information processing apparatus to perform both the transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps. The processor with a media in both steps is recited at a high level of generality (i.e., as a generic processor performing a generic computer function of “calculating”) such that it amounts no more than mere instructions to apply the exception using a generic computer component.
Accordingly, this additional element does not integrate the abstract idea into a practical
application because it does not impose any meaningful limits on practicing the abstract idea.
The claim is directed to an abstract idea. The claim does not include additional elements that
are sufficient to amount to significantly more than the judicial exception.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of a processing circuitry with an information processing apparatus to perform both the transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claim(s) is/are not patent eligible.
Referring to claim 2, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “determine the first data similar to the second data from the predetermined number of pieces of the selected first data”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “determine the first data similar to the second data from the
predetermined number of pieces of the selected first data” steps to perform both the aforementioned transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “determine the first data similar to the second data from the predetermined number of pieces of the selected first data” steps to perform both the aforementioned transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 3, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein a plurality of labels for identifying each of the plurality of pieces of first data are provided, and a label similar to the second data is determined based on a majority
decision of a number of the labels determined to be similar to the second data among the predetermined number of pieces of the first data”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein a plurality of labels for identifying each of the plurality of pieces of first data are provided, and a label similar to the second data is determined based on a majority decision of a number of the labels determined to be similar to the second data among the predetermined number of pieces of the first data” steps to perform both the aforementioned transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein a plurality of labels for identifying each of the plurality of pieces of first data are provided, and a label similar to the second data is determined based on a majority decision of a number of the labels determined to be similar to the second data among the predetermined number of pieces of the first data” steps to perform both the aforementioned transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 4, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein the processing circuitry is further configured to store the plurality of pieces of first data and the plurality of labels into the storage in association with each other, and a comparison process between the predetermined number of pieces of the first data and the second data is performed inside the storage”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein the processing circuitry is further configured to store the plurality of pieces of first data and the plurality of labels into the storage in association with each other, and a comparison process between the predetermined number of pieces of the first data and the second data is performed inside the storage” steps to perform both the aforementioned distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein the processing circuitry is further configured to store the plurality of pieces of first data and the plurality of labels into the storage in association with each other, and a comparison process between the predetermined number of pieces of the first data and the second data is performed inside the storage” steps to perform both the aforementioned transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 7, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein the storage performs writing and reading with respect to the plurality of memory cells with a page size determined according to the numbers of the plurality of first wirings and the plurality of second wirings, and the number of the first wirings is a number of pieces of data equal to or smaller than the page size”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein the storage performs writing and reading with respect to the plurality of memory cells with a page size determined according to the numbers of the plurality of first wirings and the plurality of second wirings, and the number of the first wirings is a number of pieces of data equal to or smaller than the page size” steps to perform both the aforementioned transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein the storage performs writing and reading with respect to the plurality of memory cells with a page size determined according to the numbers of the plurality of first wirings and the plurality of second wirings, and the number of the first wirings is a number of pieces of data equal to or smaller than the page size” steps to perform both the aforementioned transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 8, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein the plurality of first wirings are set to voltages corresponding to similarity between each bit in each of the plurality of pieces of first data and a corresponding bit of the second data”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein the plurality of first wirings are set to voltages
corresponding to similarity between each bit in each of the plurality of pieces of first data and a corresponding bit of the second data” steps to perform both the aforementioned transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein the plurality of first wirings are set to voltages corresponding to similarity between each bit in each of the plurality of
pieces of first data and a corresponding bit of the second data” steps to perform both the aforementioned transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 9, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein the predetermined number of pieces of the first data is selected based on the voltages of the plurality of first wirings”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein the predetermined number of pieces of the first data is selected based on the voltages of the plurality of first wirings” steps to perform both the aforementioned transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein the predetermined number of pieces of the first data is selected based on the voltages of the plurality of first wirings” steps to perform both the aforementioned transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 10, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein the processing circuitry is further configured to store the plurality of pieces of first data in the storage”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein the processing circuitry is further configured to store the plurality of pieces of first data in the storage” steps to perform both the transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein the processing circuitry is further configured to store the plurality of pieces of first data in the storage” steps to perform both the aforementioned transmitting; transmitting; outputting; distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 11, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein a plurality of memory strings that are connected to the plurality of first wirings and the plurality of second wirings and to which two or more of the memory cells are connected in series are provided, and the plurality of memory strings cause a current corresponding to similarity between each bit in each of the plurality of pieces of first data
and a corresponding bit of the second data to flow”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein a plurality of memory strings that are connected to the plurality of first wirings and the plurality of second wirings and to which two or more of the memory cells are connected in series are provided, and the plurality of memory strings cause a current corresponding to similarity between each bit in each of the plurality of pieces of first data
and a corresponding bit of the second data to flow” steps to perform both the distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein a plurality of memory strings that are connected to the plurality of first wirings and the plurality of second wirings and to which two or more of the memory cells are connected in series are provided, and the plurality of memory strings cause a current corresponding to similarity between each bit in each of the plurality of pieces of first data and a corresponding bit of the second data to flow” steps to perform both the aforementioned distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 12, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein the memory strings corresponding to the number of bits of the plurality of pieces of first data are connected to each of the plurality of first wirings, and each memory string causes a current corresponding to a comparison result between one bit of the corresponding first data and a corresponding bit of the second data to flow”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein the memory strings corresponding to the number of bits of the plurality of pieces of first data are connected to each of the plurality of first wirings, and each memory string causes a current corresponding to a comparison result between one bit of the corresponding first data and a corresponding bit of the second data to flow” steps to perform both the distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein the memory strings corresponding to the number of bits of the plurality of pieces of first data are connected to each of the plurality of first wirings, and each memory string causes a current corresponding to a comparison result between one bit of the corresponding first data and a corresponding bit of the second data to flow” steps to perform both the aforementioned distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 13, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein the storage compares each of the plurality of pieces of first
data with the second data in parallel”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein the storage compares each of the plurality of pieces of first data with the second data in parallel” steps to perform both the distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein the storage compares each of the plurality of pieces of first data with the second data in parallel” steps to perform both the aforementioned distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 14, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein the memory cell is a NAND flash memory cell”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein the memory cell is a NAND flash memory cell” steps to perform both the distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein the memory cell is a NAND flash memory cell” steps to perform both the aforementioned distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 15, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein each of the plurality of memory cells stores a corresponding
bit of the first data by a change in a resistance value”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein each of the plurality of memory cells stores a corresponding bit of the first data by a change in a resistance value” steps to perform both the distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein each of the plurality of memory cells stores a corresponding bit of the first data by a change in a resistance value” steps to perform both the aforementioned distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 16, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein by driving each of the plurality of second wirings with time shifted according to the second data, a current corresponding to an inner product value of each bit in each of the plurality of pieces of first data and corresponding bits of the second data is caused to flow through the plurality of first wirings”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein by driving each of the plurality of second wirings with time shifted according to the second data, a current corresponding to an inner product value of each bit in each of the plurality of pieces of first data and corresponding bits of the second data is caused to flow through the plurality of first wirings” steps to perform both the distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein by driving each of the plurality of second wirings with time shifted according to the second data, a current corresponding to an inner product value of each bit in each of the plurality of pieces of first data and corresponding bits of the second data is caused to flow through the plurality of first wirings” steps to perform both the aforementioned distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 17, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein the storage is a cross point-type memory.”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein the storage is a cross point-type memory.” steps to perform both the distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein the storage is a cross point-type memory.” steps to perform both the aforementioned distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 18, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein the processing circuitry is configured to repeat a process of distributing the plurality of pieces of first data into two clusters by soft clustering using non-negative matrix factorization (NMF)”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein the processing circuitry is configured to repeat a process of distributing the plurality of pieces of first data into two clusters by soft clustering using non-negative matrix factorization (NMF)” steps to perform both the distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein the processing circuitry is configured to repeat a process of distributing the plurality of pieces of first data into two clusters by soft clustering using non-negative matrix factorization (NMF)” steps to perform both the aforementioned distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 19, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “wherein the processing circuitry is configured to repeat a process of
generating one cluster using principal component analysis (PCA) and distributing the plurality of pieces of first data into two clusters”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “wherein the processing circuitry is configured to repeat a process of generating one cluster using principal component analysis (PCA) and distributing the plurality of pieces of first data into two clusters” steps to perform both the distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “wherein the processing circuitry is configured to repeat a process of generating one cluster using principal component analysis (PCA) and distributing the plurality of pieces of first data into two clusters” steps to perform both the aforementioned distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Referring to claim 20, (Step 2a, Prong One) this further merely performs an additional abstract
mental step of “a host device configured to determines a label similar to the second data from among a predetermined number of labels corresponding to the first data”.
(Step 2a, Prong Two)
This judicial exception is not integrated into a practical application. In particular, the claim only
recites the additional elements of “a host device configured to determines a label similar to the second data from among a predetermined number of labels corresponding to the first data” steps to perform both the distributing; comparing; comparing/selecting and calculating steps. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
(Step 2b)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. As discussed above with respect to integration of the abstract
idea into a practical application, the additional element of using “a host device configured to determines a label similar to the second data from among a predetermined number of labels corresponding to the first data” steps to perform both the aforementioned distributing; comparing; comparing/selecting and calculating steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
The claim(s) is/are not patent eligible.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Singh et al., US Pub. No. 2021/0397610, in view of Bordawekar et al., US Pub. No. 2024/0220488 A1, in view of Lu et al., Article: “An analog online clustering circuit in 130nm CMOS”; 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) (2013, Page(s): 177-180) Univ. of Tennessee, Knoxville, TN, USA.
As to claim 1, Singh discloses:
an information processing apparatus comprising
a storage; and
processing circuitry
(Singh Fig. 1 & Fig. 2)
and wherein the processing circuitry is configured to:
calculate a centroid value of each of the finally distributed clusters;
(Singh teaches This for a given cluster, determining a centroid for the given cluster, i.e. “calculate a centroid value of each of the finally distributed clusters” see [0016] In one case, the method may comprise filtering the clustered vector representations prior to generating the
paired data samples. This may comprise, for a given cluster, determining a centroid for the given cluster in the clustered vector representations and unassigning vector representations
of queries for the given cluster that are more than a predefined distance from the centroid.)
compare a center of each of the plurality of clusters with second data and determine a cluster having a centroid value most similar to the second data as the search cluster; and
(Singh teaches comparing based on a distance to the centroid of the query cluster, i.e. “determines a cluster having a centroid value most similar to the second data as a search cluster” [0066] As part of block 420 in FIG. 4, the groups of queries that correspond to the response clusters (e.g., 532, 534) may be further processed to refine the group membership. For example, each response cluster may be taken in tum and the response points or vectors in the clusters identified; the query indexes that correspond to these response points or
vectors ( e.g., response vector i and corresponding query I from the data set 510) are then grouped as per the response clusters. In certain cases, the query vectors within each
group may themselves be clustered. This may be used to select one of the group as the canonical query for the group, e.g. based on a distance to the centroid of the query cluster.;
see also [0067] These filtering operations may then be followed by a reassignment operation
whereby the previously unassigned vector representations are reassigned to a closest cluster.)
compare each of the plurality of pieces of first data included in the search cluster with the second data to select one or more predetermined numbers of the first data similar to the second data
(Singh teaches filtering/grouping based on removing transcriptions based on threshold from the cluster centroid/semantic distances/similarity scores, i.e. comparing pieces of data to select one or more predetermined numbers of the first data similar see [0092] The grouping operation may be repeated multiple times. In one variation, the method comprises removing transcriptions that are farther than a certain threshold from the cluster centroid; breaking down clusters that are smaller than a certain threshold; and assigning individual transcriptions from previous steps to their closest cluster.;
see also [0021] parsing the initial data representing the query and at least data derived from the output sequence data with a named entity recognizer and selecting an output sequence based on a comparison between named entities in the parsed data. These sets of post-processing operations, which may be applied individually or (preferably) together, may further improve the output that is selected for query processing, e.g. by ensuring that elements of the original input query are retained to provide an appropriate response and/or selecting one of a set of
possible outputs produced by the neural network architecture that maximizes the likelihood of responding with an accurate and appropriate query response.;
see also [0092] In another variation the method comprises generating pairs by assigning the transcriptions within each cluster with a frequency larger than a certain threshold as the target transcriptions and the rest of the transcriptions in the cluster as source transcriptions;
dropping pairs where the target transcription does not have all the entity tags available in the source transcription; and dropping pairs with a semantic distance larger than a threshold.;
see also [0095] In another comparative example, semantic distances between pairs of
queries may be compared (e.g., n2 pairs for n queries) and the pairs may then be filtered based on a semantic distance threshold ( e.g., only pairs with a similarity score above a predefined threshold are kept).).
Singh does not disclose:
equally distribute the first data to a plurality of clusters while overlapping some of the first data among the plurality of pieces of first data and repeating distribution to a new set of a plurality of clusters until a number of pieces of the first data included in each of the distributed clusters becomes equal to or less than n;
however, Bordawekar discloses:
equally distribute the first data to a plurality of clusters while overlapping some of the first data among the plurality of pieces of first data and repeating distribution to a new set of a plurality of clusters until a number of pieces of the first data included in each of the distributed clusters becomes equal to or less than n;
(Bordawekar teaches each candidate set equals the number of unique values in a given column of the table and also using size thresholds, i.e. distributing a “number of pieces of the first data included in each of the distributed clusters becomes equal to or less than a predetermined limit number” see Fig. 3B item 328 “Organize the model by candidate set, where each set corresponds to a column of the table and a size of each candidate set equals the number of unique values in a given column of the table”
See also [0067] a candidate set is obtained and, if the size of the set is greater than a predefined threshold, the candidates are clustered into a predefined number of clusters
(the threshold and the number of clusters per candidate set are pre-defined parameters). After clustering the candidate set, the cluster ID is added to each (token, vector) pair and
the centroid vector of each cluster is calculated.).
It would have been obvious to one having ordinary skill in the art at the time the time of the effective filing date to apply table/size thresholds to clusters as taught by Bordewekar to the system of Singh since it was known in the art that classification/clustering systems provide a threshold may be changed over time by monitoring the performance of the system (in terms of memory usage, processing time, and the like) and adjusting the threshold to optimize the performance), and based on the available computing power as described below where clustering parameters, such as the number of unique elements to cluster and the number of clusters may change over time based on monitoring performance (in terms of memory usage, processing time, and the like) and quality of results (results of a SQL query with and without clustering) where in one or more embodiments, the threshold is based on the performance of the computer; i.e., the higher the performance of the computer, the higher the threshold, such that clustering is invoked for higher performing computers where for example, if using a standard CPU, use a lower threshold, but if using a single instruction, multiple data (SIMD) unit or other high powered unit, use a higher threshold where this is because the cost of invoking the accelerator is not justified by the performance gain of clustering. (Bordewekar [0068]).
Singh/Bordewekar do not disclose:
wherein the storage includes:
a plurality of memory cells that store each bit of first data;
a plurality of first wirings that are connected to the plurality of memory cells
and transmit a plurality of pieces of first data included in a search cluster; and
a plurality of second wirings that are connected to the plurality of memory
cells and transmit second data including a plurality of bits,
wherein each of the plurality of first wirings outputs a voltage level corresponding to
a similarity between each of the plurality of pieces of first data and the second data,
wherein a number of the first wirings is n, n being an integer greater than 1,
However, Lu discloses:
wherein the storage includes:
a plurality of memory cells that store each bit of first data;
(Lu p. 177, “Fig. 1. The architecture of the proposed analog online clustering circuit, including an 8 × 4 array of memory and distance computation cells (one of them is shown in detail), memory adaptation circuits common to each row, and loser-take-all circuits common to each column.”)
a plurality of first wirings that are connected to the plurality of memory cells
and transmit a plurality of pieces of first data included in a search cluster; and
(Lu p. 177 sec. I “This paper describes the implementation of an ASP system realizing an online k-means clustering algorithm, widely-used in feature extraction, pattern recognition, data compression, and other applications. It infers the underlying data pattern by capturing the regularity of it [5]. A vector quantizer (VQ) searches a set of stored centroids (templates) for the one nearest to the input vector.”;
See also Fig. 1 and p. 177 sec. II “A time-domain loser-take-all (LTA) network common to the
columns searches for the single centroid k with minimum distance to x and sets SELk to high.”)
a plurality of second wirings that are connected to the plurality of memory
cells and transmit second data including a plurality of bits,
(Lu Fig. 1 and p. 177, “Fig. 1. The architecture of the proposed analog online clustering circuit, including an 8 × 4 array of memory and distance computation cells (one of them is shown in detail), memory adaptation circuits common to each row, and loser-take-all circuits common to each column.”)
wherein each of the plurality of first wirings outputs a voltage level corresponding to
a similarity between each of the plurality of pieces of first data and the second data,
(Lu teaches measures of similarity/“distance computation cells” and voltage output from the Memory Adaptation (MA) Circuit,
See abstract: “An analog clustering circuit is presented. It is capable of inferring the underlying pattern and extracting the statistical parameters from the input vectors, as well as providing measures of similarity based on both mean and variance.”;
See p. 177: “The core of the prototype is an array of memory and distance computation cells (MDCs). The 4 columns form 4 centroids, each with 8 dimensions. The MDC consists of two analog memories (FGMs) and a distance computation block (D3).”;
See also p. 179 sec. D: “D. Memory Adaptation (MA) Circuit The error currents between the input and the best-matching centroids’ memory values are passed to the MA circuits. Each
row of the MDC cells shares two MA circuits, for mean and variance memory respectively. The simplified schematic and timing diagram is shown in Fig. 4. The MA circuit utilizes the
charging and discharging of capacitor to realize current-to-pulse- width conversion. The voltage Vp is first discharged from Vdd by the input current for a fixed period of t1, then ramped up by the external voltage VRAMP at the bottom plate of C1, until Vp crosses Vdd at t2. The update pulse is defined by t2-t1, and is proportional to the input error current, allowing the memory values to adapt to the moving averages. While the MA determines the magnitude of memory adaptation, the direction of adaptation for mean memory is determined by the Sgn output of the MDC. For variance memory, an absolute value circuit in Fig. 2 is added to the MA block, generating both the unsigned error current and the direction of adaptation.;
see also Fig. 6. Transfer characteristics of the D3 block. The markers are the measured
data and the dashed lines are curves fitted to the quadratic form a(x-10)2, where
a is the fitting parameter.)
wherein a number of the first wirings is n, n being an integer greater than 1,
(Lu teaches wire-summing using a analog online clustering circuit with a set number of wires, i.e.” wherein a number of the first wirings is n, n being an integer greater than 1”, see Fig. 1; see also p. 177: “Fig. 1. The architecture of the proposed analog online clustering circuit, including an 8 × 4 array of memory and distance computation cells (one of
them is shown in detail), memory adaptation circuits common to each row, and loser-take-all circuits common to each column.”;see also p. 177: “The Euclidean distances between x and the centroid yj is obtained
by wire-summing the D3’s output currents along the columns,”)
It would have been obvious to one having ordinary skill in the art at the time the time of the effective filing date to apply similarity voltages as taught by Lu to the system of Singh/ Bordewekar since it was known in the art that classification/clustering systems provide an architecture for a clustering circuit where signal processing is implemented in current mode to allow efficient arithmetic operations and wide linear range with an array of memory and distance
computation cells (MDCs) using 4 columns form 4 centroids, each with 8 dimensions where the MDC consists of two analog memories (FGMs) and a distance computation block (D3) and the
FGM stores the centroid mean yij and variance yij var, and is accessible and programmable from off-chip in test mode where the D3 block provides 3 distance metrics between the input vector and the local centroid, necessary for different operation modes. (Lu, Sec. II p. 177).
As to claim 2, Singh as modified discloses the information processing apparatus according to claim 1, wherein the processing circuitry is further configured to:
determine the first data similar to the second data from the predetermined number of pieces of the selected first data
(Singh teaches grouping based on transcriptions based on threshold from the cluster centroid/semantic distances/similarity scores, i.e. determine the first data similar to the second data
see [0092] The grouping operation may be repeated multiple times. In one variation, the method comprises removing transcriptions that are farther than a certain threshold from the cluster centroid; breaking down clusters that are smaller than a certain threshold; and assigning individual transcriptions from previous steps to their closest cluster.;
see also [0021] parsing the initial data representing the query and at least data derived from the output sequence data with a named entity recognizer and selecting an output sequence based on a comparison between named entities in the parsed data. These sets of post-processing operations, which may be applied individually or (preferably) together, may further improve the output that is selected for query processing, e.g. by ensuring that elements of the original input query are retained to provide an appropriate response and/or selecting one of a set of
possible outputs produced by the neural network architecture that maximizes the likelihood of responding with an accurate and appropriate query response.;
see also [0092] In another variation the method comprises generating pairs by assigning the transcriptions within each cluster with a frequency larger than a certain threshold as the target transcriptions and the rest of the transcriptions in the cluster as source transcriptions;
dropping pairs where the target transcription does not have all the entity tags available in the source transcription; and dropping pairs with a semantic distance larger than a threshold.;
see also [0095] In another comparative example, semantic distances between pairs of
queries may be compared (e.g., n2 pairs for n queries) and the pairs may then be filtered based on a semantic distance threshold ( e.g., only pairs with a similarity score above a predefined threshold are kept).).
As to claim 19, Singh as modified discloses the information processing apparatus according to claim 1, wherein the processing circuitry is further configured to repeat a process of generating one cluster using principal component analysis (PCA) and distributing the plurality of pieces of first data into two clusters (Singh [0062] In certain variations, the vector pairs 522, 524 ( or
single combined vector) may be further processed prior to clustering. For example, in certain implementations, a dimensionality reduction pre-processor may be applied. The dimensionality reduction pre-processor may comprise an operation of projecting the embedding vectors to a lower dimensionality vector space. For example, in one case, principal component analysis (PCA) may be performed on the initial vector pairs 522, 524 to determine a set of linear
variational components that may be used to decompose the vector representations. In one case, a subset of linear variational components may be selected that represent a certain predefined amount of variance in the data represented by the initial vector pairs 522, 524. The vector representations may be reduced via PCA as a single concatenated vector or
separately. For example, the data formed by the query vectors may be processed by a PCA fitting function and the subset of linear variational components that represent 95% of the variance may be selected, wherein the elements of the transformed output represent the different amounts of each of the subset of linear variational components. This operation may help reduce the dimensionality from a higher dimensional representation (e.g., 768 elements) to a lower dimensional representation (e.g., a few).
Claim(s) 3-4 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Singh et al., US Pub. No. 2021/0397610, in view of Bordawekar et al., US Pub. No. 2024/0220488 A1, in view of Lu et al., Article: “An analog online clustering circuit in 130nm CMOS”; 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) (2013, Page(s): 177-180) Univ. of Tennessee, Knoxville, TN, USA, in view of Taljanovic et al., US Pub. No. 2016/0070780.
As to claim 3, Singh/ Bordewekar/Lu do not disclose:
wherein a plurality of labels for identifying each of the plurality of pieces of first data are provided, and a label similar to the second data is determined based on a majority
decision of a number of the labels determined to be similar to the second data among the predetermined number of pieces of the first data;
However, Taljanovic discloses:
the information processing apparatus according to claim 2,
wherein a plurality of labels for identifying each of the plurality of pieces of first data are provided, and a label similar to the second data is determined based on a majority
decision of a number of the labels determined to be similar to the second data among the predetermined number of pieces of the first data
(Taljanovic teaches determining majority destination folder for the closest data cluster, i.e. “a label similar to the second data is determined based on majority decision of the number of the labels” [0047] In operation 518, the analyzer 120, or more specifically, the path determination engine 420, may examine the destination folders of the vector data points in the data cluster (described further in FIG. 7). All data points may have a destination folder. In some embodiments, the data points without a destination folder may be removed prior to clustering.
The majority destination may be chosen from one or more destination folders. The analyzer 120 may then determine if there is a majority destination folder for the closest data cluster. In one embodiment, the majority destination may be determined by the most destination folders within the data cluster. For example, if fifty vector data points exist in the data cluster, and twenty-three of the vector data points are directed to the media folder, and thirteen of the vector data points are directed to the images folder, then the majority destination folder may be the media folder even if there is not an overwhelming majority.;
See also [0006] The system may also have a file system with the capability of saving the incoming file to a save folder. The system may also have an analyzer with the capability of creating one or more data points from the file metadata, grouping the data points into data clusters, locating a closest data cluster to the data point derived from the file save request, determining a majority destination folder for the closest data cluster, and selecting the majority destination folder as the save folder.)
It would have been obvious to one having ordinary skill in the art at the time the time of the effective filing date to apply majority decisions to clusters as taught by Taljanovic to the system of Singh/ Bordewekar/Lu since it was known in the art that classification/clustering systems provide an analyzer/the path determination engine which may examine the destination folders of the vector data points in the data cluster where all data points may have a destination folder and the data points without a destination folder may be removed prior to clustering where a majority destination may be chosen from one or more destination folders where the analyzer may then determine f there is a majority destination folder for the closest data cluster where the majority destination may be determined by the most destination folders within the data cluster where for example, if fifty vector data points exist in the data cluster, and twenty-three of the vector data points are directed to the media folder, and thirteen of the vector data points are directed to the images folder, then the majority destination folder may be the media folder even if there is not an overwhelming majority. (Taljanovic [0047]).
As to claim 4, Singh as modified discloses the information processing apparatus according to claim 3, wherein the processing circuitry is further configured to store the plurality of pieces of first data and the plurality of labels into the storage in association with each other, and a comparison process between the predetermined number of pieces of the first data and the second data is performed inside the storage
(Singh teaches named entity recognition and tag replacement, i.e. store the plurality of pieces of first data and the plurality of labels into a storage see [0072] In certain cases, if named entity recognition and tag replacement is performed as described above, the original text tokens may be stored in association with ( e.g., together with or indexed by) the processed text portions, such as pairs 512 and 514. Following generation of the data set 550 for training the machine learning system, the original text tokens may be written back to the data samples. For example, following named entity parsing the query data 512 may comprise [["What, is, the, weather, in, <PLACE>, ?" ], "Toronto" ], where clustering is performed on the first list element and then, within the text tokens within one of the target and source data 552, 554, the original token "Toronto" is inserted back into the set of tokens in place of <PLACE>, i.e. becomes again ["What, is, the, weather, in, "Toronto", ?" ] . This is performed for both the source and target data samples 512, 514 with the same replacement being performed, i.e. "Toronto" is inserted in place of <PLACE> tags in both the source and target data samples 512, 514. This may also help to augment the training data to improve accuracy, for example, as source query samples with different named entities but a common processed form may be
mapped to a target query sample with a further different named entity and then different versions may be created using different versions of the original named entities. For
example, all the queries in data 601 and 603 may be mapped to one target data sample to initially generate sixteen sourcetarget pairs, and then all the original <DATE> and <LOCATION>
named entities, corresponding to different dates and locations where there may be many more than sixteen entities, may be inserted into different copies of the sixteen source-target pairs to generate more than sixteen training samples.).
As to claim 20, Taljanovic as modified discloses the information processing apparatus according to claim 2, further comprising:
a host device configured to determines a label similar to the second data from among
a predetermined number of labels corresponding to the first data.
(Taljanovic teaches determining majority destination folder for the closest data cluster, i.e. “determines a label similar to the second data from among a predetermined number of labels corresponding to the first data” [0047] In operation 518, the analyzer 120, or more specifically, the path determination engine 420, may examine the destination folders of the vector data points in the data cluster (described further in FIG. 7). All data points may have a destination folder. In some embodiments, the data points without a destination folder may be removed prior to clustering. The majority destination may be chosen from one or more destination folders. The analyzer 120 may then determine if there is a majority destination folder for the closest data cluster. In one embodiment, the majority destination may be determined by the most destination folders within the data cluster. For example, if fifty vector data points exist in the data cluster, and twenty-three of the vector data points are directed to the media folder, and thirteen of the vector data points are directed to the images folder, then the majority destination folder may be the media folder even if there is not an overwhelming majority.;
See also [0006] The system may also have a file system with the capability of saving the incoming file to a save folder. The system may also have an analyzer with the capability of creating one or more data points from the file metadata, grouping the data points into data clusters, locating a closest data cluster to the data point derived from the file save request, determining a majority destination folder for the closest data cluster, and selecting the majority destination folder as the save folder.)
Claim(s) 8-10, 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Singh et al., US Pub. No. 2021/0397610, in view of Bordawekar et al., US Pub. No. 2024/0220488 A1, in view of Lu et al., Article: “An analog online clustering circuit in 130nm CMOS”; 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) (2013, Page(s): 177-180) Univ. of Tennessee, Knoxville, TN, USA, in view of Taljanovic et al., US Pub. No. 2016/0070780, in view of Garzon et al., Article: “AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing”; E. Garzón, M. Lanuzza, A. Teman, and L. Yavits, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 13, no. 1, pp. 408–421, 2023.
As to claim 8, Singh/Bordawekar/Lu/Taljanovic do not disclose:
wherein the plurality of first wirings are set to voltages corresponding to similarity between each bit in each of the plurality of pieces of first data and a corresponding bit of the second data;
However, Garzon as modified discloses the information processing apparatus according to claim 4, wherein the plurality of first wirings are set to voltages corresponding to similarity between each bit in each of the plurality of pieces of first data and a corresponding bit of the second data
(Garzon p. 415: “F. Approximate Search CAM (ACAM) Multiple applications, including text processing (e.g., text retrieval, signal processing, computational biology [31], [32], [33], and genome analysis [9], [15]), require approximate rather than exact search, for example to tolerate errors, or find similarities among erroneous or ambiguous data patterns. In approximate search, if the difference between a stored pattern and the query pattern is below a certain predefined threshold, the compare result should still be considered a “match”. AM4 can support approximate search by adjusting the MLS sampling time, using the speed of the match line discharge as a measure of Hamming distance. To make the operation mode robust, an ML can be amended by an NMOS discharge transistor with a configurable gate voltage. In such a configuration, the approximate search utilizes the matchline charge redistribution rather than its rise or fall time. By tuning this gate voltage (possibly automatically), we can set a desired level of Hamming distance without adjusting the ML sampling time [34], [35].”).
It would have been obvious to one having ordinary skill in the art at the time the time of the effective filing date to apply similarity according to voltage as taught by Garzon to the system of Singh/ Bordewekar/Lu/Taljanovic since it was known in the art that similarity determining systems provide approximate rather than exact search, for example to tolerate errors, or find similarities among erroneous or ambiguous data patterns where in approximate search, if the difference between a stored pattern and the query pattern is below a certain predefined threshold, the compare result should still be considered a “match” where AM4 can support approximate search by adjusting the MLS sampling time, using the speed of the matchline discharge as a measure of Hamming distance and to make the operation mode robust, an ML can be amended by an NMOS discharge transistor with a configurable gate voltage. In such a configuration, the approximate search utilizes the matchline charge redistribution rather than its rise or fall time. By tuning this gate voltage (possibly automatically), we can set a desired level of Hamming distance without adjusting the ML sampling time (Garzon p. 415).
As to claim 9, Garzon as modified discloses the information processing apparatus according to claim 8, wherein the predetermined number of pieces of the first data is selected based on the voltages of the plurality of first wirings
(Garzon p. 415: “F. Approximate Search CAM (ACAM) Multiple applications, including text processing (e.g., text retrieval, signal processing, computational biology [31], [32], [33], and genome analysis [9], [15]), require approximate rather than exact search, for example to tolerate errors, or find similarities among erroneous or ambiguous data patterns. In approximate search, if the difference between a stored pattern and the query pattern is below a certain predefined threshold, the compare result should still be considered a “match”. AM4 can support approximate search by adjusting the MLS sampling time, using the speed of the match line discharge as a measure of Hamming distance. To make the operation mode robust, an ML can be amended by an NMOS discharge transistor with a configurable gate voltage. In such a configuration, the approximate search utilizes the matchline charge redistribution rather than its rise or fall time. By tuning this gate voltage (possibly automatically), we can set a desired level of Hamming distance without adjusting the ML sampling time [34], [35].”).
As to claim 10, Garzon as modified discloses the information processing apparatus according to claim 4, wherein the processing circuitry is further configured to store the plurality of pieces of first data in the storage
(Garzon teaches various storage operation/memories, i.e. “to store the plurality of pieces of first data in the storage”
See p. 415 E. Content Addressable Memory (CAM) and Ternary CAM (TCAM) In addition to its functionality as an AP, AM4 can be operated in CAM/TCAM mode. Operation in CAM mode is
straightforward, according to the search and write operations, described previously. To support TCAM mode, either the search (query) pattern bits or the bits of the data patterns
stored in the MRAM crossbar can be “don’t care” in addition to conventional ‘1’ and ‘0’ values. To store a “don’t care”, a ‘0’ is written to both top and bottom MTJs of an AM4 cell, presenting a LRS through both top and bottom discharge paths to the ML. During a compare, the “don’t care”-written cell will not affect the result of the operation (match or mismatch). To create a “don’t care” search pattern bit, we simply mask it off, as presented above.;
see also p. 419: “To our knowledge, AM4 is the first solution that converts a MRAM crossbar designed for random access storage, into an associative processor. We achieve that without altering the MRAM core, only by manipulating data and amending the peripheral circuitry.”).
As to claim 14, Garzon as modified disclose the information processing apparatus according to claim 11, wherein the memory cell is a NAND flash memory cell
(Garzon p. 412: “The resistive path through the serially connected MRAM bitcells serves as a NAND-style Match Line (ML), enabling the NAND CAM compare functionality.”;
See also p. 409: “The contributions of this work are summarized as follows: • AM4 is the first NAND-type CAM based on a random-access magnetoresistive crossbar.”;).
As to claim 15, Garzon as modified discloses the information processing apparatus according to claim 4, wherein each of the plurality of memory cells stores a corresponding bit of the first data by a change in a resistance value (Garzon p. 412: “The resistive path through the serially connected MRAM bitcells serves as a NAND-style Match Line (ML), enabling the NAND CAM compare functionality. We further label the stored states as ‘1’ and ‘0’ according to the resistances of the left (now top) and right (now bottom) DMTJs. A ‘0’ is stored by writing parallel spin (LRS) into the top DMTJ and anti-parallel spin (HRS) into the bottom DMTJ.
The complementary state (HRS, LRS) is considered a ‘1’.”).
As to claim 16, Garzon as modified discloses the information processing apparatus according to claim 15, wherein by driving each of the plurality of second wirings with time shifted according to the second data, a current corresponding to an inner product value of each bit in each of the plurality of pieces of first data and corresponding bits of the second data is caused to flow through the plurality of first wirings
(Garzon teaches adjusting the MLS sampling time i.e. “time shifting” see p. 415: “F. Approximate Search CAM (ACAM) Multiple applications, including text processing (e.g., text retrieval, signal processing, computational biology [31], [32],
[33], and genome analysis [9], [15]), require approximate rather than exact search, for example to tolerate errors, or find similarities among erroneous or ambiguous data patterns. In approximate search, if the difference between a stored pattern and the query pattern is below a certain predefined threshold, the compare result should still be considered a “match”. AM4 can support approximate search by adjusting the MLS sampling time, using the speed of the matchline discharge as a measure of Hamming distance.”).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Singh et al., US Pub. No. 2021/0397610, in view of Bordawekar et al., US Pub. No. 2024/0220488 A1, in view of Lu et al., Article: “An analog online clustering circuit in 130nm CMOS”; 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) (2013, Page(s): 177-180) Univ. of Tennessee, Knoxville, TN, USA, in view of Taljanovic et al., US Pub. No. 2016/0070780, in view of Tanzawa et al., US Pub. No. 2003/0112662 A1.
As to claim 7, Singh/Bordawekar/Lu/Taljanovic do not disclose:
the information processing apparatus according to claim 4, wherein the storage performs writing and reading with respect to the plurality of memory cells with a page size determined according to the numbers of the plurality of first wirings and the plurality of second wirings, and the number of the first wirings is a number of pieces of data equal to or smaller than the page size;
However, Tarzawa discloses:
the information processing apparatus according to claim 4,
wherein the storage performs writing and reading with respect to the plurality of memory cells with a page size determined according to the numbers of the plurality of first wirings and the plurality of second wirings, and the number of the first wirings is a number of pieces of data equal to or smaller than the page size
(Tanzawa [0184] In page read, the data-line 3' for read and the SenseAmp 7' for read are equal to the page size, while the data-line 4' for program and verify, the SenseAmp 8' for
program and verify, and the program circuit 9' are smaller than the page size.;
see also [0020] FIG. 2 is a circuit diagram showing part of a memory cell array obtained by arraying memory cell transistors shown in FIG. 1 in a matrix for explaining the
conventional nonvolatile semiconductor memory;
see also claim 2: “data-lines for read and data-lines for program and verify which are arranged in a region between said first and second nonvolatile memory banks and selectively connected
to bit-lines of said first and second nonvolatile memory banks, the number of data-lines for read is Nl, and the number of data-lines for program and verify is N2 that is smaller than Nl;
sense amplifiers for read connected to said data-lines for read, the number of sense amplifiers for read is Nl; sense amplifiers for program and verify connected to said data-lines for program and verify, the number of sense amplifiers for program and verify is N2; and”)
It would have been obvious to one having ordinary skill in the art at the time the time of the effective filing date to apply page size / data line limits as taught by Tanzawa to the system of Singh/ Bordewekar/Lu/Taljanovic since it was known in the art that storage systems provide that a page read, the data-line for read and the SenseAmp for read are equal to the page size, while the data-line for program and verify, the SenseAmp for program and verify, and the program circuit are smaller than the page size where this can reduce the pattern-occupied areas of the data-line for program and verify, the SenseAmp for program and verify, and the program circuit, thereby decreasing the chip cost. (Tanzawa [0184-0185]).
Claim(s) 11-13, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Singh et al., US Pub. No. 2021/0397610, in view of Bordawekar et al., US Pub. No. 2024/0220488 A1, in view of Lu et al., Article: “An analog online clustering circuit in 130nm CMOS”; 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) (2013, Page(s): 177-180) Univ. of Tennessee, Knoxville, TN, USA, in view of Taljanovic et al., US Pub. No. 2016/0070780, in view of Jeong, Y.; Lee, J.; Moon, J.; Shin, J. H.; Lu, W. D. K-means Data Clustering with Memristor Networks. Nano Lett. 2018, 18, 4447– 4453, DOI: 10.1021/acs.nanolett.8b01526.
As to claim 11, Singh/Bordawekar/Lu/Taljanovic do not disclose:
wherein a plurality of memory strings that are connected to the plurality of first wirings and the plurality of second wirings and to which two or more of the memory cells are connected in series are provided, and the plurality of memory strings cause a current corresponding to similarity between each bit in each of the plurality of pieces of first data
and a corresponding bit of the second data to flow;
However, Jeong discloses:
The information processing apparatus according to claim 4, wherein a plurality of memory strings that are connected to the plurality of first wirings and the plurality of second wirings and to which two or more of the memory cells are connected in series are provided, and the plurality of memory strings cause a current corresponding to similarity between each bit in each of the plurality of pieces of first data and a corresponding bit of the second data to flow
(Jeong p. 4448: “The first process, the search step, is to find the nearest centroid for a given input and assign the input to the associated cluster. It is then followed by the second process, the update (learning) step, which updates the selected centroid coordinates due to changes in the cluster composition. The crossbar structure as shown in Figure 1b is extremely efficient in implementing vector-matrix multiplication operation, which is one of the core operations1−4 in neuromorphic systems, through simple Ohm’s raw and Kirchhoff’s law, i.e., the current (or charge) collected at each output neuron (In = Σj Vj·Wjn) represents the dot product of the input voltage vector and the stored conductance vector. In general, vector−vector dot-product operation provides a good indication of the similarity between the input vector and the stored vector, and thus can be viewed as performing a pattern-matching operation and is commonly used in machine-learning algorithms, particularly if the stored feature vectors can be readily normalized. However, algorithms such as K-means rely on finding the exact Euclidean distances, not just the similarity between the vectors, to decide the winning neurons and perform the updates.”).
It would have been obvious to one having ordinary skill in the art at the time the time of the effective filing date to apply page size / data line limits as taught by Jeong to the system of Singh/ Bordewekar/Lu/Taljanovic since it was known in the art that similarity determining systems provide a crossbar structure as which is extremely efficient in implementing vector-matrix multiplication operation, which is one of the core operations in neuromorphic systems, through simple Ohm’s raw and Kirchhoff’s law, i.e., the current (or charge) collected at each output neuron (In = Σj Vj·Wjn) represents the dot product of the input voltage vector and the stored conductance vector where in general, vector−vector dot-product operation provides a good indication of the similarity between the input vector and the stored vector, and thus can be viewed as performing a pattern-matching operation and is commonly used in machine-learning algorithms. (Jeong p.4448).
As to claim 12, Jeong as modified discloses the information processing apparatus according to claim 11, wherein the memory strings corresponding to the number of bits of the plurality of pieces of first data are connected to each of the plurality of first wirings, and each memory string causes a current corresponding to a comparison result between one bit of the corresponding first data and a corresponding bit of the second data to flow
(Jeong p. 4448: “The first process, the search step, is to find the nearest centroid for a given input and assign the input to the associated cluster. It is then followed by the second process, the update (learning) step, which updates the selected centroid coordinates due to changes in the cluster composition. The crossbar structure as shown in Figure 1b is extremely efficient in implementing vector-matrix multiplication operation, which is one of the core operations1−4 in neuromorphic systems, through simple Ohm’s raw and Kirchhoff’s law, i.e., the current (or charge) collected at each output neuron (In = Σj Vj·Wjn) represents the dotproduct of the input voltage vector and the stored conductance vector. In general, vector−vector dot-product operation provides a good indication of the similarity between the input vector and the stored vector, and thus can be viewed as performing a pattern-matching operation and is commonly used in machine-learning algorithms, particularly if the stored feature vectors can be readily normalized. However, algorithms such as K-means rely on finding the exact Euclidean distances, not just the similarity between the vectors, to decide the winning neurons and perform the updates.”).
As to claim 13, Jeong as modified discloses the information processing apparatus according to claim 11, wherein the storage compares each of the plurality of pieces of first data with the second data in parallel
(Jeong p. 4451: “Experimental Implementation of the K-means Algorithm. The K-means algorithm was experimentally implemented using the memristor array and a custom-built test board (Figure 2a and S4). The test board allows arbitrary pulse signals to be sent to and electronic current collected from either individual devices or multiple devices in multiple rows and columns simultaneously in parallel.”).
As to claim 17, Jeong as modified discloses the information processing apparatus according to claim 15, wherein the storage is a cross point-type memory
(Jeong p. 4448: “Here we address these challenges and experimentally implement the K-means algorithm in memristor crossbar array-based hardware as a test case. In the implementation,
locations of the K centroids are directly mapped as weights in the memristor array in column-wise fashion, i.e., Wmn at crosspoint (m, n) in the memristor array corresponds to the mth
coordinate value of the nth centroid.”).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Singh et al., US Pub. No. 2021/0397610, in view of Bordawekar et al., US Pub. No. 2024/0220488 A1, in view of Lu et al., Article: “An analog online clustering circuit in 130nm CMOS”; 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) (2013, Page(s): 177-180) Univ. of Tennessee, Knoxville, TN, USA, in view of Perronin et al., US Pub. No. 2009/0271433 A1.
As to claim 18, Singh/Bordawekar/Lu do not disclose:
wherein the processing circuitry is further configured to repeat a process of distributing the plurality of pieces of first data into two clusters by soft clustering using non-negative matrix factorization (NMF);
However, Perronnin discloses:
as modified discloses the information processing apparatus according to claim 1, wherein the processing circuitry is further configured to repeat a process of distributing the plurality of pieces of first data into two clusters by soft clustering using non-negative matrix factorization (NMF)
(Perronnin [0007] In some illustrative embodiments disclosed as illustrative examples herein, a clustering method comprises: constructing a nonnegative sparse similarity matrix for a set of
objects; performing nonnegative factorization of the nonnegative sparse similarity matrix; and allocating objects of the set of objects to clusters based on factor matrices generated by
the nonnegative factorization of the nonnegative sparse similarity matrix.; see also [0017] The objects clustering system 20 operates on the similarity measures to cluster the objects by (i) building a sparse nonnegative feature matrix encoding an exact or approximate similarity between pairs of documents; and (ii) performing nonnegative factorization of the feature matrix to obtain soft (or optionally hard) cluster assignments. These operations are described with illustrative reference to the objects clustering system 20 of the FIGURE.;
see also [0027] A nonnegative factorization engine 40 factorizes the nonnegative sparse similarity matrix 36 to generate factor matrices based upon which a clusters identifier 42 allocates objects of the set of objects 22, for example in the form of cluster allocation probabilities 44 in the case of soft clustering, or cluster assignments in the case of hard clustering).
It would have been obvious to one having ordinary skill in the art at the time the time of the effective filing date to apply soft clustering via nonnegative factorization of the feature matrix as taught by Perronnin to the system of Singh/Bordewekar/Lu since it was known in the art that clustering systems provide soft clustering via nonnegative matrix factorization as nonnegative matrix factorization techniques are known to be efficient clustering techniques for sparse matrices in the context of textual documents characterized by document/word co-occurrence matrices where in that application, elements of the sparse matrix represent occurrences of words in documents. In the object clustering techniques disclosed herein, elements of the nonnegative sparse similarity matrix represent similar objects, for example occurrence of an
object in theK-NNlistof another object in the case of a K-NN directed graph, that is, a link in the K-NN directed graph where it is recognized herein that applying nonnegative matrix factorization
to the nonnegative sparse similarity matrix enables efficient clustering of the objects into clusters. (Perronnin [0028]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
CONTACT INFORMATION
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVAN S ASPINWALL whose telephone number is (571)270-7723. The examiner can normally be reached Monday-Friday 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Neveen Abel-Jalil can be reached at 571-270-0474. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Evan Aspinwall/Primary Examiner, Art Unit 2152