Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-15 are pending.
Drawings
3. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: “first data” and “second data”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
4. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “first data” and “second data”. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
5. Claim 2 is objected to because of the following informalities: Line 2 states “the second data are present” and should be replaced with “the second data is present”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "a second buffer, configured to receive and store second data when the first buffer is full" in lines 5-6. It’s unclear where the second data is coming from. Is the second data the same as the first data coming from outside of the electronic device or is it coming from within the electronic device?
Claim 11 recites the limitation "a second buffer receiving and storing second data when the first buffer is full" in line 8. It’s unclear where the second data is coming from. Is the second data the same as the first data coming from outside of the electronic device or is it coming from within the electronic device?
Claims 2-10 and 12-15 are further rejected based on their dependency of claims 1 and 11.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 1, 2, 4, 7, 8, 10, 11, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Bain (US Patent No. 7,764,710 B1 hereinafter “Bain”) in view of Greenberger (US Pub. No. 2006/0041702 A1 hereinafter “Greenberger”), and further in view of Schmidt et al. (US Pub. No. 2002/0034178 A1 hereinafter “Schmidt”).
Referring to claim 1, Bain discloses an electronic device, comprising:
a first buffer (Bain – Fig. 4, Buffer 0), configured to receive and store first data when the first buffer is not full (Bain – Fig. 3 shows Steps 301, 303, 305);
a second buffer (Bain – Fig. 4, Buffer 1), configured to receive and store second data when the first buffer is full (Bain – Fig. 3 shows Steps 301, 303, 309).
Bain fails to explicitly disclose the first buffer to perform a First-In-First-Out (FIFO) operation on the first data; and the second buffer to perform the FIFO operation on the second data; a first multiplexer, electrically connected between the first buffer and the second buffer, configured to receive the first data from outside of the electronic device or to receive the second data from the second buffer, wherein a depth of the first buffer is less than that of the second buffer.
Greenberger discloses the first buffer to perform a First-In-First-Out (FIFO) operation on the first data (Greenberger – Fig. 4, par. [0044]) discloses the first memory buffer 112 temporarily stores data being transferred to and from the first device (e.g., the hard disk 32) via the first device interface logic 104 and the interface 85. The first memory buffer 112 includes at least one buffer device (e.g., a first FIFO memory 122) that temporarily stores data read from the first device 32, and at least one buffer device (e.g., a second FIFO memory 124) that temporarily stores data to be written to the first device 32.); the second buffer to perform the FIFO operation on the second data (Greenberger – Fig. 4, par. [0045]) discloses the second memory buffer 116 temporarily stores data being transferred to and from the second device (e.g., the CD-RW 34), via the second device interface logic 106 and the interface 87. The second memory buffer 116 includes at least one buffer device (e.g., a third FIFO memory 126) that temporarily stores data read from the second device 34, and at least one buffer device (e.g., a fourth FIFO memory 128) that temporarily stores data to be written to the second device 34.); and a first multiplexer, electrically connected between the first buffer and the second buffer, configured to receive the first data from outside of the electronic device or to receive the second data from the second buffer (Greenberger – Fig. 4, par. [0046]) discloses the first multiplexing circuitry 114 includes circuitry that allows the memory device that stores data to be written to the first device (i.e., the second FIFO memory 124) to receive data from either the bus 14, via the host interface logic 102, or the second device 34, via the third FIFO memory 126.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Greenberger’s teachings with Bain’s teachings for the benefit of the time required for data transfer is reduced and the data transfer components dissipate less power (Greenberger – Par. [0008]).
Bain and Greenberger fail to explicitly disclose wherein a depth of the first buffer is less than that of the second buffer.
Schmidt discloses wherein a depth of the first buffer is less than that of the second buffer (Schmidt – Claim 52 discloses the second buffer is larger than the first buffer.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Schmidt’s teachings with Bain and Greenberger’s teachings for the benefit of providing additional address capacity such that a new address is created within the switch itself for routing data within the switch (Schmidt – Par. [0012]).
Referring to claim 2, Bain, Greenberger and Schmidt disclose the electronic device as claimed in claim 1, wherein when the first buffer is full, the first data is read out from the first buffer (Bain – Fig. 3 shows Steps 315, 317), and the second data are present in the second buffer, the first buffer receives the second data from the second buffer (Bain – Fig. 3 shows Steps 319) through the first multiplexer (Greenberger – Fig. 4, first multiplexing circuitry 114).
Referring to claim 4, Bain, Greenberger and Schmidt disclose the electronic device as claimed in claim 1, wherein after the first data are read from the first buffer (Bain – Fig. 3 shows Steps 315, 317), the first multiplexer receives the second data from the second buffer (Greenberger – Fig. 4, par. [0046]) discloses the first multiplexing circuitry 114 includes circuitry that allows the memory device that stores data to be written to the first device (i.e., the second FIFO memory 124) to receive data from either the bus 14, via the host interface logic 102, or the second device 34, via the third FIFO memory 126.) and outputs the second data to the first buffer (Bain – Fig. 3 shows Steps 319).
Referring to claim 7, Bain, Greenberger and Schmidt disclose the electronic device as claimed in claim 1, wherein when the first buffer is not full (Bain – Fig. 3 shows Steps 303, 305), the first multiplexer receives the first data from outside of the electronic device (Greenberger – Fig. 4, par. [0046]) discloses the first multiplexing circuitry 114 includes circuitry that allows the memory device that stores data to be written to the first device (i.e., the second FIFO memory 124) to receive data from either the bus 14, via the host interface logic 102, or the second device 34, via the third FIFO memory 126.), and outputs the first data to the first buffer (Bain – Fig. 3 shows Steps 303, 305).
Referring to claim 8, Bain, Greenberger and Schmidt disclose the electronic device as claimed in claim 1, wherein the second buffer (Greenberger – Fig. 4, par. [0045]) discloses the second memory buffer 116.) comprises: a memory unit, configured to store the second data (Greenberger – Fig. 4, memory 128.) when the first buffer is full (Bain – Fig. 3 shows Steps 301, 303, 309); and a data selecting unit, configured to select the second data based on the FIFO operation, and output the second data to the first multiplexer when the first buffer is full (Bain – Fig. 3 shows Steps 301, 303, 309).
Referring to claim 10, Bain, Greenberger and Schmidt disclose the electronic device as claimed in claim 1, wherein when the depth of the first buffer is larger than 1, the first buffer comprises a data selecting unit; the data selecting unit selects the first data based on the FIFO operation, and outputs the first data when the first data is read out (Greenberger – Fig. 4, par. [0044]) discloses the first memory buffer 112 temporarily stores data being transferred to and from the first device (e.g., the hard disk 32) via the first device interface logic 104 and the interface 85. The first memory buffer 112 includes at least one buffer device (e.g., a first FIFO memory 122) that temporarily stores data read from the first device 32, and at least one buffer device (e.g., a second FIFO memory 124) that temporarily stores data to be written to the first device 32.)
Referring to claim 11, note the rejection of claim 1 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 14, note the rejection of claim 7 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 15, note the rejection of claim 1 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
11. Claims 5, 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Bain in view of Greenberger and Schmidt, and further in view of Watanabe et al. (US Patent No. 6,101,151 hereinafter “Watanabe”).
Referring to claim 5, Bain, Greenberger and Schmidt disclose the electronic device as claimed in claim 1, however, fail to explicitly disclose wherein when the first buffer is not full, the second buffer receives a control signal to stop a clock signal in the second buffer.
Watanabe discloses the second buffer receives a control signal to stop a clock signal in the second buffer (Watanabe – Claim 1 states a supply stop circuit for stopping supplying of the clock signal from said clock signal supplying circuit to at least one of said plurality of buffer circuits in response to said control signal.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Watanabe’s teachings with Bain, Greenberger and Schmidt’s teachings for the benefit of providing a synchronous semiconductor memory device allowing reduction of power consumption, by stopping clock driver circuits in the binary clock tree block (Watanabe – Col. 2, lines 62-65).
Referring to claim 9, Bain, Greenberger and Schmidt disclose the electronic device as claimed in claim 1, however, fail to explicitly disclose wherein the first buffer receives a control signal to stop a clock signal in the first buffer.
Watanabe discloses the first buffer receives a control signal to stop a clock signal in the first buffer (Watanabe – Claim 1 states a supply stop circuit for stopping supplying of the clock signal from said clock signal supplying circuit to at least one of said plurality of buffer circuits in response to said control signal.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Watanabe’s teachings with Bain, Greenberger and Schmidt’s teachings for the benefit of providing a synchronous semiconductor memory device allowing reduction of power consumption, by stopping clock driver circuits in the binary clock tree block (Watanabe – Col. 2, lines 62-65).
Referring to claim 13, note the rejection of claim 5 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
12. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Bain in view of Greenberger and Schmidt, and further in view of Zahn et al. (US Pub. No. 2015/0269304 hereinafter “Zahn”).
Referring to claim 6, Bain, Greenberger and Schmidt disclose the electronic device as claimed in claim 1, however, fail to explicitly disclose electronic device as claimed in claim 1, wherein the first buffer comprises one or more Ultra-Low-Voltage-Threshold (ULVT) cell.
Zahn discloses one or more Ultra-Low-Voltage-Threshold (ULVT) cell (Zahn – Par. [0041] discloses the use of the ultra-low voltage threshold cell.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Zahn’s teachings with Bain, Greenberger and Schmidt’s teachings for the benefit of a system and method for employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce total power in an electronic circuit, particularly an IC (Zahn – Par. [0001]).
Related Prior Art
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. Beier et al. (US Pub. No. 2022/0405289 A1 hereinafter “Beier”) discloses a computer-implemented method for facilitating large data transfers from a first data management system to a second data management system is disclosed. The method comprises receiving data from the first data management system by a first buffer component, rerouting, upon the first buffer component reaching a predefined fill-level, dynamically the received data to a second buffer component, wherein the second buffer component is adapted to process the rerouted received data, forwarding, by the second buffer component, the rerouted data once the first buffer component is again ready for receiving the rerouted data from the second buffer component, and sending, by a sending component, the data buffered in the first component to the second data management system.
b. Wu et al. (US Patent No. 7,539,791 B2 hereinafter “Wu”) discloses a method for storing data in a first buffer and a second buffer is disclosed. The method includes: sequentially storing an incoming data into the first buffer and the second buffer according to a first threshold; transferring data stored in the second buffer to the first buffer when an amount of data stored in the second buffer reaches a second threshold; and driving the first buffer to output data stored therein when an amount of data stored in the first buffer exceeds the first threshold after transferred data is received from the second buffer.
c. Wu (US Pub. No. 2007/0245043 A1 hereinafter “Wu”) discloses FIFO systems and operating method thereof are provided to transfer data between a first device and a second device. In the FIFO system, a memory controller serves as an interface to access a memory device for storage of the data, and a CPU processes instructions to control the data transfer. Two data FIFOs serve as data buffers for data transactions to and from the first and second devices, and two status FIFOs serve as an instruction buffers for status transactions between the first, second devices and the CPU. A data controller connects the memory controller and the two data FIFOs for direct data delivery therebetween.
d. Kim et al. (US Pub. No. 2002/0199042 A1 hereinafter “Kim”) discloses a first-in, first-out (FIFO) memory system (10) includes first and second FIFOs (A and B). First and second multiplexers (12, 14) each have two input terminals for receiving data. An output terminal of the first multiplexer (12) is coupled to the first FIFO (A) and an output terminal of the second multiplexer (14) is coupled to the second FIFO (B). In response to the data being one data type, write control logic (90, 95, 100) is used to cause the data to be alternately written to the first and second FIFOs (A, B). In response to the data being a second data type, write control logic (90, 95, 100) is used to cause the data to be simultaneously written to the first and second FIFOs (A, B).
e. Treggiden (US Pub. No. 2002/0046307 A1 hereinafter “Das”) discloses a direct memory access (DMA) first-in-first-out (FIFO) buffer includes two FIFO devices connected in parallel. An output multiplexer is controlled by a controller to pass to its output data provided by a selected one of the FIFO devices. Data is clocked into one FIFO device until it is full, after which data may be written from it. When data is written from a FIFO device, the FIFO device is emptied before data is again read into it. Using this arrangement, data can be read into one FIFO device whilst data is written from the other FIFO device.
Allowable Subject Matter
14. Claims 3 and 12 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest a second multiplexer, electrically connected to the second buffer, configured to… output a binary zero to the second buffer when the first buffer is not full, in combination with other recited limitations in dependent claims 3 and 12.
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Ill(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAYTON LEWIS-TAYLOR whose telephone number is (571) 2707754. The examiner can normally be reached on Monday through Thursday, 8AM TO 4PM, EASTERN TIME.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye, can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Dayton Lewis-Taylor/
Examiner, Art Unit 2181
Prosecution Insights