DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s arguments filed on 07/07/2026.
Response to Arguments
Applicant's arguments filed on 07/07/2026 have been fully considered but they are not persuasive. Applicant mainly argued regarding independent claims 1 & 8, for same limitations, which will be discussed below. Other claims were noted due to dependence on claims 1 & 8.
Applicant mainly argued regarding independent claims 1 & 8, as follows,
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However, respectfully the Examiner disagrees. Applicants seem to be arguing over an anticipated in-sequenced conditional functional language that was never claimed.
Note that Applicant fails to clearly claim i) how current flowing the auxiliary switch is sensed or considered, ii) what is zero reference (is it ZCD or actual reference or threshold, if so is it voltage reference or current reference) and/or iii) how is it determined that the current flowing through the auxiliary switch reaching zero reference (i.e., is it ZCD, compared or sensed).
Under broadest reasonable interpretations (BRI), Examiner is only required to find an art which teaches using a control circuit to control a main control switch and an auxiliary switch
in response to a feedback voltage (which can be direct sensed or scaled down feedback voltage, not even any type of error signal, only that the feedback voltage is indicative of the output voltage); wherein
in response to a shutdown signal switching on the main switch and off the auxiliary switch, until a current flowing though the main power switch reaches a main current limit; and then (not necessarily in response to anything having to)
switch on the auxiliary switch and switch off the main power switch until a current flowing through the auxiliary switch (i.e., when the auxiliary switch is on, such as using duty cycle or fixed PWM or PFM, it is anticipated that some type of current will be passing though, which is known and established. Applicant never claims is a direct current is sensed from the auxiliary switch. To one of ordinary skill in the art, using some other type of elements voltage of specific elements can be representation of a sensed current (in this case of the auxiliary switch) using ohm’s law I=V/R) reaches a zero reference (i.e., which could be a voltage or current reference of some kind of zero value, under BRI) to have the integrated circuit enter protection mode.
Applicant already agrees that part A-B are taught by Hwang, except for part C. Noting down the pointed broadest reasonable interpretation in above part C, see following amended Fig.(s) of Hwang,
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Above annotated Fig. 1, 9-10 are from Hwang (US Pub 2017/0179832), provided for quick comparison and understanding, however do note that all of Hwang’s Fig. 1-14 and corresponding Paras are applicable for following teaching of each claim(s)
According to Hwang’s paras ‘43, 90’, ZCD is representation of voltage level Vcc and voltage signal
V
L
; wherein,
V
L
is formed at a node between SW1 and SW2 and at the second terminal of the primary winding of transformer T. The voltage levels of Vcsn and
V
L
, both are based on switching operation of SW1-2; wherein from Hwang’s Fig. 3-4 it is evident that using the switching operations of SW1-2, the voltage level
V
L
can be configured to be varied including zero. From, Hwang’s paras 31-33, it is also evident Hwang prefers to have SW1 & SW2 be controlled in a complementary manner, but Hwang’s controller ‘152 & 154’ is also configured to be selectively switch one of the switches being turned on and then off while the other switch is off, vice versa to regulate the output voltage. It is also evident that Hwang’s 154 that is used to drive SW2 operates based on 152’s output (wherein 152 considers ZCD, I sense, Veao, OSC, Vcc), along with Vcsn (representation of SW2’s current, when SW2 is on, Hwang’s Fig. 7, wherein current I and/or voltage V can be easily calculated using ohm’s law [I=V/R or V=IxR]) and
V
L
; wherein SW2 is triggered to be on, while SW1 off, based on comparator CMP2’s provided output Ilimit by comparing between Vcsn (i.e., when SW1=off and SW2=on, the current in the primary winding of T1 can pass through the switch SW2 to the snubber capacitor Csn, and thus generating Vcsn, wherein Vcsn is voltage representation of SW2’s carried current when conducting, which is anticipated based on Hwang’s Fig. 7 and ohm’s law [I=V/R or V=IxR], current I and/or voltage V can be easily calculated) and
V
L
(similarly, voltage level of
V
L
is formed based on switching on-off of SW1 and SW2, wherein
V
L
is voltage representation of SW1-2’s carried current when conducting, which is anticipated based on ohm’s law I=V/R or V=IxR); and then 154’s 160 considers Ilimit & 152’s output READYHIGHON to determine when to switch SW2, while 152 controls the switching operation of SW1.
Therefore, under broadest reasonable interpretations (BRI) and based on above rationale Hwang clearly teaches “the control circuit (154, 152) is configured to control the auxiliary switch to be turned on (SW2=on) and the main power switch to be turned off (SW1=off), until a current flowing through the auxiliary switch (current flowing though SW2 when conducting, used by CMP2 in 154. For example, when SW1=off and SW2=on, the current in the primary winding of T1 can pass through the switch SW2 to the snubber capacitor Csn, and thus generating Vcsn, wherein Vcsn is voltage representation of SW2’s carried current when conducting, which is anticipated based on Hwang’s Fig. 7 and ohm’s law [I=V/R or V=IxR], current I and/or voltage V can be easily calculated) reaches a zero reference (i.e., ZCD valued or zero valued
V
L
also used by CMP2 in 154; Para 36, 43-45 and 90-91), to control the integrated circuit (IC) to enter a protection mode (Fig. 5-14; based on shut down detecting condition, various protection modes of operation being performed i) current control protection mode 172 amplifying ISENSE during very light load to up until full or heavy mode vs. ii) frequency control protection mode 174 reducing ISENSE during full or heavy mode vs. iii) burst-mode of operation, as can be seen in Fig. 12, using detail-controlled elements, which can be seen in Fig. 9-14)”.
Lastly, Examiner recommends clearly claim i) how current flowing the auxiliary switch is sensed or considered, ii) what is zero reference and/or iii) how is it determined that the current flowing through the auxiliary switch reaching zero reference (i.e., is it compared or sensed). For example, from Applicant’s Fig. 1-7, it appears that sensed auxiliary switch current (i.e., Appliant’s I 102 using a sensor) is compared with a reference current (Applicant’s Iz) in order to determine zero current detection which is also used by some type of logic gate prior to switching of main power switch 101 vs. auxiliary power switch 102. Examiner recommends somehow incorporate these into claims 1 & 8 to overcome rejection.
For further evidence, Examiner recommends to Applicant to read through the entire Hwang art, as everything in Hwang is required to make his invention work (to understand Hwang as a whole), but for quick reference see following excerpt from Hwang,
[0025] … in FIG. 2, the input voltage source Vin is coupled to a first terminal of a capacitor Csn and to a first terminal of a primary winding of a transformer T1. The capacitor Csn functions as a snubber capacitor. A voltage Vcsn having polarity formed across Csn. A second terminal of the primary winding of T1 is coupled to a first terminal of a “low side” switch SW1 and to a first terminal of a “high side” switch SW2. A voltage
V
L
is formed at a node between SW1 and SW2 and at the second terminal of the primary winding of T1. A second terminal of SW1 is coupled to a first ground node. A second terminal of the switch SW2 is coupled to a second terminal of the capacitor Csn. The switch SW1 is controlled by a signal LOWOUT while the switch SW2 is controlled by a signal HIGHOUT.
[0030] When SW1 is opened “off” and the switch SW2 is in the closed “on” position, the current in the primary winding of T1 can pass through the switch SW2 to the snubber capacitor Csn. Alternatively, when (both) SW1 and SW2 in the open position, the current in the primary winding of T1 can pass through the body diode of SW2.
[0031] SW2 is preferably controlled to be OFF when the SW1 is ON. Then, when SW1 is OFF and the energy from the transformer T1 has been largely discharged to the output capacitor C1, the voltage
V
L
will be equal to Vcsn. Under these conditions, SW2 is briefly ON…. operated under zero volt switching (ZVS) conditions… (resulting) SW2 discharges the level of
V
L
to that of Vin. Then, once
V
L
is substantially equal to Vin, SW2 is OFF. The voltage
V
L
continues to fall after SW2 is OFF, such that when SW1 is ON, the voltage across it is zero or nearly zero. Thus, SW1 is also preferably operated under ZVS conditions. The cycle then repeats.
[0032] To summarize, during a switching cycle, SW1 is off; then SW2 is turned on and then off immediately before SW is turned on. The cycle is then repeated (i.e. SW1—off, SW2—on, SW2—off, SW1—on, SW1—off, . . .). SW2 is thus turned on then off once before each SW1 turn on. Also, SW2 is turned on then off once for each cycle of SW1 (while SW1 is off). In other words, each switch is turned on and then off while the other switch is off.
[0033] …, both SW1 and SW2 are operated under ZVS, regardless of load. Thus, they are both operated under ZVS from no load to full load.
[0043] T1 include a second secondary winding. As shown in FIG. 5, …. A voltage Vcc is formed across the capacitor C4 … used for powering control circuitry of the flyback converter 150. A resistive divider includes resistors R5 and R6 and generates a voltage signal ZCD that is representative of the level of Vcc. The signal ZCD is also representative of the level of
V
L
.
[0044] …in FIG. 5, a current sensing resistor Rsense is coupled between the second terminal of SW1 and the first ground node. A current signal Isense is formed across the resistor Rsense.
[0045] The low driver controller 152 receives as inputs the signals ZCD, Isense, Veao as well as an oscillator signal OSC and uses these signals to generate the signal LOWOUT for controlling SW1. Briefly, the signal Veao represents the load power and is used to regulate the output voltage in a feedback loop based on either peak current control or switching frequency control. The signal Isense represents the current in T1 and is used to the control peak current in T1’s primary winding during switching (i.e., S1 vs. S2 ON/OFF switching operation). The oscillator signal OSC is used for controlling the timing of switching. The signal ZCD is representative of the level of
V
L
and is used to turn on SW1.
[0046] 152 generates a differential signal READYHIGHON … informs the high driver controller 154 that it can (i.e. has permission to) turn on SW2, …154 determines the timing of turning on SW2. The signal READYHIGHON is preferably a differential signal because 152 and 154 have different ground reference nodes. … 152 is referenced to the first ground node, whereas 154 preferably uses the voltage
V
L
as its reference.
[0047] in FIG. 5, …, when
V
L
is greater than Vin and CS is substantially equal to
V
L
, 154 turns on SW2, until
V
L
is substantially equal to Vin and then the switch SW2 is turned off.
[0048] in FIG. 5, the voltage Vcc can be used as a power supply for powering elements of 152. A voltage VBOOT can be used as a power supply for powering elements of 154. The voltage VBOOT can be obtained by drawing current from Vcc, for example, via a diode which then charges a capacitor CBOOT.
[0049] A switching cycle is performed as follows. SW1 is on. Then, once the peak current in the primary winding of T1 is reached, as indicated by Isense, SW1 is off. The peak current depends on the level of Veao: (1) when Veao is less than a threshold (e.g. 2.5 volts), then the flyback converter is in frequency control mode and the peak current is essentially a fixed value (though the peak current is preferably gradually reduced as VEAO falls in order to increase efficiency and inhibit audible noise in burst mode); (2) when Veao is greater than the threshold (e.g. 2.5 volts), then the flyback converter is in current control mode and the peak current depends on Veao (and the switching frequency is clamped). Once SW1 turns off, the voltage
V
L
flies up, eventually reaching a level above Vin. 152 then activates sending the READYHIGHON signal to 154 at a time that depends upon the switching frequency. After receiving the READYHIGHON signal, 154 determines that
V
L
is greater than Vin and, in response to this determination, 154 turns on SW2… (wherein) SW2 remains on until the level of
V
L
falls to the level of Vin, as which time, 154 turns off SW2. When the level of
V
L
falls to zero, the low side switch SW1 can be turned on again.
[0074] FIG. 9 illustrates 154 … A signal RVIN, which approximates the signal Vin, is compared by a comparator CMP1 to the signal
V
L
. An output of CMP1 is inverted by an inverter 158 to form a logic signal
V
L
>Vin. The signal
V
L
>Vin is coupled to an input of a NAND gate 160, to an inverted set input S-bar of a flip-flop FF.sub.1, to an input of a NAND gate 161 and to an input of a NAND gate 162.
[0075] The signals at the input of the comparator CMP1 are shown as approximately equal Vin and
V
L
. These input signal levels may be adjusted (e.g. by a current source adding or removing current from each comparator input node) in order to compensate for signal path delays during high-frequency operation and to limit their amplitudes (e.g., by diode clamping).
[0076] The signal Vcsn is coupled to a first terminal of a resistor R10 and to a first terminal of a MOSFET M4. The signal Vcsn may also be amplitude limited by diode clamping. A second terminal of the resistor R10 is coupled to a first input terminal of a comparator CMP2. A second terminal of the MOSFET M4 is coupled to the signal
V
L
and to a reference node of the comparator CMP2. The signal
V
L
is coupled to a second input terminal of the comparator CMP2. The comparator CMP2 compares the signal Vcsn to the signal
V
L
to form a current-limit signal Ilimit. The signal Ilimit is provided via an inverter 164 to an input of the NAND gate 160 and to an inverted set input S-bar of a flip-flop FF2. The signal Ilimit indicates that the level of Vcsn is equal to
V
L
and that SW2 can be opened.
[0082] SW2 stays on until
V
L
is substantially equal to Vin and then SW2 is turned off. This is determined when Vcsn is substantially equal to
V
L
, as indicated by the signal Ilimit. The generated signal HIGHOUT is used to control SW2.
[0090] The timer block generates a logic signal HON and a logic signal ONSET which are coupled to the switching logic 178. The signal HON is used to generate the signal READYHIGHON for 154. For peak current control, the signal HON is generated at fixed intervals. The signal ONSET is used to turn on SW1. For example, a timer of 3.33 microseconds can be reset for each switching cycle; 500 nanoseconds prior to expiration of the timer, the signal HON is activated. And, upon expiration of the timer, and once ZCD is greater than zero, then the signal ONSET can be activated… (resulting) SW1 can be closed (ON) upon a valley in signal ZCD (since ZCD represents
V
L
) so as to operate SW1 under zero volt switching (ZVS) conditions. The 500 nanosecond difference ensures that HON is activated prior to ONSET.
[0091] The signal ZCD is referenced to the same ground level as 152. The signal ZCD is also representative of the level of
V
L
. Thus, signal ZCD is used by 152 as a proxy for
V
L
in order to operate the switch SW1 under ZVS conditions.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1, 6-7, 8, 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang (US Pub 2017/0179832).
Regarding independent claim 1, Hwang teaches (Fig. 1-14; Para 41-107. Also, see, above annotated Figs and relevant citations) an active clamp flyback converter (Fig. 5; 150), comprising:
a transformer (Fig. 5; T1), including a primary winding (Fig. 5; W1) configured to receive an input voltage (Fig. 5; DC Vin), and a secondary winding (Fig. 5; W2_1-2) configured to generate an output voltage (Vo);
a main power switch (Fig. 5; low-side switch SW1), coupled between the primary winding (W1) and a primary reference ground (Fig. 5; GND), wherein an electrical connection (Fig. 5; i.e., at a node where VL being generated which coupled SW1-2 and W1) of the main power switch (SW1) and the primary winding (W1) forms a switch node;
an auxiliary switch (Fig. 5; high-side switch SW2) and an auxiliary capacitor (Fig. 5; Csn), coupled in series between the switch node (Fig. 5; i.e., at a node where VL being generated which coupled SW1-2 and W1; wherein when SW2=ON, established a series connection between the taught switch node and Vin) and the input voltage (DC Vin), wherein the main power switch (SW1) and the auxiliary switch (SW2) are integrated into a single integrated circuit (various alternative arrangements of Fig. 5’s elements in an integrated circuit (IC); Para 51-73);
a control circuit (Fig. 5-14; 154, 152), configured to generate a main control signal (Fig. 5-14; LWOUT) and an auxiliary control signal (Fig. 5-14; HIGHOUT) in response to a feedback voltage (Fig. 5; VEAO) indicative of the output voltage (Vo), to respectively control the main power switch (SW1) and the auxiliary switch (SW2); and
a shutdown detection circuit (Fig. 5-14; any of the comparing means outputs, once detecting shutdown condition), configured to detect a shutdown condition (i.e., any one of CMP3’s inputs, VEAO, ISENSE, UVLO, ZCD, over-temperatures (OT) or ILIMIT (for overcurrent operation) being detected shut-down conditions) of the active clamp flyback converter (150), to generate a shutdown signal (i.e., any of the comparing means outputs, once detecting shutdown condition, for example CMP3’s output, which is arranged inside 152 configured to perform switching between two proception modes, one of them ii) frequency control protection mode 174 reducing ISENSE during full or heavy mode, as can be seen in Fig. 12, using detail-controlled elements, which can be seen in Fig. 9-14);
wherein
the control circuit (Fig. 5-14; 154, 152) is configured to control the main power switch to be turned on (SW1=on) and the auxiliary switch to be turned off (SW2=off) in response to the shutdown signal (i.e., CMP3’s output), until a current (ISENSE) flowing through the main power switch (SW1) reaches a main current limit (Fig. 5-14; Ilimit); and then
the control circuit (154, 152) is configured to control the auxiliary switch to be turned on (SW2=on) and the main power switch to be turned off (SW1=off), until a current flowing through the auxiliary switch (current flowing though SW2 when conducting, used by CMP2 in 154. For example, when SW1=off and SW2=on, the current in the primary winding of T1 can pass through the switch SW2 to the snubber capacitor Csn, and thus generating Vcsn, wherein Vcsn is voltage representation of SW2’s carried current when conducting, which is anticipated based on Hwang’s Fig. 7 and ohm’s law [I=V/R or V=IxR], current I and/or voltage V can be easily calculated) reaches a zero reference (i.e., ZCD valued or zero valued
V
L
also used by CMP2 in 154; Para 36, 43-45 and 90-91), to control the integrated circuit (IC) to enter a protection mode (Fig. 5-14; based on shut down detecting condition, various protection modes of operation being performed i) current control protection mode 172 amplifying ISENSE during very light load to up until full or heavy mode vs. ii) frequency control protection mode 174 reducing ISENSE during full or heavy mode vs. iii) burst-mode of operation, as can be seen in Fig. 12, using detail-controlled elements, which can be seen in Fig. 9-14).
Regarding independent claim 8, Hwang teaches (Fig. 1-14; Para 41-107. Also, see, above annotated Figs and relevant citations) an integrated circuit (Fig. 6) used for an active clamp flyback converter (150), comprising:
an auxiliary switch (Fig. 5; high-side switch SW2);
a main power switch (Fig. 5; low-side switch SW1), coupled between the auxiliary switch (Fig. 5; high-side switch SW2) and a reference ground (gnd);
a control circuit (Fig. 5-14; 154, 152), configured to generate a main control signal (Fig. 5-14; LWOUT) and an auxiliary control signal (Fig. 5-14; HIGHOUT) in response to a feedback voltage (Fig. 5; VEAO) indicative of an output voltage (Vo) of the active clamp flyback converter (150), to respectively control the main power switch (SW1) and the auxiliary switch (SW2); and
a shutdown detection circuit (Fig. 5-14; any of the comparing means outputs, once detecting shutdown condition), configured to detect a shutdown condition (i.e., any one of CMP3’s inputs, VEAO, ISENSE, UVLO, ZCD, over-temperatures (OT) or ILIMIT (for overcurrent operation) being detected shut-down conditions) of the active clamp flyback converter (150), to generate a shutdown signal (i.e., any of the comparing means outputs, once detecting shutdown condition, for example CMP3’s output, which is arranged inside 152 configured to perform switching between two proception modes, one of them ii) frequency control protection mode 174 reducing ISENSE during full or heavy mode, as can be seen in Fig. 12, using detail-controlled elements, which can be seen in Fig. 9-14);
wherein
the control circuit (Fig. 5-14; 154, 152) is configured to control the main power switch to be turned on (SW1=on) and the auxiliary switch to be turned off (SW2=off) in response to the shutdown signal (i.e., any of the comparing means outputs, once detecting shutdown condition, for example CMP3’s output, which is arranged inside 152 configured to perform switching between two proception modes, one of them ii) frequency control protection mode 174 reducing ISENSE during full or heavy mode, as can be seen in Fig. 12, using detail-controlled elements, which can be seen in Fig. 9-14), until a current flowing through the main power switch (ISENSE) reaches a main current limit (ILIMIT); and then
the control circuit (154, 152) is configured to control the auxiliary switch to be turned on (SW2=on) and the main power switch to be turned off (SW1=off), until a current flowing through the auxiliary switch (current flowing though SW2 when conducting, used by CMP2 in 154. For example, when SW1=off and SW2=on, the current in the primary winding of T1 can pass through the switch SW2 to the snubber capacitor Csn, and thus generating Vcsn, wherein Vcsn is voltage representation of SW2’s carried current when conducting, which is anticipated based on Hwang’s Fig. 7 and ohm’s law [I=V/R or V=IxR], current I and/or voltage V can be easily calculated) reaches a zero reference (i.e., ZCD valued or zero valued
V
L
also used by CMP2 in 154; Para 36, 43-45 and 90-91), to control the integrated circuit (IC) to enter a protection mode (Fig. 5-14; based on shut down detecting condition, various protection modes of operation being performed i) current control protection mode 172 amplifying ISENSE during very light load to up until full or heavy mode vs. ii) frequency control protection mode 174 reducing ISENSE during full or heavy mode vs. iii) burst-mode of operation, as can be seen in Fig. 12, using detail-controlled elements, which can be seen in Fig. 9-14).
Regarding claims 6, 13, Hwang teaches the shutdown condition (i.e., any one of CMP3’s inputs, VEAO, ISENSE, UVLO, ZCD or ILIMIT) of the active clamp flyback converter (150) comprises at least one of (i.e., meaning only one of the following conditions is required, which is emphasized as italicized portion):
the current flowing (ISENSE) through the main power switch (SW1) reaches the main current limit (ILIMIT);
the current flowing through the auxiliary switch (current flowing through SW2, when SW2 is on) reaches an auxiliary current limit (ILIMIT);
the output voltage (Vo) reaches a voltage threshold (desired Vo) (Para 42);
a temperature of the integrated circuit reaches a temperature threshold (Para 71); and
when the integrated circuit is disabled (Para 52, 71).
Regarding claims 7, 14, Hwang teaches the protection mode (Fig. 5-14; based on shut down detecting condition, various protection modes of operation being performed i) current control protection mode 172 amplifying ISENSE during very light load to up until full or heavy mode vs. ii) frequency control protection mode 174 reducing ISENSE during full or heavy mode vs. iii) burst-mode of operation, as can be seen in Fig. 12, using detail-controlled elements, which can be seen in Fig. 9-14) comprises: the active clamp flyback converter enters burst mode (burst mode; Para 49, 96, 107), or the integrated circuit is shutdown (i.e., based on shut down detecting condition, various protection modes of operation being performed i) to iii); wherein during ii) frequency control protection mode 174 reducing ISENSE during full or heavy mode, meaning shutting down being performed, even though it may not be spelled out).
Allowable Subject Matter
Claim(s) 2-5, 9-12, 18 is or are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 2, 9, Hwang fails to teach as a whole, nor would it be obvious to piece-by-piece simply combine with any other arts, as that would destroy Hwang’s intended circuit design, having the control circuit (i.e., Applicant’s Fig. 5) comprises (emphasizing on italicized portion, and then considering as a whole):
“a first comparator, configured to compare a main sense signal indicative of the current flowing through the main power switch with the main current limit, to generate an over current signal; a second comparator, configured to compare an auxiliary sense signal indicative of the current flowing through the auxiliary switch with the zero reference, to generate a zero detect signal; a flip flop, configured to generate the main control signal and the auxiliary control signal in response to the shutdown signal and the over current signal; and a logical circuit, configured to generate a protection signal in response to the over current signal and the zero detect signal, to have the integrated circuit enter the protection mode”, as claimed in claim 2; similarly
“a first comparator, configured to compare a main sense signal indicative of the current flowing through the main power switch with the main current limit, to generate an over current signal; a second comparator, configured to compare an auxiliary sense signal indicative of the current flowing through the auxiliary switch with the zero reference, to generate a zero detect signal; a flip flop, configured to generate the main control signal and the auxiliary control signal in response to the shutdown signal and the over current signal; and a logical circuit, configured to generate a protection signal in response to the over current signal and the zero detect signal, to have the integrated circuit enter the protection mode”, as claimed in claim 9.
Claims ‘3-4’, ‘10-11’ are depending from claims 2, 9, respectively.
Regarding claims 5, 12, Hwang fails to teach as a whole, nor would it be obvious to piece-by-piece, simply combine with any other arts, as that would destroy Hwang’s intended circuit design, having the control circuit (i.e., Applicant’s Fig. 5) comprises (emphasizing on italicized portion, and then considering as a whole):
“a proportional integrated circuit, configured to amplify a difference of the feedback voltage and a reference voltage, to generate a compensation signal; a voltage comparator, configured to compare the compensation signal with a main sense signal indicative of the current flowing through the main power switch, to generate a reset signal; and a flip flop, configured to generate the main control signal and the auxiliary control signal in response to the reset signal, to respectively control the main power switch and the auxiliary switch”, as claimed in claim 5; similarly
“a proportional integrated circuit, configured to amplify a difference of the feedback voltage and a reference voltage, to generate a compensation signal; a voltage comparator, configured to compare the compensation signal with a main sense signal indicative of the current flowing through the main power switch, to generate a reset signal; and a flip flop, configured to generate the main control signal and the auxiliary control signal in response to the reset signal, to respectively control the main power switch and the auxiliary switch”, as claimed in claim 12.
Claims 15-20 are allowed.
Regarding independent claim 15, cited art(s) failed to teach, a control circuit used in an active clamp flyback converter, the active clamp flyback converter including a main power switch and an auxiliary switch integrated at a single integrated circuit, the control circuit comprising: “a first comparator, configured to compare a main sense signal indicative of a current flowing through the main power switch with a main current limit, to generate an over current signal; a second comparator, configured to compare an auxiliary sense signal indicative of a current flowing through the auxiliary switch with a zero reference, to generate a zero detect signal; and a flip flop, configured to generate a main control signal and an auxiliary control signal in response to the over current signal and a shutdown signal indicative of a shutdown condition of the integrated circuit, wherein the flip flop is configured to: control the main power switch to be turned on and the auxiliary switch to be turned off in response to the shutdown signal; and control the main power switch to be turned off and the auxiliary switch to be turned on in response to the over current signal”.
Claims 16-20 depend on claim 15.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NUSRAT QUDDUS whose telephone number is (571)270-7921. The examiner can normally be reached on M-Th 9-4 PM ET.
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
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