DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/08/2026 has been entered.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “display data receiving module”, “frame rate switching control module”, “gamma modules”, “first switching unit”, and “second switching unit” in claims 1-20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
The modules of claims 1-20 are elements interpreted under 35 U.S.C. 112(f) and the circuitry is based on the description in the specification. Specifically, Fig. 12 and [0134]-[0135] show a hardware structure of an electronic device according to an embodiment of the application including a processor encoded with software having the described operations and functions as disclosed throughout the Specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-10, 12-13 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shih et al. (US 11,483,530) in view of Lee et al. (US PGPub 2023/0083289) hereinafter referred to as Lee ‘289.
Regarding claim 1, Shih discloses a display control chip (fig. 1, color compensation system 1; and column 4, lines 39-54 teach hardware may be a chip), wherein the display control chip comprises a display data receiving module and a frame rate switching control module, wherein the display data receiving module is configured to receive a first (column 1, lines 51-61, “a color compensation method for a monitor, which comprises obtaining a target brightness, a target pulse number and a target frame rate; selecting a plurality of second gamma groups from a plurality of first gamma groups according to the target pulse number, wherein the plurality of first gamma groups respectively correspond to a plurality of frame rates; and calculating a compensation value for compensating a brightness and a color of the monitor according to the target brightness, the target frame rate, the plurality of second gamma groups and a calculation method”);
wherein the display control chip further comprises a plurality of gamma modules, and the plurality of gamma modules are configured to calculate a display parameter corresponding to the target frame rate (column 1, lines 58-61, “calculating a compensation value for compensating a brightness and a color of the monitor according to the target brightness, the target frame rate, the plurality of second gamma groups and a calculation method”), wherein
the display parameter comprises at least one of display brightness or color (column 1, lines 58-61, “calculating a compensation value for compensating a brightness and a color of the monitor”);
wherein the plurality of gamma modules correspond one-to-one with a plurality of frame rate grades, and the plurality of frame rate grades are determined based on the number of gamma modules in the plurality of gamma modules and a frame rate switching range of the frame rate switching control module; wherein the target frame rate is any frame rate value within the frame rate switching range of the frame rate switching control module (fig. 4 and column 3, line 58 – column 4, line 13, “Moreover, in step S206, the timing controller 10 may calculate the compensation value to compensate the brightness of the monitor according to the target brightness, the target frame rate, the plurality of second gamma groups included in the plurality of second pulse number transformations and the calculation method. In an embodiment, the target frame rate may be arbitrarily changed within the application frequency range of the plurality of frame rates. For example, the target frame rate may be selected to be 50 Hz and 80 Hz with gamma group stored in the memory 30, or any frequency such as 57 Hz and 88 Hz between the application frequency range 30 Hz to 120 Hz. In another embodiment, when the target frame rate is 57 Hz, the target brightness equals 05 and the target pulse number equals 4, the timing controller 10 may select the Gamma Group 1 corresponding to 50 Hz and the Gamma Group 2 corresponding to 80 Hz, and calculate the compensation value to compensate the brightness and the color of the monitor according to the calculation method. For example, as shown in the following equation (1), the timing controller 10 calculates the compensation value Gout to compensate the brightness and the color of the monitor according to an interpolation algorithm”).
While Shih discloses that the first signal is a display signal to be supplied to an OLED (Shih: column 3, lines 36-57) without specifying that the first signal is a first image signal, it has been known in the art that the display data signal sent to the display panel pixel/subpixel units is an image signal. In a similar field of endeavor of display devices, Lee ‘289 discloses the display data receiving module is configured to receive a first image signal ([0025], “The host processor 110 may generate input image data IDAT to be displayed on the display panel 122, and transmit the input image data DAT and a control command CMD to the display driving circuit 121. For example, the control command CMD may include setting information about luminance, gamma, a frame frequency, an operating mode of the display driving circuit 121, and the like. The host processor 110 may transmit a clock signal, a synchronization signal, or the like to the display driving circuit 121”).
In view of the teachings of Shih and Lee ‘289 it would have been obvious to one of ordinary skill in the art to send an image signal to a display driving circuit of Lee ‘289 in the system of Shih, for the purpose of providing details of the specific signal sent to the display driving circuit to implement the generally described data signal in Shih, in order for specific implementation, and furthermore to reduce deterioration in image quality and prevent, or reduce, flicker when implementing display driving setting control for the image signal (Lee ‘289: [0006] and [0025]) which Shih also similarly utilizes display frame rate control for the data signal to the display panel (Shih: column 3, lines 36-57).
Regarding claim 4, the combination of Shih and Lee ‘289 further discloses wherein the target frame rate is between a first frame rate grade and a second frame rate grade adjacent among the plurality of frame rate grades; and
the display control chip further comprises a calculation module, the calculation module being configured to calculate the display parameter corresponding to the target frame rate based on a formula {(A-B)*(B-C)/M-m}, wherein
B represents the target frame rate, A represents a frame rate corresponding to the first frame rate grade, C represents a frame rate corresponding to the second frame rate grade, M represents a maximum frame rate switchable by the frame rate switching control module, and m represents a minimum frame rate switchable by the frame rate switching control module (Lee ‘289: [0120]-[0121], “When the frame rate FR of the k-th frame is 90 Hz, lookup tables each corresponding to a frame rate less than 90 Hz include the first lookup table LUT1 and the second lookup table LUT2. A lookup table corresponding to the highest frame rate FR among the first lookup table LUT1 and the second lookup table LUT2 is the second lookup table LUT2. Lookup tables each corresponding to a frame rate greater than 90 Hz are the third lookup table LUT3 and the fourth lookup table LUT4. Among the third lookup table LUT3 and the fourth lookup table LUT4, the third lookup table LUT3 corresponds to the lowest frame rate FR. The correction control logic 710 may generate a lookup table LUTA corresponding to 90 Hz, based on the second lookup table LUT2 and the third lookup table LUT3. The lookup table LUTA corresponding to 90 Hz may be calculated by Equation 1.
LUTA={LUT2*(FR 90−FR 80)+LUT3*(FR 100−FR 90)}/(FR 100−FR 80) [Equation 1]
The correction control logic 710 may correct the (k+1)th frame data by using the lookup table LUTA corresponding to 90 Hz.” Where FR100-FR80 would represent the maximum minus the minimum as the denominator and the numerator includes FR100-FR90 times FR90-FR80).
Regarding claim 5, the combination of Shih and Lee ‘289 further discloses wherein the frame rate switching range is between the minimum frame rate m and the maximum frame rate M switchable by the frame rate switching control module, the number of gamma modules in the plurality of gamma modules is p, the number of frame rate grades is p, and a frame rate difference between the first frame rate grade and second frame rate grade adjacent among the plurality of frame rate grades is greater than or equal to M/p and less than or equal to 2M/p (Shih: fig. 4 and column 3, lines 42-57: “Each pulse number transformation further contains the gamma groups respectively corresponding to 30 Hz, 40 Hz, 50 Hz, 60 Hz, 70 Hz, 80 Hz, 90 Hz, 100 Hz, 110 Hz and 120 Hz, wherein an application frequency range is 30 Hz-120 Hz. In the practical application of OLED monitors, the pulse width modulation may be used to generate signals with different pulse numbers to control the brightness. For example, when the target brightness equals 05, the timing controller 10 may select 2 pulse number transformations corresponding to 4 and 8 pulse numbers according to the practical application, and make the pulse number transformation with 4 pulse numbers include the Gamma Group 0-4 respectively corresponding to 30 Hz, 50 Hz, 80 Hz, 110 Hz and 120 Hz, and the pulse number transformation with 8 pulse numbers include the Gamma Group 5-7 respectively corresponding to 30 Hz, 80 Hz and 120 Hz”).
Regarding claim 6, the combination of Shih and Lee ‘289 further discloses wherein the frame rate switching control module comprises at least one of a first switching unit or a second switching unit;
the first switching unit is configured to adjust an idle interval between any two adjacent image frames in the first image signal to a target idle interval to obtain the corresponding second image signal, wherein the target idle interval is determined based on the target frame rate (Shih: column 3, line 58- column 4, line 9: “the timing controller 10 may calculate the compensation value to compensate the brightness of the monitor according to the target brightness, the target frame rate, the plurality of second gamma groups included in the plurality of second pulse number transformations and the calculation method. In an embodiment, the target frame rate may be arbitrarily changed within the application frequency range of the plurality of frame rates. For example, the target frame rate may be selected to be 50 Hz and 80 Hz with gamma group stored in the memory 30, or any frequency such as 57 Hz and 88 Hz between the application frequency range 30 Hz to 120 Hz. In another embodiment, when the target frame rate is 57 Hz, the target brightness equals 05 and the target pulse number equals 4, the timing controller 10 may select the Gamma Group 1 corresponding to 50 Hz and the Gamma Group 2 corresponding to 80 Hz, and calculate the compensation value to compensate the brightness and the color of the monitor according to the calculation method”); and
the second switching unit is configured to interpolate a target image frame between any two adjacent image frames in the first image signal to obtain the corresponding second image signal, wherein the target image frame is determined based on the target frame rate (Shih: --column 4, lines 10-13, “the timing controller 10 calculates the compensation value Gout to compensate the brightness and the color of the monitor according to an interpolation algorithm).
Claim 7-10 are within the scope of claim 6 and are therefore interpreted and rejected based on similar reasoning.
Regarding claim 12, the combination of Shih and Lee ‘289 further discloses a display panel (Lee ‘289: fig. 1, display device 120), comprising a display module (Lee ‘289: display panel 122) and a display control chip (Lee ‘289: display driving circuit 121), wherein the display control chip is within the scope of the display control chip of claim 1 and is therefore interpreted and rejected based on similar reasoning, wherein the display module is electrically connected to the display control chip (Lee ‘289: fig. 1); and
the display module is configured to receive and display the second image signal output by the display control chip, wherein a display frame rate of the display module matches the target frame rate (Lee ‘289: [0004], “In order to reduce or prevent tearing, a variable frame mode, that is, a variable refresh rate (VRR) mode, may be used in which the host processor changes a blank period for each frame and provides frame data to the display device at a variable frame rate. The VRR mode may include a free-sync mode and a G-sync mode”).
Regarding claim 13, the combination of Shih and Lee ‘289 further discloses wherein the display module comprises a display part and a driving part electrically connected to the display part, wherein the driving part drives the display part to display images and the display control chip is integrated into the driving part; and the display frame rate of the display module is the same as the target frame rate (Shih: column 3, line 58- column 4, line 9: “the timing controller 10 may calculate the compensation value to compensate the brightness of the monitor according to the target brightness, the target frame rate, the plurality of second gamma groups included in the plurality of second pulse number transformations and the calculation method. In an embodiment, the target frame rate may be arbitrarily changed within the application frequency range of the plurality of frame rates. For example, the target frame rate may be selected to be 50 Hz and 80 Hz with gamma group stored in the memory 30, or any frequency such as 57 Hz and 88 Hz between the application frequency range 30 Hz to 120 Hz. In another embodiment, when the target frame rate is 57 Hz, the target brightness equals 05 and the target pulse number equals 4, the timing controller 10 may select the Gamma Group 1 corresponding to 50 Hz and the Gamma Group 2 corresponding to 80 Hz, and calculate the compensation value to compensate the brightness and the color of the monitor according to the calculation method”).
Claims 16-17 are within the scope of claims 4-5 respectively and are therefore interpreted and rejected based on similar reasoning.
Regarding claim 18, the combination of Shih and Lee ‘289 further discloses an electronic device (Lee ‘289, fig. 1), comprising a system-level chip (Lee ‘289: fig. 1, host processor 110) and a display panel within the scope of the display panel of claim 12 and therefore interpreted and rejected based on similar reasoning,
wherein the system-level chip is electrically connected to the display data receiving module (Lee ‘289: [0027] “The host processor 110 may be a graphics processor. However, the inventive concepts are not limited thereto, and the host processor 110 may include various types of processors such as a central processing unit (CPU), a microprocessor, a multimedia processor, an application processor, and the like. In some example embodiments, the host processor 110 may be implemented as an integrated circuit (IC) or a system on chip (SoC)”), and the display data receiving module is configured to receive the first image signal output by the system-level chip (Lee ‘289: [0028], “The display device 120 may display the input image data IDAT received from the host processor 110”).
Claim 19 is within the scope of claim 13 and is therefore interpreted and rejected based on similar reasoning.
Regarding claim 20, the combination of Shih and Lee ‘289 further discloses a display processing method, applied to the electronic device according to claim 18, wherein a display control chip of the electronic device comprises a frame rate switching control module and a plurality of gamma modules, and the method comprises:
receiving, by the display data receiving module, a first image signal sent by the system-level chip (Lee ‘289: [0027] “The host processor 110 may be a graphics processor. However, the inventive concepts are not limited thereto, and the host processor 110 may include various types of processors such as a central processing unit (CPU), a microprocessor, a multimedia processor, an application processor, and the like. In some example embodiments, the host processor 110 may be implemented as an integrated circuit (IC) or a system on chip (SoC)”);
adjusting, by the frame rate switching control module, a frame rate of the first image signal to a target frame rate to obtain a corresponding second image signal; determining, by the plurality of gamma modules, a display parameter corresponding to the target frame rate; and outputting corresponding display content based on the second image signal and the display parameter corresponding to the target frame rate (Shih: fig. 4 and column 3, line 58 – column 4, line 13, “Moreover, in step S206, the timing controller 10 may calculate the compensation value to compensate the brightness of the monitor according to the target brightness, the target frame rate, the plurality of second gamma groups included in the plurality of second pulse number transformations and the calculation method. In an embodiment, the target frame rate may be arbitrarily changed within the application frequency range of the plurality of frame rates. For example, the target frame rate may be selected to be 50 Hz and 80 Hz with gamma group stored in the memory 30, or any frequency such as 57 Hz and 88 Hz between the application frequency range 30 Hz to 120 Hz. In another embodiment, when the target frame rate is 57 Hz, the target brightness equals 05 and the target pulse number equals 4, the timing controller 10 may select the Gamma Group 1 corresponding to 50 Hz and the Gamma Group 2 corresponding to 80 Hz, and calculate the compensation value to compensate the brightness and the color of the monitor according to the calculation method. For example, as shown in the following equation (1), the timing controller 10 calculates the compensation value Gout to compensate the brightness and the color of the monitor according to an interpolation algorithm”).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang et al. (US PGPub 2023/0335049) discloses “For each individual frame refresh rate or FPS, the display panel may store different gamma tables for different panel display brightness value (DBV) ranges” ([0045])
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY J FRANK whose telephone number is (571)270-7255. The examiner can normally be reached Monday-Thursday 8AM-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EJF/
/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629
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