DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “display data receiving module”, “frame rate switching control module”, “gamma modules”, “first switching unit”, and “second switching unit” in claims 1-20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
The modules of claims 1-20 are elements interpreted under 35 U.S.C. 112(f) and the circuitry is based on the description in the specification. Specifically, Fig. 12 and [0134]-[0135] show a hardware structure of an electronic device according to an embodiment of the application including a processor encoded with software having the described operations and functions as disclosed throughout the Specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US PGPub 2022/0114956) in view of Lee et al. (US PGPub 2023/0083289) hereinafter referred to as Lee ‘289 and Peng et al. (US PGPub 2019/0237021).
Regarding claim 1, Lee discloses a display control chip (fig. 1, display driver integrated circuit 200), comprising a display data receiving module and a frame rate switching control module, wherein the display data receiving module is configured to receive a first ([0052], “The display driver integrated circuit 200 may change the data transmitted from the processor 140 into a form capable of being transmitted to the display panel 160”); and the frame rate switching control module is configured to adjust a frame rate of the first ([0053], “the display driver integrated circuit 200 may change the driving frequency of the display panel 160 (e.g., change from 60 Hz to 120 Hz or vice versa (change from 120 Hz to 60 Hz), change from 60 Hz to 90 Hz or vice versa, or change from 60 Hz to 30 Hz, or vice versa), depending on at least one of the type of content requested to be played back and a user setting”…“the display driver integrated circuit 200 may determine the luminance value of the display panel 160, and may differently determine at least one of the number, values, or holding times of intermediate driving frequencies (frequencies between the current driving frequency and the target driving frequency), depending on the determined luminance value”).
While Lee discloses a first signal transmitted from the processor (Lee: [0052]) without specifying what is included in the data signal, it has been known that an image signal could be sent from a processor to a display driving circuit. In a similar field of endeavor of display devices, Lee ‘289 discloses the display data receiving module is configured to receive a first image signal ([0025], “The host processor 110 may generate input image data IDAT to be displayed on the display panel 122, and transmit the input image data DAT and a control command CMD to the display driving circuit 121. For example, the control command CMD may include setting information about luminance, gamma, a frame frequency, an operating mode of the display driving circuit 121, and the like. The host processor 110 may transmit a clock signal, a synchronization signal, or the like to the display driving circuit 121”).
In view of the teachings of Lee and Lee ‘289 it would have been obvious to one of ordinary skill in the art to send an image signal to a display driving circuit of Lee ‘289 in the system of Lee, for the purpose of providing details of the specific signal sent to the display driving circuit to implement the generally described data signal in Lee, in order for specific implementation and furthermore to reduce deterioration in image quality and prevent, or reduce, flicker (Lee ‘289: [0006]).
While the combination of Lee and Lee ‘289 teaches a display driver integrated chip to perform the various display and driving functions including those indicated above, it has been known to use a display chip and a driver chip to perform those display and driving functions. In a similar field of endeavor of display devices, Peng discloses display control circuitry, implemented by a discrete display chip with a driving chip of a display panel ([0109], “Data receiver 612 may be any suitable display interface between processor 114 and control logic 104, such as but not limited to DSI, DPI, and DBI by the MIPI Alliance, UDI, DVI, and DP. As described above, in some embodiments, control data and status information, such as information related to the division of the array of pixels into zones and information related to the pre-processing processes performed on the display data (e.g., display data compression and/or frame rate reduction) may be received by data receiver 612 from data transmitter 610 as well. It is to be appreciated that processor 114 and control logic 104 in this embodiment are two discrete components of display system 600, for example, in two separate chip packages. Control logic 104 in this embodiment is not an internal component as part of processor 114. Thus, data transmitter 610 of processor 114 transmits stream of display data 106 to data receiver 612 of control logic 104 via a display interface, such as but not limited to DSI, DPI, and DBI by the MIPI Alliance, UDI, DVI, and DP”).
In view of the teachings of Lee and Lee ‘289 which teaches using a single integrated circuitry to perform the various intended display and driving functions, and Peng which teaches that similar display control driving functions could be performed by a discreate display chip and a driving chip of a display panel, it would have been obvious to one of ordinary skill in the art to implement the integrated display control chip of Lee and Lee ‘289 by integrating the discrete display chip and display panel driving chip as known and taught by Peng, since the concept of simply having known function hardware or known equivalents integrated vs separate to provide the same known functions without unexpected functions or results does not constitute inventive step but rather obvious and within the skill level of one skilled in the art.
Regarding claim 2, the combination of Lee, Lee ‘289 and Peng further discloses wherein the display control chip further comprises a plurality of gamma modules, and the plurality of gamma modules are configured to calculate a display parameter corresponding to the target frame rate (Lee: [0047], “control of the size of the AMOLED off ratio (AOR) (e.g., duty off size) for each set luminance value of the display panel 160, or the gamma correction for each set luminance value of the display panel 160”), wherein
the display parameter comprises at least one of display brightness or color (Lee: [0044], “When the driving frequency change (e.g., refresh rate change) of the display panel 160 is requested in a state in which the luminance value of the display panel 160 is changed”).
Regarding claim 3, the combination of Lee, Lee ‘289 and Peng further discloses wherein the plurality of gamma modules correspond one-to-one with a plurality of frame rate grades, and the plurality of frame rate grades are determined based on the number of gamma modules in the plurality of gamma modules and a frame rate switching range of the frame rate switching control module (Lee ‘289: [0032], “[0032] The image corrector 124 may correct the input image data IDAT, based on the frame rate extracted by the frame rate extractor 123. In detail, the image corrector 124 may perform, based on the frame rate, color correction and gamma correction on the frame data included in input image data. In some example embodiments, the image corrector 124 may perform color correction and gamma correction on the input image data IDAT by using a lookup table corresponding to the extracted frame rate, and generate output image data”).
Regarding claim 4, the combination of Lee, Lee ‘289 and Peng further discloses wherein the target frame rate is between a first frame rate grade and a second frame rate grade adjacent among the plurality of frame rate grades; and
the display control chip further comprises a calculation module, the calculation module being configured to calculate the display parameter corresponding to the target frame rate based on a formula {(A-B)*(B-C)/M-m}, wherein
B represents the target frame rate, A represents a frame rate corresponding to the first frame rate grade, C represents a frame rate corresponding to the second frame rate grade, M represents a maximum frame rate switchable by the frame rate switching control module, and m represents a minimum frame rate switchable by the frame rate switching control module (Lee ‘289: [0120]-[0121], “When the frame rate FR of the k-th frame is 90 Hz, lookup tables each corresponding to a frame rate less than 90 Hz include the first lookup table LUT1 and the second lookup table LUT2. A lookup table corresponding to the highest frame rate FR among the first lookup table LUT1 and the second lookup table LUT2 is the second lookup table LUT2. Lookup tables each corresponding to a frame rate greater than 90 Hz are the third lookup table LUT3 and the fourth lookup table LUT4. Among the third lookup table LUT3 and the fourth lookup table LUT4, the third lookup table LUT3 corresponds to the lowest frame rate FR. The correction control logic 710 may generate a lookup table LUTA corresponding to 90 Hz, based on the second lookup table LUT2 and the third lookup table LUT3. The lookup table LUTA corresponding to 90 Hz may be calculated by Equation 1.
LUTA={LUT2*(FR 90−FR 80)+LUT3*(FR 100−FR 90)}/(FR 100−FR 80) [Equation 1]
The correction control logic 710 may correct the (k+1)th frame data by using the lookup table LUTA corresponding to 90 Hz.” Where FR100-FR80 would represent the maximum minus the minimum as the denominator and the numerator includes FR100-FR90 times FR90-FR80).
Regarding claim 5, the combination of Lee, Lee ‘289 and Peng further discloses wherein the frame rate switching range is between the minimum frame rate m and the maximum frame rate M switchable by the frame rate switching control module, the number of gamma modules in the plurality of gamma modules is p, the number of frame rate grades is p, and a frame rate difference between the first frame rate grade and second frame rate grade adjacent among the plurality of frame rate grades is greater than or equal to M/p and less than or equal to 2M/p (Lee: [0077]-[0078], “In operation 407, the display driver integrated circuit 200 may determine whether the current luminance value of the display panel 160 is between a specified minimum value Lmin and a specified maximum value Lmax. The specified minimum value Lmin and maximum value Lmax may vary depending on at least one of a panel characteristic of the display panel 160, a usage time of the display panel 160, and types of executed contents. If the luminance value of the display panel 160 exists between the minimum value Lmin and the maximum value Lmax, in operation 409, the display driver integrated circuit 200 may change the current driving frequency to the target driving frequency based on the intermediate driving frequency.”).
Regarding claim 6, the combination of Lee, Lee ‘289 and Peng further discloses wherein the frame rate switching control module comprises at least one of a first switching unit or a second switching unit;
the first switching unit is configured to adjust an idle interval between any two adjacent image frames in the first image signal to a target idle interval to obtain the corresponding second image signal, wherein the target idle interval is determined based on the target frame rate (Lee: [0079], “If the luminance value of the display panel 160 does not exist between the minimum value Lmin and the maximum value Lmax, in operation 411, the display driver integrated circuit 200 may perform the change to the target driving frequency without determining and applying any separate intermediate driving frequency. For example, if the luminance value of the display panel 160 is less than or equal to the minimum value Lmin or equal to or greater than the maximum value, the display driver integrated circuit 200 may perform the change to the target driving frequency without employing any separate intermediate driving frequency. According to various embodiments of the disclosure, the display driver integrated circuit 200 may adjust at least one of the light emission cycle, the AOR, the driving speed, and the gamma correction table of the display panel 160 at the target driving frequency when the change to the target driving frequency is performed, and thus may perform control such that the optical characteristic of the display panel 160 at the target driving frequency is the same as or similar to the optical characteristic of the display panel 160 at the current driving frequency.”); and
the second switching unit is configured to interpolate a target image frame between any two adjacent image frames in the first image signal to obtain the corresponding second image signal, wherein the target image frame is determined based on the target frame rate (Lee: [0078], “If the luminance value of the display panel 160 exists between the minimum value Lmin and the maximum value Lmax, in operation 409, the display driver integrated circuit 200 may change the current driving frequency to the target driving frequency based on the intermediate driving frequency. In the process of changing, the display driver integrated circuit 200 may adjust at least one of the light emission cycle, the AOR, the driving speed, and the gamma correction table at each driving frequency (e.g., intermediate driving frequency and target driving frequency) in order to maintain the optical characteristic of the display panel 160.” and Lee ‘289: [0118], “when there is no lookup table corresponding to the frame rate FR of the k-th frame in the plurality of lookup tables, the correction control logic 710 may generate a lookup table corresponding to the frame rate FR of the k-th frame by using interpolation. Linear interpolation and nonlinear interpolation may be used”).
Claim 7-10 are within the scope of claim 6 and are therefore interpreted and rejected based on similar reasoning.
Regarding claim 11, the combination of Lee, Lee ‘289 and Peng further discloses wherein the target frame rate is any frame rate value within the frame rate switching range of the frame rate switching control module (Lee: [0044], “When the driving frequency change (e.g., refresh rate change) of the display panel 160 is requested in a state in which the luminance value of the display panel 160 is changed due to various reasons, the processor 140 may differently determine at least one of the numbers, values, or holding times of intermediate driving frequencies between the current driving frequency and the target driving frequency (e.g., a driving frequency value requested to be changed) depending on the size of the difference between the current luminance value of the display panel 160 and the target luminance value to be changed. For example, the processor 140 may allocate a greater number of intermediate driving frequencies as the difference of the luminance values increases. In this operation, the processor 140 may perform control such that the intermediate driving frequency values and holding times are allocated evenly or unevenly, or are allocated in a linear or nonlinear increasing manner, according to the number of allocated intermediate driving frequencies”).
Regarding claim 12, the combination of Lee, Lee ‘289 and Peng further discloses a display panel (Lee: fig. 1), comprising a display module (Lee: fig. 1, display panel 160) and a display control chip, wherein the display control chip is within the scope of the display control chip of claim 1 and is therefore interpreted and rejected based on similar reasoning, wherein the display module is electrically connected to the display control chip (Lee: fig. 1); and
the display module is configured to receive and display the second image signal output by the display control chip, wherein a display frame rate of the display module matches the target frame rate (Lee: [0050], “the display panel 160 may output a screen with the driving frequency depending on the driving of the display driver integrated circuit 200”).
Regarding claim 13, the combination of Lee, Lee ‘289 and Peng further discloses wherein the display module comprises a display part and a driving part electrically connected to the display part (Lee: [0052], “[0052] The display driver integrated circuit 200 may change the data transmitted from the processor 140 into a form capable of being transmitted to the display panel 160, and may transmit the changed data to the display panel 160”), wherein the driving part drives the display part to display images and the display control chip is integrated into the driving part; and the display frame rate of the display module is the same as the target frame rate (Lee: [0050], “the display panel 160 may output a screen with the driving frequency depending on the driving of the display driver integrated circuit 200”).
Claims 14-17 are within the scope of claims 2-5 respectively and are therefore interpreted and rejected based on similar reasoning.
Regarding claim 18, the combination of Lee, Lee ‘289 and Peng further discloses an electronic device (Lee, fig 1, and Lee ‘289, fig. 1), comprising a system-level chip (Lee ‘289: fig. 1, host processor 110) and a display panel within the scope of the display panel of claim 12 and therefore interpreted and rejected based on similar reasoning,
wherein the system-level chip is electrically connected to the display data receiving module (Lee ‘289: [0027] “The host processor 110 may be a graphics processor. However, the inventive concepts are not limited thereto, and the host processor 110 may include various types of processors such as a central processing unit (CPU), a microprocessor, a multimedia processor, an application processor, and the like. In some example embodiments, the host processor 110 may be implemented as an integrated circuit (IC) or a system on chip (SoC)”), and the display data receiving module is configured to receive the first image signal output by the system-level chip (Lee ‘289: [0028], “The display device 120 may display the input image data IDAT received from the host processor 110”).
Claim 19 is within the scope of claim 13 and is therefore interpreted and rejected based on similar reasoning.
Regarding claim 20, the combination of Lee, Lee ‘289 and Peng further discloses a display processing method, applied to the electronic device according to claim 18, wherein a display control chip of the electronic device comprises a frame rate switching control module and a plurality of gamma modules, and the method comprises:
receiving, by the display data receiving module, a first image signal sent by the system-level chip (Lee: [0052], “The display driver integrated circuit 200 may change the data transmitted from the processor 140 into a form capable of being transmitted to the display panel 160” where Lee ‘289 teaches an image signal);
adjusting, by the frame rate switching control module, a frame rate of the first image signal to a target frame rate to obtain a corresponding second image signal; determining, by the plurality of gamma modules, a display parameter corresponding to the target frame rate; and outputting corresponding display content based on the second image signal and the display parameter corresponding to the target frame rate (Lee: [0053], “the display driver integrated circuit 200 may change the driving frequency of the display panel 160 (e.g., change from 60 Hz to 120 Hz or vice versa (change from 120 Hz to 60 Hz), change from 60 Hz to 90 Hz or vice versa, or change from 60 Hz to 30 Hz, or vice versa), depending on at least one of the type of content requested to be played back and a user setting”…“the display driver integrated circuit 200 may determine the luminance value of the display panel 160, and may differently determine at least one of the number, values, or holding times of intermediate driving frequencies (frequencies between the current driving frequency and the target driving frequency), depending on the determined luminance value”).
Response to Arguments
Applicant’s arguments with respect to the claim amendment “a display control chip obtained by integrating a discrete display chip with a driving chip of a display panel” have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant's arguments filed 10/29/2025 have been fully considered but they are not persuasive. Regarding claim 1, Applicants argue “Lee also does not mention the concept of ‘image signal frame rate’ and only processes the frequency at the panel driving end. Therefore, Lee does not disclose, teach or suggest the feature ‘the frame rate switching control module is configured to adjust a frame rate of the first image signal to a target frame rate to obtain a corresponding second image signal’” (page 10, paragraph 3), however Examiner respectfully disagrees. Examiner maintains Lee ‘289 teaches at [0025] and [0026] the host processor may transmit a control command to the display driving circuit where the control command includes information about a frame frequency. Additionally, Lee ‘289 teaches the host processor may change a variable blank period of each frame, and may provide the input image data to the display device at a variable frame rate. Lee ‘289 teaches “the host processor 110 may include various types of processors such as a central processing unit (CPU), a microprocessor, a multimedia processor, an application processor, and the like. In some example embodiments, the host processor 110 may be implemented as an integrated circuit (IC) or a system on chip (SoC)” ([0027]). Therefore, the combination of Lee, Lee ‘289 and Peng teaches the limitations of claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Xie (CN116568090A) discloses “Compared with the prior art, the invention adopts the discrete display architecture, namely the original integrated display driving chip is divided into the driving chip and the display chip, the driving chip and the display chip are connected through a plurality of differential lines, and the driving chip and the display chip are manufactured by adopting different manufacturing processes, so that on one hand, the manufacturing cost of the chip can be effectively reduced, the packaging form is simpler, on the other hand, the number of connecting lines between the chips can be reduced, and the signal transmission speed and the anti-interference capability between the chips are improved” (page 3).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY J FRANK whose telephone number is (571)270-7255. The examiner can normally be reached Monday-Thursday 8AM-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EJF/
/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629
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