Prosecution Insights
Last updated: October 02, 2026
Application No. 18/884,073

MEMS SENSOR

Non-Final OA §102§103
Filed
Sep 12, 2024
Priority
Mar 16, 2022 — JP 2022-041601 +1 more
Examiner
DUNLAP, JONATHAN M
Art Unit
Tech Center
Assignee
Rohm Co., Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
693 granted / 910 resolved
+16.2% vs TC avg
Strong +17% interview lift
Without
With
+17.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
25 currently pending
Career history
929
Total Applications
across all art units

Statute-Specific Performance

§101
3.9%
-36.1% vs TC avg
§103
46.0%
+6.0% vs TC avg
§102
24.9%
-15.1% vs TC avg
§112
21.4%
-18.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 910 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 6, 8-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yazawa et al. (US 2015/0008544 A1). Considering claim 1, Yazawa discloses a MEMS sensor comprising: - a semiconductor substrate 30 (SOI substrate; Figures 1-2; [0047-50]); - a sensor unit 3a-3d formed on the semiconductor substrate (piezoresistive layers 2; Figure 1; [0051-54]) - a pad unit 9a-9d, 8 formed on the semiconductor substrate (Figure 1; [0053-56]); and - a connection wiring 7a,7b formed on the semiconductor substrate and connecting the sensor unit 3a-3d and the pad unit 9a-9d (Figures 1 and 3-4; [0052-53], [0058], [0065-68], wherein the connection wiring is a semiconductor wiring formed from a semiconductor material ([0066], 7a,7b formed by doping impurity into an N-type impurity layer making up the silicon substrate; [0057], doping by boron; [0084-86], 7a,7b formed by doping P-type impurity boron into silicon substrate 31). Considering claim 2, Yazawa discloses the connection wiring is formed from a semiconductor material having a linear expansion coefficient equivalent to that of the semiconductor substrate ([0057], doping by boron with concentration of at least 1017-18/cm3; [0084-86], 7a,7b formed by doping P-type impurity boron into silicon substrate 31, whereby this concentration inherently provides a negligible change in TCE of silicon). Considering claim 3, Yazawa discloses that the semiconductor substrate is a silicon substrate (SOI substrate; Figures 1-2; [0047-50]), and the connection wiring is formed from silicon (([0066], 7a,7b formed by doping impurity into an N-type impurity layer making up the silicon substrate; [0057], doping by boron; [0084-86], 7a,7b formed by doping P-type impurity boron into silicon substrate 31). Considering claim 4, Yazawa discloses that the connection wiring is a diffusion wiring formed by introducing an impurity into the semiconductor substrate ([0066], 7a,7b formed by doping impurity into an N-type impurity layer making up the silicon substrate; [0057], doping by boron; [0084-86], 7a,7b formed by doping P-type impurity boron into silicon substrate 31). Considering claim 6, Yazawa discloses that the connection wiring 7a,7b has same width as the pad unit 8 in plan view (Figure 1). It is noted that Figures 6-7 of the instant invention and [0046-47] merely require a portion of the connection wiring to have the same width as the pad, not the entirety of the connection wiring. Considering claim 8, Yazawa discloses that the semiconductor substrate includes a diaphragm 21, and the sensor unit 2 is provided on the diaphragm (Figure 1; [0050-52]). Considering claim 9, Yazawa discloses that the diaphragm is formed in a quadrangular shape in plan view (Figure 1 shows a diaphragm having four side portions, four chambered corners, as required by [0010] of the instant application and “two sides extending parallel to the X direction and two sides extending parallel to the Y direction in plan view” as understood from [0021] of the instant application), and the sensor unit 3a-3d includes a piezoresistive element 2 formed on each side portion of the diaphragm (Figure 1). Considering claim 10, Yazawa discloses that the plurality of the connection wirings connecting the sensor unit and the pad unit are formed on the semiconductor substrate, and the plurality of connection wirings form a bridge circuit including a piezoresistive element formed on each side portion of the diaphragm (Figure 5; [0060]). Considering claim 11, Yazawa discloses that a cavity 23 is formed in the semiconductor substrate 31, and the cavity is sealed by the diaphragm 21 (Figures 1-2; [0050]). Considering claim 12, Yazawa discloses that the semiconductor substrate includes a first semiconductor substrate 32 having a cavity 23 and a second semiconductor substrate 31 having a diaphragm 21 covering the cavity and joined to the first semiconductor substrate, and the sensor unit is provided on the diaphragm (Figures 1-2; [0050]). Considering claim 13, Yazawa discloses that the MEMS sensor is a pressure sensor ([0048]). Claims 1-4, 8-10 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tojo et al. (US 2008/0204185 A1). Considering claim 1, Tojo discloses a MEMS sensor comprising: - a semiconductor substrate 10 (Figures 1-3; [0024-25]); - a sensor unit 211-214 formed on the semiconductor substrate (Figure 2; [0025-26]); - a pad unit 251b-254b formed on the semiconductor substrate (Figure 2; [0029-30]); and - a connection wiring 222 (221-224) formed on the semiconductor substrate and connecting the sensor unit and the pad unit (Figure 2; [0027-33]). Considering claim 2, Tojo discloses the connection wiring is formed from a semiconductor material having a linear expansion coefficient equivalent to that of the semiconductor substrate ([0024]; [0033-34]). Considering claim 3, Tojo discloses that the semiconductor substrate is a silicon substrate, and the connection wiring is formed from silicon ([0024]; [0033]). Considering claim 4, Tojo discloses that the connection wiring is a diffusion wiring formed by introducing an impurity into the semiconductor substrate ([0033]). Considering claim 8, Yazawa discloses that the semiconductor substrate includes a diaphragm 11, and the sensor unit is provided on the diaphragm (Figures 1-3; [0025-26]). Considering claim 9, Yazawa discloses that the diaphragm is formed in a quadrangular shape in plan view (Figure 2), and the sensor unit includes a piezoresistive element formed on each side portion of the diaphragm (Figure 2; [0025-26]). Considering claim 10, Tojo discloses that the plurality of the connection wirings connecting the sensor unit and the pad unit are formed on the semiconductor substrate, and the plurality of connection wirings form a bridge circuit including a piezoresistive element formed on each side portion of the diaphragm ([0027-28]). Considering claim 13, Tojo discloses that the MEMS sensor is a pressure sensor ([0024-26]). Claims 1-3, 5, 8-10 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato et al. (US 2010/0242618 A1). Considering claim 1, Sato discloses a MEMS sensor comprising: - a semiconductor substrate 1 ([0044]; [0050]); - a sensor unit 7 formed on the semiconductor substrate ([0043-46]) - a pad unit 12 formed on the semiconductor substrate ([0047]; [0056]); and - a connection wiring 7a formed on the semiconductor substrate and connecting the sensor unit 7 and the pad unit 12 ([0046-47]; [0055-56]). Considering claim 2, Sato discloses the connection wiring is formed from a semiconductor material having a linear expansion coefficient equivalent to that of the semiconductor substrate ([0044]; [0046]; [0050]). Considering claim 3, Sato discloses that the semiconductor substrate is a silicon substrate ([0044]; [0050]), and the connection wiring is formed from silicon ([0044]; [0046]). Considering claim 5, Sato discloses that the connection wiring is a polycrystalline silicon wiring formed from polycrystalline silicon ([0046]; [0055]). Considering claim 8, Sato discloses that the semiconductor substrate includes a diaphragm 5 ([0044]), and the sensor unit 7 is provided on the diaphragm ([0043-46]). Considering claim 9, Sato discloses that the diaphragm 5 is formed in a quadrangular shape in plan view (Figure 1), and the sensor unit 7 includes a piezoresistive element formed on each side portion of the diaphragm (Figure 1; [0080], polysilicon has piezoresistance). Considering claim 10, Sato discloses that the plurality of the connection wirings connecting the sensor unit and the pad unit are formed on the semiconductor substrate, and the plurality of connection wirings form a bridge circuit including a piezoresistive element formed on each side portion of the diaphragm (Figure 3; [0046-47]). Considering claim 13, Sato discloses that the MEMS sensor is a pressure sensor ([0043-44]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yazawa et al. (US 2015/0008544 A1) in view of Suresh (US 2020/0278265 A1). It is noted that any combination of Suresh with Tojo or Sato would also be applicable for the same rationale. Considering claim 7, Yazawa discloses that a plurality of the sensor units 3a-3d and a plurality of the pad units 9a-9d are formed on the semiconductor substrate, a plurality of the connection wirings 7a,7b connecting the sensor unit and the pad unit are formed on the semiconductor substrate (Figure 1), but fails to explicitly disclose that the connection wirings are formed to have equivalent electric resistance values. However, Suresh teaches the technique of balancing electrical resistance values of Wheatstone bridge connection leads ([0161-162]; [0147-148]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize connection wirings that are formed to have equivalent electric resistance values, as taught by Suresh, in the invention by Yazawa. The motivation for doing so, as understood from Yazawa, it to provide a balanced initial bridge so that actual measurement mismatches will indicate sensor damage ([0161], [0169]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. WO 2017/073207 A1 discloses a semiconductor based pressure sensor having a plurality of piezoresistive sensors on a diaphragm, whereby diffusion wirings connect one end of piezoresistive sensors with metal wirings and pad portions. Inoue discloses silicon based pressure sensor having a plurality of piezoresistive sensors connected by diffusion wiring to terminal pads. Kurtz teaches providing bridge balance by customizing the resistance of contact leads. CN 1433094 A discloses a semiconductor pressure sensor having piezoresistive sensors connected to terminal pads with highly doped connecting leads. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jonathan M Dunlap whose telephone number is (571)270-1335. The examiner can normally be reached Mon-Fri 10AM - 7PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Peter Macchiarolo can be reached at 571-272-2375. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JONATHAN M DUNLAP/Primary Examiner, Art Unit 2855 August 31, 2026
Read full office action

Prosecution Timeline

Sep 12, 2024
Application Filed
Sep 02, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
93%
With Interview (+17.0%)
2y 5m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 910 resolved cases by this examiner. Grant probability derived from career allowance rate.

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