Detailed Action
This Office Action is sent in response to Applicant’s Communication received on 09/13/2024 for application number 18/884,174. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, IDS, and Claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The instant application claims priority to provisional application number 63/585,612, filed on 09/27/2023.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 6, the limitation “a central processing unit, configured to perform a synchronization source selector, a distributed unit component, and a central unit component” is indefinite, as it is unclear whether the synchronization source selector, distributed unit component, and central unit component are performed by the central processing unit or are intended to be separate units within the first processing circuit of Claim 1. The specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Paragraph 33 of the specification notes that in practical applications, the synchronization source selector, distributed unit component, and central unit component can be implemented with software hardware, or a combination of software and hardware. For purposes of examination and in light of the specification, the limitation is interpreted to mean: wherein the synchronization source selector is a program executed by the central processing unit, wherein a distributed unit component, and a central unit component are hardware components.
Regarding Claims 7-17, the dependent claims do not further define the synchronization source selector, a distributed unit program, and the central unit component, and thus inherit the deficiencies of their parent claim and are rejected accordingly.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US 2018/0115478 A1), and in view of SANTOSA et al. (US 6,819,150 B1).
Regarding Claim 1, KIM discloses:
A cell site device in a radio access network [system 50, FIG. 2; timestamp generator 52 included in system 50 receives GPS signal 62 (i.e. part of a radio access network), par. 28], comprising:
a clock synchronizer, configured to generate a first operation clock and a second operation clock [GPS receiver 60 generates clocks CLK_1 (i.e. a SECOND operation clock) and CLK_2 (i.e. a FIRST operation clock), par. 28];
a first processing circuit, electrically connected to the clock synchronizer [a detector 66 (i.e. a first processing circuit) connected to GPS receiver 60],
configured to receive the first operation clock [Detector 66 receives CLK_2, FIG. 2],
and generate a cross-unit periodic synchronization signal [The detector 66 can provide an output (i.e. a cross-unit periodic synchronization signal) in response to detecting a positive edge on CLK_2, par. 31];
and a second processing circuit, electrically connected to the clock synchronizer and the first processing circuit [pulse generator 68 (i.e. second processing unit), connected to gps receiver 60 (i.e. clock synchronizer) and detector 68 (i.e. first processing circuit), FIG. 2],
configured to receive the second operation clock from the clock synchronizer [pulse generator 68 receives CLK_1 from GPS receiver 60, FIG. 2],
and receive the cross-unit periodic synchronization signal from the first processing circuit [The detector 66 can provide an output to an input of the pulse generator (i.e. the second processing circuit receives a signal from first processing circuit) in response to detecting a positive edge on CLK_2 (i.e. the cross-unit periodic synchronization signal), par. 31].
KIM does not explicitly disclose a first processing circuit configured to generate a synchronizer setting signal, and transmit the synchronizer setting signal to the clock synchronizer.
However, in the analogous art of adjusting clock generation, SANTOSA teaches a first circuit generating a synchronizer setting signal [event generator 60 generates a fast/slow select mode 110 (i.e. a synchronizer setting signal), FIG. 1; Column 3 Lines 4-8.],
and transmitting the synchronizer setting signal to a clock synchronizer [event generator 60 sends signal 110 to synchronizer circuit 90, FIG. 1].
It would have been obvious to one of ordinary skill in the art, having the teachings of KIM and SANTOSA before him before the effective filling date of the claimed invention, to incorporate generating and transmitting a synchronizer setting signal as taught by SANTOSA into the device as disclosed by KIM in order to switch between multiple clock frequencies, increasing power saving [SANTOSA Column 1 Lines 40-42].
Regarding Claim 3, KIM in view of SANTOSA teaches the device of Claim 1 as applied above.
SANTOSA further teaches an oscillator, electrically connected to the clock synchronizer [slow clock source 10 (i.e. an oscillator) connected to synchronizer circuit 90 (i.e. a clock synchronizer), FIG. 1], configured to provide an internal clock signal to the clock synchronizer [slow clocking source 10 generates a slow clocking signal to circuit A 30 located inside synchronizer circuit 90, FIG. 1, Column 2 Lines 56-61; slow clocking source 10 and synchronizer 90 are part of power saving management circuit 150 (i.e. clock signal is an internal clock signal), Column 2 Lines 54-56].
Regarding Claim 20, KIM discloses a clock synchronization method [a method utilizing system 50 of FIG. 2, FIG. 7, par. 47],
and a processing circuit generating a signal according to an external clock synchronization source and another clock [timestamp generator 158 (i.e. a processing circuit) is configured to generate an extended timestamp TS (i.e. a signal) based on a combination of the time references produced by reference generators 159 and 160, par. 57; reference generator 159 generates a clock (i.e. another clock), par. 56; reference generator 158 provides a coarse time reference derived from PTP (i.e. an external clock synchronization source), par. 56].
The remainder of Claim 20 recites limitations similar to those of Claim 1, and is rejected accordingly.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of SANTOSA as applied to Claim 1, and further in view of HEO et al. (US 2016/0066280 A1).
Regarding Claim 2, KIM in view of SANTOSA teaches the device of Claim 1 as applied above.
KIM in view of SANTOSA does not explicitly teach wherein the clock synchronizer adjusts the first operation clock and the second operation clock according to the synchronizer setting signal.
However, in the analogous art of clock management, HEO teaches wherein a clock synchronizer adjusts a first operation clock and a second operation clock according to a signal [CLK divider 332 adjusts a first and second operating clock in response to a received alarm signal (i.e. a signal), par. 91].
It would have been obvious to one of ordinary skill in the art, having the teachings of KIM, SANTOSA, and HEO before him before the effective filling date of the claimed invention, to incorporate adjusting the operation clocks according to a signal as taught by HEO into the device as taught by KIM in view of SANTOSA in order to extend operation of a device despite lower battery conditions and sudden momentary power loss [HEO par. 52].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of SANTOSA as applied to Claim 3, and further in view of JUNG et al. (US 2016/0162001 A1).
Regarding Claim 4, KIM in view of SANTOSA teaches the device of Claim 3 as applied above.
KIM in view of SANTOSA does not explicitly teach a frequency of the first operation clock higher than a frequency of the second operation clock, and the frequency of the second operation clock higher than a frequency of the internal clock signal.
However, in the analogous art of clock frequency adjustment, JUNG teaches a frequency of a first operation clock higher than a frequency of a second operation clock, and the frequency of the second operation clock higher than a frequency of a reference clock [second minimum INT clock INT_MIN_CLK2 (i.e. a second operation clock) generated by INT clock generating unit 124 has a clock rate higher than that of the reference clock REF_CLK (i.e. the reference clock), but lower than that of the original INT clock INT_CLK (i.e. a first operation clock), par. 52].
It would have been obvious to one of ordinary skill in the art, having the teachings of KIM, SANTOSA, and JUNG before him before the effective filling date of the claimed invention, to incorporate a second operation clock being lower than a first operation clock but higher than the reference clock as taught by JUNG into the device as taught by KIM in view of SANTOSA in order to reduce power consumption in a lower power mode [JUNG par. 9].
Claims 5, 6, 7, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of SANTOSA as applied to Claim 1, and further in view of ELLENBECK et al. (US 2021/0243713 A1).
Regarding Claim 5, KIM in view of SANTOSA teach the device of Claim 1 as applied above.
KIM in view of SANTOSA does not explicitly teach wherein the first processing circuit generates the synchronizer setting signal according to an external clock synchronization source if the external clock synchronization source is available, wherein the first processing circuit generates the synchronizer setting signal according to the first operation clock if the external clock synchronization source is unavailable.
However, in the analogous art of synchronization, ELLENBECK teaches wherein a first processing circuit generates the synchronizer setting signal according to an external clock synchronization source if the external clock synchronization source is available [Baseband modem 2506 alongside satellite receiver 2516 and satellite antenna system 2514 (i.e. wherein all of these components are interpreted to be a first processing circuit) contains sync controller 2512 configured to provide synchronization signals to transmitter 2510 (i.e. generate a synchronizer setting signal), par. 179; Sync controller 2512 synchronizes with a satellite-based synchronization source if it receives satellite-based synchronization signals from a satellite-based synchronization source (i.e. according to a an external clock synchronization source if it’s available), FIG. 25, par. 184],
wherein the first processing circuit generates the synchronizer setting signal according to the first operation clock if the external clock synchronization source is unavailable [sync controller 2512 (part of a first processing circuit) configured to provide synchronization signals to transmitter 2510 (i.e. generate a synchronizer setting signal), par. 179; If no external synchronization source is available, sync controller uses its internal device clock as an internal synchronization source (i.e. operation clock), FIG. 25, par. 184].
It would have been obvious to one of ordinary skill in the art, having the teachings of KIM, SANTOSA, and ELLENBECK before him before the effective filling date of the claimed invention, to incorporate choosing either an external or internal synchronization source depending on availability of the external source as taught by ELLENBECK into the device as taught by KIM in view of SANTOSA in order to avoid cluster segmentation in a wireless network [ELLENBECK par. 175].
Regarding Claim 6, KIM in view of SANTOSA and ELLENBECK teaches the device of Claim 5 as applied above.
ELLENBECK further teaches a central processing unit, configured to perform a synchronization source selector, a distributed unit component, and a central unit component [first processing circuit contains sync controller 2512 (i.e. central processing unit) configured to execute instructions that define the synchronization operations of wireless device 2500 (i.e. a synchronization source selector); sync controller 2512 also provides control signals to transmitter 2510 (i.e. a distributed unit component) and receiver 2508 (i.e. a central unit component) that control transmitter 2510 and receiver 2508 (i.e. performing a distributed unit component and central unit component), par. 179],
wherein the synchronization source selector provides a processing-circuit clock to the distributed unit component and the central unit component [sync controller 2512 (performing the synchronization source selector) may provide control settings containing a time and frequency reference (i.e. a processing-circuit clock) to transmitter 2510 and receiver 2508 (i.e. the distributed unit component and the central unit component), par. 179],
wherein the synchronization source selector generates the processing-circuit clock according to the external clock synchronization source if the external clock synchronization source is available [Sync controller 2512 (which performs a synchronizer source selector) synchronizes (correct timing and frequency (i.e. a clock) are types of synchronization settings) with a satellite-based synchronization source if it receives satellite-based synchronization signals from a satellite-based synchronization source (i.e. according to a an external clock synchronization source if it’s available), par. 184],
wherein the synchronization source selector selects the first operation clock to be the processing-circuit clock if the external clock synchronization source is unavailable [If no external synchronization source is available, sync controller 2512 (which performs a synchronization source selector) uses its internal device clock as an internal synchronization source (i.e. operation clock, selecting operating clock to be processing-circuit clock), par. 184].
Regarding Claim 7, KIM in view of SANTOSA and ELLENBECK teaches the device of Claim 6 as applied above.
KIM further teaches wherein the cross-unit periodic synchronization signal is generated once per second [output from detector 66 (i.e. cross-unit periodic synchronization signal) is generated in response to detecting a positive edge of CLK_2, par. 31; CLK_2 is provided at 1Hz, such as corresponding to the Coordinated Universal Time (UTC) second (i.e. generated once per second), par. 30].
Regarding Claim 17, KIM in view of SANTOSA and ELLENBECK teaches the device of Claim 6 as applied above.
ELLENBECK further teaches wherein a second processing circuit performs a radio unit component [RF transceiver 2504 modulates, transmits, receives, and demodulates radio signals (i.e. a second processing circuit performing a radio unit component), par. 178],
and the radio unit component exchanges synchronization-related information with the distributed unit component [transmitter 2510 (i.e. a distributed unit component) provides signals to RF transceiver 2504 (i.e. radio unit) for broadcast to other devices; signals are synchronization signals (i.e. synchronization-related information) sent by sync controller 2512 to transmitter 2510 for broadcast, par. 179].
Regarding Claim 19, KIM in view of SANTOSA teach the device of Claim 1 as applied above.
KIM in view of SANTOSA does not explicitly teach wherein the cell site device is in communication with a plurality of user equipment.
However, in the analogous art of node synchronization, ELLENBECK teaches a cell site device in communication with a plurality of user equipment [network access node 110 (i.e. cell site device) provide radio access network (i.e. in communication) to terminal devices 102, par. 63; terminal devices are user equipment, par. 62].
It would have been obvious to one of ordinary skill in the art, having the teachings of KIM, SANTOSA, and ELLENBECK before him before the effective filling date of the claimed invention, to incorporate a device in communication with a plurality of user equipment as taught by ELLENBECK into the device as taught by KIM in view of SANTOSA in order to maximize the probability that all wireless devices are synchronized with the same synchronization source [ELLENBECK par. 175].
Claims 8, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of SANTOSA and ELLENBECK as applied to Claim 6 above, and further in view of RANGANATHAN et al. (US 10,608,647 B1).
Regarding Claim 8, KIM in view of SANTOSA and ELLENBECK teaches the device of Claim 6 as applied above.
KIM in view of SANTOSA and ELLENBECK does not explicitly teach wherein the external clock synchronization source is one of a global navigation satellite system (GNSS)-based periodic synchronization signal, a plurality of precision time protocol timestamps, and a synchronous Ethernet clock signal.
However, in the analogous art of clock synchronization, RANGANATHAN teaches wherein an external clock synchronization source is one of a global navigation satellite system (GNSS)-based periodic synchronization signal, a plurality of precision time protocol timestamps, and a synchronous Ethernet clock signal [network clock signal IN (i.e. external clock synchronization source) is based on an atomic clock reference (e.g., SyncE (i.e. synchronous Ethernet), GPS (i.e. GNSS-based periodic synchronization signal), SONET, or PTP timestamps), Column 5 Lines 63-66].
It would have been obvious to one of ordinary skill in the art, having the teachings of KIM, SANTOSA, ELLENBECK, and RANGANATHAN before him before the effective filling date of the claimed invention, to incorporate an external clock synchronization signal being of multiple types of clock references as taught by RANGANATHAN into the device as taught by KIM in view of SANTOSA and ELLENBECK in order to incorporate multiple methods that improve clock accuracy and satisfy timing requirements [RANGANATHAN Column 1 Lines 13-31].
Regarding Claim 9, KIM in view of SANTOSA, ELLENBECK, and RANGANATHAN teaches the device of Claim 8 as applied above.
ELLENBECK further teaches wherein the first processing circuit further comprises: a GNSS antenna, in communication with at least one GNSS satellite [satellite antenna 2514 (i.e. a GNSS antenna, interpreted as part of a first processing circuit as applied in Claim 5) receives satellite signals from a GNSS satellite, configured to generate a GNSS interface signal according to a GNSS signal received from the at least one GNSS satellite [satellite antenna 2514 sends signals to satellite receiver 2516 (i.e. GNSS interface signal according to a GNSS signal received), par. 180];
And a GNSS receiver, electrically connected to the GNSS antenna and the central processing unit [satellite receiver 2516 (interpreted as part of a first processing circuit as applied in Claim 5) receives signals from antenna 2514 and sends info to sync controller (i.e. central processing unit, electrically connected to both modules), FIG. 25, par. 180],
configured to receive the GNSS interface signal and generate a GNSS-based periodic synchronization signal [satellite receiver receives signals from satellite antenna 2514 and processes them to determine a satellite time (i.e. a GNSS-based periodic synchronization signal), par. 180].
Regarding Claim 11, KIM in view of SANTOSA, ELLENBECK, and RANGANATHAN teaches the device of Claim 9 as applied above.
ELLENBECK further teaches wherein the synchronization source selector generates the processing-circuit clock according to the GNSS-based periodic synchronization signal if the GNSS receiver generates the GNSS-based periodic synchronization signal [sync controller 2512 (which performs synchronization source selector) may use the satellite signal (i.e. the GNSS-based periodic synchronization signal) sent from satellite receiver 2516 (i.e. the GNSS receiver) as a satellite-based synchronization source (i.e. generating clock using the GNSS signal if it’s sent by the satellite receiver 2615), par. 180].
Claims 10, 13, 14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of SANTOSA, ELLENBECK and RANGANATHAN as applied to Claim 9 above, and further in view of BYAGOWI et al. (US 11,616,587 B1).
Regarding Claim 10, KIM in view of SANTOSA, ELLENBECK, and RANGANATHAN teaches the device of Claim 9 as applied above.
KIM in view of SANTOSA, ELLENBECK, and RANGANATHAN does not explicitly teach wherein the GNSS-based periodic synchronization signal is generated once per second.
However, in the analogous art of clock synchronization, BYAGOWI teaches wherein a GNSS-based signal is generated once per second [PPS generator outputs a square wave (i.e. generated) at the start of each second of time kept by atomic clocks of a GNSS (i.e. once per second), Column 6 Lines 64-66].
It would have been obvious to one of ordinary skill in the art, having the teachings of , KIM, SANTOSA, ELLENBECK, RANGANATHAN, and BYAWOGI before him before the effective filling date of the claimed invention, to incorporate a GNSS based signal generated once per second as taught by BYAWOGI into the device as taught by KIM in view of SANTOSA, ELLENBECK, and RANGANATHAN in order to improve reliability of GNSS time synchronization [BYAWOGI Column 2 Lines 41-46].
Regarding Claim 13, KIM in view of SANTOSA, ELLENBECK, and RANGANATHAN teaches the device of Claim 9 as applied above.
KIM in view of SANTOSA, ELLENBECK, and RANGANATHAN does not explicitly teach wherein the first processing circuit further comprises: a network interface circuit, configured to receive a network signal from a mobile network.
However, in the analogous art of clock synchronization, BYAGOWI teaches a network interface circuit, configured to receive a network signal from a mobile network [computer device 400 (a computer system 206 of FIG. 2) includes network interface 416, coupled to receive information (i.e. a network signal) from a telecommunications network (i.e. a mobile network), FIG. 4, Column 10 Lines 12-18].
It would have been obvious to one of ordinary skill in the art, having the teachings of , KIM, SANTOSA, ELLENBECK, RANGANATHAN, and BYAWOGI before him before the effective filling date of the claimed invention, to incorporate a network interface receiving signals from a telecommunications network as taught by BYAWOGI into the device as taught by KIM in view of SANTOSA, ELLENBECK, and RANGANATHAN in order to improve time synchronization of devices in a network [BYAWOGI Column 2 Lines 41-45].
Regarding Claim 14, KIM in view of SANTOSA, ELLENBECK, RANGANATHAN, and BYAWOGI teaches the device of Claim 13 as applied above.
KIM further teaches wherein a network signal comprises a precision time protocol packet [time base interface 70 receives timestamps from data packets, par. 36; time base interface implements Precision Time Protocol (thus a packet is a precision time protocol packet), par. 37].
Regarding Claim 16, KIM in view of SANTOSA, ELLENBECK, RANGANATHAN, and BYAWOGI teaches the device of Claim 13 as applied above.
RANGANATHAN further teaches wherein the network signal comprises a synchronous Ethernet clock signal [network clock signal IN (i.e. external clock synchronization source) is based on an atomic clock reference (e.g., SyncE (i.e. synchronous Ethernet)), Column 5 Lines 63-66].
ELLENBECK further teaches wherein when the GNSS receiver does not generate the GNSS-based periodic synchronization signal, the first processing circuit generates the synchronizer setting signal, [If satellite receiver 2516 cannot reliably receive satellite-based synchronization signals from a satellite-based synchronization source (if receiver doesn’t receive signals, then it cannot generate the GNSS-based period synchronization signal based on the GNSS signal), sync controller 2512 (i.e. part of the first processing circuit) synchronizes with a satellite master, par. 184; Sync controller 2512 configured to provide synchronization signals to transmitter 2510 (i.e. generate a synchronizer setting signal), par. 179;
and the synchronization source selector generates the processing-circuit clock according to another synchronization source [Sync controller 2512 (which performs synchronizer source selector) synchronizes (correct timing and frequency (i.e. a clock) are types of synchronization settings) with a satellite master, par. 184].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of SANTOSA, ELLENBECK and RANGANATHAN as applied to Claim 9 above, and further in view of SCHUERMAN (US 2012/0259478 A1).
Regarding Claim 12, KIM in view of SANTOSA, ELLENBECK, and RANGANATHAN teaches the device of Claim 9 as applied above.
ELLENBECK further teaches the GNSS receiver generating a device positioning information according to the GNSS interface signal [Satellite receiver 2516 (i.e. GNSS receiver) may be configured to process the received satellite signals (i.e. the GNSS interface signal) to determine a geographic location of wireless device 2500 (i.e. device positioning information), par. 180].
KIM in view of SANTOSA, ELLENBECK, and RANGANATHAN does not explicitly teach the GNSS receiver transmitting the device positioning information to the first processing circuit via a universal asynchronous receiver/transmitter interface.
However, in the analogous art of network protocols, SCHUERMAN teaches a GNSS receiver transmitting positioning information to a processing circuit via a universal asynchronous receiver/transmitter interface [RF processing block 240 is operably coupled to the GPS antenna 236 for receiving satellite broadcast signals, and is operably coupled to another processing resource 244, which in turn is operably coupled to UART 249 for communication of the location data to processing resource 202, par. 82].
It would have been obvious to one of ordinary skill in the art, having the teachings of KIM, SANTOSA, ELLENBECK, RANGANATHAN, and SCHUERMAN before him before the effective filling date of the claimed invention, to incorporate transmitting information through a UART as taught by SCHUERMAN into the device as taught by KIM in view of SANTOSA, ELLENBECK, and RANGANATHAN in order to reduce minimize delay of location-based functionalities of a device [SCHUERMAN par. 63].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of SANTOSA, ELLENBECK and RANGANATHAN, and BYAGOWI as applied to Claim 14, and further in view of ZHAO et al. (US 2016/0043823 A1).
Regarding Claim 15, KIM in view of SANTOSA, ELLENBECK, RANGANATHAN, and BYAGOWI teaches the device of Claim 14 as applied above.
ELLENBECK further teaches wherein when the GNSS receiver does not generate the GNSS-based periodic synchronization signal, the first processing circuit generates the synchronizer setting signal, [If satellite receiver 2516 cannot reliably receive satellite-based synchronization signals from a satellite-based synchronization source (if receiver doesn’t receive signals, then it cannot generate the GNSS-based period synchronization signal based on the GNSS signal), sync controller 2512 (i.e. part of the first processing circuit) synchronizes with a satellite master, par. 184; Sync controller 2512 configured to provide synchronization signals to transmitter 2510 (i.e. generate a synchronizer setting signal), par. 179];
and the synchronization source selector generates the processing-circuit clock according to another synchronization source [Sync controller 2512 (which performs the synchronizer source selector) synchronizes (correct timing and frequency (i.e. a clock) are types of synchronization settings) with a satellite master, par. 184].
KIM in view of SANTOSA, ELLENBECK, RANGANATHAN, and BYAGOWI do not explicitly teach the central processing unit further performing a precision time protocol driver, wherein the precision time protocol driver generates at least one of the plurality of precision time protocol timestamps according to the precision time protocol packet.
However, in the analogous art of clock synchronization, ZHAO teaches a processing unit performing a precision time protocol driver, wherein the precision time protocol driver generates at least one of the plurality of precision time protocol timestamps according to the precision time protocol packet [data packet processing unit 12 (i.e. a processor executing instructions, i.e. a driver) is configured to receive a data packet, determine if it’s a PTP packet, and if it is a PTP packet, generate a timestamp (i.e. generates a PTP-based timestamp based on the PTP data packet), par. 42].
It would have been obvious to one of ordinary skill in the art, having the teachings of KIM, SANTOSA, ELLENBECK, RANGANATHAN, BYAGOWI, and ZHAO before him before the effective filling date of the claimed invention, to incorporate generating timestamps from PTP packets as taught by ZHAO into the device as taught by KIM in view of SANTOSA, ELLENBECK, RANGANATHAN, and BYAGOWI in order to improve time synchronization of a communication network [ZHAO par. 29].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of SANTOSA as applied to Claim 1, and further in view of ZHU (US 2023/0259465 A1).
Regarding Claim 18, KIM in view of SANTOSA teach the device of Claim 1 as applied above.
KIM in view of SANTOSA does not explicitly teach the first processing circuit transmitting the synchronizer setting signal to the clock synchronizer via a serial peripheral interface.
However, in the analogous art of synchronization, ZHU teaches a first processing circuit transmitting signals to another unit via a serial peripheral interface [CPU 102 communicates with FPGA 106 through SPI ports 110 and 112 (i.e. transmitting signals via a serial peripheral interface), FIG. 1, par. 31].
It would have been obvious to one of ordinary skill in the art, having the teachings of KIM, SANTOSA, and ZHU before him before the effective filling date of the claimed invention, to incorporate sending signals via a serial peripheral interface as taught by ZHU into the device as taught by KIM in view of SANTOSA in order to enable direct access between modules [ZHU par. 31].
CONCLUSION
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSUE L RODRIGUEZ whose telephone number is (571)272-8927. The examiner can normally be reached Monday-Friday 9am-5pm EST.
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/J.L.R./ Examiner, Art Unit 2175
/ANDREW J JUNG/ Supervisory Patent Examiner, Art Unit 2175
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