DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Color photographs and color drawings are not accepted in utility applications unless a petition filed under 37 CFR 1.84(a)(2) is granted. Any such petition must be accompanied by the appropriate fee set forth in 37 CFR 1.17(h), one set of color drawings or color photographs, as appropriate, if submitted via the USPTO patent electronic filing system or three sets of color drawings or color photographs, as appropriate, if not submitted via the via USPTO patent electronic filing system, and, unless already present, an amendment to include the following language as the first paragraph of the brief description of the drawings section of the specification:
The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawings will be provided by the Office upon request and payment of the necessary fee.
Accordingly, replacement drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to this Office action. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 15-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 15, the applicant claims that “the determining of a region in which the capping layer is to be positioned determines at least one of the location, width, and length of the capping layer”. The difference between the terms “region” and “location” has not been established making it unclear whether the positioning of the capping layer is the cause or consequence of a different property of the capping layer.
Regarding claim 16, it is unclear whether the thin film transistor is the driving device of a different device or there is a driving device included in the claimed thin film transistor.
For purposes of examination, the claim is interpreted by the Examiner as follows:
Claim 16: “The manufacturing method of a thin film transistor according to claim 11, wherein thin film transistor acts as a driving device”
Regarding claim 17, it is unclear what the applicant means by: “a thin film transistor, which is a circuit for displays comprising at least one thin film transistor” as well as what the applicant is referring to when stating:“…wherein the thin film transistor is the thin film transistor of claim 1”.
For purposes of examination, the claim is interpreted by the Examiner as follows:
Claim 17: “A circuit for displays comprising at least one thin film transistor for a switching or driving purpose, wherein the thin film transistor is the thin film transistor of claim 1”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 9-11, and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (US 20170104018 A1) hereinafter referred to as "Yamazaki".
Regarding claim 1, Yamazaki teaches a thin film transistor, comprising; a substrate (FIG. 5B, element 102; ¶: [0238]); a gate electrode (FIG. 5B, element 106; ¶: [0238]) formed on the substrate; an insulating layer (FIG. 5B, element 104; ¶: [0238]) formed on the substrate to cover the gate electrode; a semiconductor (FIG. 5B, element 108; ¶: [0238]) formed on the insulating layer to form a channel; a source electrode (FIG. 5B, element 108s; ¶: [0239]) and a drain electrode (FIG. 5B, element 108d; ¶: [0239]) formed spaced apart from each other on the semiconductor layer; and a capping layer (FIG. 5B, element 116; ¶: [0238]) formed in at least one region between the source electrode and the drain electrode on the semiconductor layer to control the carrier concentration of the channel.
Regarding claim 2, Yamazaki teaches the thin film transistor according to claim 1. Yamazaki further teaches the capping layer (FIG. 5B, element 116; ¶: [0184]) comprising at least one selected from the group consisting of aluminum oxide (Al203), silicon oxide (SiO2), silicon nitride (SiNX) and inorganic insulating materials, and the carrier concentration of the region in which the capping layer is formed (FIG. 5B, element 116; ¶: [0221]) being higher than the carrier concentration of a region in which the capping layer is not formed (FIG. 5B, element 110; ¶: [0218]).
Regarding claim 9, Yamazaki teaches the thin film transistor according to claim 1. Yamazaki further teaches the semiconductor layer (FIG. 5B, element 108; ¶: [0181, 0307]) positioned on the bottom of the region in which the capping layer is formed performing the role of an N-type doping region.
Regarding claim 10, Yamazaki teaches the thin film transistor according to claim 1. Yamazaki further teaches at least a part of the capping layer (FIG. 5B, element 116; ¶: [0115]) being in contact with the source electrode (FIG. 5B, element 108s; ¶: [0115]) and the drain electrode (FIG. 5B, element 108d; ¶: [0115]).
Regarding claim 11, Yamazaki teaches a manufacturing method of a thin film transistor, comprising; preparing a substrate (FIG. 5B, element 102; ¶: [0238]); forming a gate electrode (FIG. 5B, element 106; ¶: [0238]) on the substrate; forming an insulating layer (FIG. 5B, element 104; ¶: [0238]) on the substrate to cover the gate electrode; forming a semiconductor layer (FIG. 5B, element 108; ¶: [0238]) on the insulating layer; forming a source electrode (FIG. 5B, element 108s; ¶: [0239]) and a drain electrode (FIG. 5B, element 108d; ¶: [0239]) spaced apart on the semiconductor layer; and forming a capping layer (FIG. 5B, element 116; ¶: [0238]) in at least a part of a region between the source electrode and drain electrode on the semiconductor layer.
Regarding claim 16, Yamazaki teaches the thin film transistor according to claim 11. Yamazaki further teaches the driving device of the thin film transistor is the thin film transistor (FIG. 5B, element 110A; ¶: [0244]) of claim 1.
Regarding claim 17, Yamazaki teaches a circuit for displays comprising at least one thin film transistor (FIG. 5B, element 100A; ¶: [0254]) for a switching or driving purpose, wherein the thin film transistor is the thin film transistor of claim 1 .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Lin et al. (CN 107749422 A) hereinafter referred to as "Lin".
Regarding claim 3, Yamazaki teaches the thin film transistor according to claim 1. Yamazaki does not teach the thickness of the capping layer being 2nm to 10nm.
Lin teaches the thickness of the capping layer (FIG. 6, element 05; ¶: [0010, 0029]) being 2nm to 10nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a capping layer of this specific thickness in order to obtain a desired carrier concentration (¶: [0023])
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Hirano et al. (US 20180026103 A1) hereinafter referred to as "Hirano"
Regarding claim 7, Yamazaki teaches the thin film transistor according to claim 1. Yamazaki does not teach the length of the capping layer being 95% or less of the length of the channel..
Hirano teaches the length of the capping layer (FIG. 3, element 5; ¶: [0123]) being 95% or less of the length of the channel.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the capping layer in this fashion in order to suppress a shift of the threshold voltage in the negative direction without increasing the size of the transistor (¶: [0125]).
Regarding claim 8, Yamazaki teaches the thin film transistor according to claim 1. Yamazaki does not teach the length direction formation position of the capping layer satisfying the value of [Y= k(LCH - LCAP), (0 ≤ k ≤ 1)] in relation to the channel.
Hirano teaches the length direction formation position of the capping layer (FIG. 3, element 5; ¶: [0123]) satisfying the value of [Y= k(LCH - LCAP), (0 ≤ k ≤ 1)] in relation to the channel.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the capping layer in this fashion in order to suppress a shift of the threshold voltage in the negative direction without increasing the size of the transistor (¶: [0125]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Yamazaki et al. (US 20130140554 A1) hereinafter referred to as "Yamazaki 554"
Regarding claim 12, Yamazaki teaches the thin film transistor according to claim 11. Yamazaki does not explicitly teach the forming of an insulating layer comprising depositing an insulating material with a thickness of 100 nm to 200 nm on the substrate.
Yamazaki 554 teaches the forming of an insulating layer comprising depositing an insulating material (FIG. 402, element 402; ¶: [0142]) with a thickness of 200 nm on the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have an increased thickness of the gate insulating layer in order to increase the amount of oxygen released thus, reducing oxygen vacancies ¶: [0207]).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki.
Regarding claim 13, Yamazaki teaches the thin film transistor according to claim 11. Yamazaki does not explicitly teach forming a capping layer comprising forming the capping layer through a sputtering method at a room temperature.
However, Yamazaki teaches another protective film being formed by a sputtering method as well as the fact that films included in the transistor can be formed using the sputtering method as a typical example of a film formation method (¶: [0389]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the sputtering method at room temperature to form the capping layer and expect a predictable result.
Regarding claim 14, Yamazaki teaches the thin film transistor according to claim 11. Yamazaki does not explicitly teach determining a region in which the capping layer is to be positioned in consideration of the SS, threshold voltage and mobility values of the thin film transistor, before the forming the capping layer.
However, Yamazaki teaches the formation and use of other similar functioning films in consideration of reducing the change in threshold voltage (¶: [0115, 0182]) and having a higher mobility value (¶: [0009, 0469]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have positioned the capping layer in an effort to yield better results for SS, threshold voltage, and mobility.
Allowable Subject Matter
Claims 4-6 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4 (and thus further dependent claims 5 and 6) objected to for being dependent on rejected claim 1
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the art teaches certain elements of the claimed invention including but not limited to a thin film transistor comprising a gate electrode, a gate insulating layer, a semiconductor layer, a source and drain electrode, and a capping layer in ascending order. However, the prior art when taken alone or in combination cannot be seen as teaching specific elements of the invention regarding: “the width and the length of the capping layer are smaller than the width and length of the channel, respectively”.
Regarding claim 5, the art teaches certain elements of the claimed invention including but not limited to a thin film transistor comprising a gate electrode, a gate insulating layer, a semiconductor layer, a source and drain electrode, and a capping layer in ascending order. However, the prior art when taken alone or in combination cannot be seen as teaching specific elements of the invention regarding: “the width of the capping layer is 50% or less of the width of the channel”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/I.H./Examiner, Art Unit 2899
/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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