DETAILED ACTION
This Office action is in response to the application filed on 13 September 2024 and Applicant’s response to the requirement for election of species filed on 10 June 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Species C in the reply filed on 10 June 2026 is acknowledged. Claims 3, 6 and 9-11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5 and 12-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li (US 2020/0321890).
In re claim 1, Li discloses a control circuit for a switching power supply that contains a switching transistor (see Fig. 2: control circuit 20; half-bridge(s) 21 includes switching transistors according to Fig. 3 and [0029]), the control circuit comprising:
a first switching detection pin (Fig. 6: pin receiving signal Vbody) to be connected to a first node in the switching power supply (Vbody pin is connected to electrodes of one or more switching transistors: [0042]);
a second switching detection pin (Fig. 6: pin receiving signal GH/GL) to be connected to a second node in the switching power supply (GH/GL pin connects to gates of one or more switching transistors: see Fig. 3, [0057]);
a time-to-digital converter (Fig. 6: comparator 60 and counter 61 and Fig. 15: counter 154) structured to generate a digital value (tdel; as shown in more detail in Fig. 15, tdel is a 10-bit digital value output from the counter) that represents a time difference between a notable edge of a first switching voltage that appears at the first switching detection pin and a notable edge of a second switching voltage that appears at the second switching detection pin (see [0057]-[0058] and, e.g., Fig. 7B); and
a software-controllable digital signal processor (Fig. 2: 22; it is understood to be a digital controller because it receives and processes the digital value tdel from the counter; see Figs. 6 and 15; see also [0007] teaching the use of software in the control of the power supply) structured to generate a control pulse that instructs on/off of the switching transistor, with reference to at least the digital value ([0037]).
In re claims 12 and 15, Li discloses a control circuit and method for controlling a switching power supply that contains a switching transistor (see Fig. 2: control circuit 20; half-bridge(s) 21 includes switching transistors according to Fig. 3 and [0029]), the control circuit and method comprising:
a switching detection pin to be connected to a node at which voltage fluctuates in response to on/off of the switching transistor in the switching power supply (Fig. 6: pin receiving Vbody, which is a voltage across one or more switching transistors and thus fluctuates according to ON/OFF of the transistors; see [0042]);
a time-to-digital converter (Fig. 6: comparator 60 and counter 61 and Fig. 15: counter 154) structured to receive a control pulse that instructs on/off of the switching transistor (GH/GL are the gate signals for the transistors: see Fig. 3 and [0057]), and voltage at the switching detection pin, and to generate a digital signal (tdel; as shown in more detail in Fig. 15, tdel is a 10-bit digital value output from the counter) that represents a time difference between the control pulse and the voltage at the switching detection pin (see [0057]-[0058] and, e.g., Fig. 7B); and
a digital signal processor (Fig. 2: 22; it is understood to be a digital controller because it receives and processes the digital value tdel from the counter; see Figs. 6 and 15; see also [0007] teaching the use of software in the control of the power supply) structured to generate the control pulse, in response to at least the digital signal ([0037]).
In re claim 2, Li discloses a multiplexer arranged in a preceding stage of the time-to-digital converter, the multiplexer being structured to output, by swapping, a signal at the first switching detection pin and a signal at the second switching detection pin (Fig. 15 and [0075], [0077], [0103]: MUXes 151A/B and 152A/B).
In re claim 4, Li discloses wherein the digital signal processor is structured to conduct calibration with reference to the digital value ([0037]: the control circuit compensates a dead time between the switching transistors of the half-bridge, which is considered a calibration process).
In re claim 5, Li discloses wherein the digital signal processor is structured to reflect the digital value, on a control parameter of a main feedback loop (see Fig. 15 and [0037]: the delay measurements are reflected onto a current feedback parameter in that they are used to determine the polarity of said current).
In re claims 13-14, Li discloses the switching power supply containing the control circuit (see Figs. 2, 3, 6, 15).
Allowable Subject Matter
Claims 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 7, the closest prior art in Li discloses the invention according to claim 1 as explained above, but does not further disclose a transformer; a bridge circuit connected to a primary winding of the transformer; and a synchronous rectifier circuit connected to a secondary winding of the transformer; the first switching detection pin is connected to receive the control pulse supplied to a switching transistor that constitutes the synchronous rectifier circuit, and the second switching detection pin is connected to receive voltage that appears in the secondary winding of the transformer.
However, other prior art on record, such as Manabe et al. (US 2018/0329394) demonstrate the use of similar delay measurement circuits in a power supply having a transformer and bridge circuit and synchronous rectifier (see Figs. 3A, 4, 6). However, nonetheless the prior art on record, including Manabe, does not disclose the first and second switching detection pins being connected receive the specific signals as required by claim 7: the control pulse supplied to a switching transistor that constitutes the synchronous rectifier circuit, and voltage that appears in the secondary winding of the transformer, respectively.
Claim 8 depends from claim 7 and thus would be allowable for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Patent 7,057,910 discloses a Semiconductor Device And Control Method with circuits for measuring dead time between switching events of a switching power supply.
US 2013/0193938 discloses DEAD-TIME COMPENSATION IN A POWER SUPPLY SYSTEM including a digital delay system configured to measure the activation dead-time and to add the measured activation dead-time to the activation of the high-side switch.
US 2021/0203239 is the English-language equivalent document of a Japanese patent document cited by Applicant on an Information Disclosure Statement.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
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