DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for the examination.
Double Patenting
2. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
3. A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
4. The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
5. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
6. Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent 12118384 B2 . Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-7 of US Patent US 12118384 B2 contain(s) every element of claim(s) 1-20 of the instant application and thus anticipate the claim(s) of the instant application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 5, 6, 7, 14, 15, 16, 17, 19 are rejected under 35 U.S.C. 103 as being unpatentable over McCrory( US 6513057 B1) in view of McDonald( US 20030088608 A1) and further in view of DORSEY( US 20180349191 A1).
As to claim 1, McCrory teaches a plurality of processors, each respective processor of the plurality of processors with a collection of clusters( one or more processors from a first processor family are packaged on a single printed circuit card along with necessary bus interface converters for coupling the card to a common bus. Additional circuit cards include processors from other families of processors, col 2, ln 39-45), and a kernel scheduler to: associate each respective processor(This involves scheduling the kernel request on a processor which is native to the HSMP OS, col 3, ln 3-6/ The HSMP OS schedules kernel services in a ready queue native to the instruction stream of the kernel service. Upon completion of the kernel service, control is returned to the originating processor, col 8, ln 15-20);
, wherein each cluster of the collection of clusters represents a respective different subset of the plurality of processors, and the respective processor is a member of each cluster of the collection of clusters( Heterogenous SMP (HSMP) system 310 supports a plurality of processors and a plurality of processor families. Each processor board 312-316 includes one or more individual processors belonging to the same family of processors. For example, processor family 312 may be an Intel family of processors, where processor 318 is an Intel Pentium 200 MHz and processor 320 is an Intel Pentium 166 MHz processor with both processors running at the same external bus speed. Similarly, processor family 314 may be a DEC family of processors, col 5, ln 55-67 to col 6, ln 1-10/ Fig.3);
and for each corresponding cluster of the collection of clusters, maintain a data structure associated with a ready queue of the kernel scheduler( The HSMP OS maintains a separate ready queue for each family of processors for scheduling the execution of process threads on the various system processors, col 6, ln 60-66/ the operating system maintains a ready queue 212 for scheduling execution of those process threads when one or more of processors 112-116 become available. In the example of FIG. 2, "ready" threads include threads 214, 218 and 226. Ready threads 214, 218 and 226 are placed in ready queue 212 to wait their turn for an available processor. Ready queue 212 is often implemented as a linked list, col 4, ln 60-67/ The HSMP OS schedules kernel services in a ready queue native to the instruction stream of the kernel service. Upon completion of the kernel service, control is returned to the originating processor or family of processors, col 8, ln 15-30).
McDonald teaches the data structure comprising elements representing thread priorities, wherein an element of the data structure is associated with an ordered list of threads in the ready queue( Dispatcher 304 selects a thread for dispatching from thread ready queue structure 305. Ready queue structure 305 is illustrated in greater detail in FIG. 4. As shown in FIG. 4, ready queue structure comprises multiple lists 401-403 of control blocks 410-412, of which three lists are shown for illustrative purposes in FIG. 4, it being understood that the actual number may vary. Each control block list 401-403 is arranged in a FIFO order. Control blocks 410-412 of a given list represent threads associated with a designated priority, which are ready and waiting to execute. I.e., control block lists 401-403 contain threads in the ready state, i.e. those that are ready to execute, and are waiting only for an available processor. When a thread enters the ready state, its control block is placed at the end of the list having the priority associated with the thread, para[0051]/ Each control block 410-412 contains certain state information with respect to an active thread, some of which is used by dispatcher 304 to select a thread for dispatch. FIG. 5 illustrates certain thread-specific information from a typical control block 410 which is used by the dispatcher. As shown in FIG. 5, the control block includes priority 501, affinity mask 502, ideal node mask 503, ideal processor 504, last executed processor 505, and queue time 506. Priority field 501 contains the designated numerical priority of the thread, para[0053], ln 1-10/ Fig. 3-5/ The thread select function is called to select a thread for a target CPU (designated P), which is generally the CPU which just became available, as explained above. The thread select function traverses the various control block lists 401-403 in ready queue 305 from highest priority to lowest priority until a suitable thread is found. As shown in FIG. 7, the thread select function first selects a list to traverse (step 701). Initially, the control block list selected is the highest priority list, and with each subsequent iteration of the main loop, step 701 selects the list having the highest priority of those lists which have not yet been examined. The variables ideal_node_hit and ideal_CPU_hit are initialized to null values (step 702). Additionally, the dispatcher determines a maximum waiting time (wmax) for threads in the selected control block list (also step 702). The maximum waiting time varies for each list, it being less for higher priority lists and greater for lower priority lists, para[0065]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of McCrory with McDonald to incorporate the feature of the data structure comprising elements representing thread priorities, wherein an element of the data structure is associated with an ordered list of threads in the ready queue because this avoids starvation or other problems which may arise from too rigidly constraining the thread dispatching choice.
Dorsey teaches respective ready queues for corresponding clusters of the collection of clusters, the ready queues comprising a first ready queue including a first data structure associated with a first cluster of the collection of clusters, and a second ready queue including a second data structure associated with a second cluster of the collection of clusters, wherein threads ready for execution on a first processor of the plurality of processors are represented in the first data structure of the first ready queue, and in the second data structure of the second ready queue; and schedule a thread for execution on the first processor by accessing data structures of a plurality of ready queues including the first data structure of the first ready queue and the second data structure of the second ready queue( processor complex scheduler 210 can include a thread queue for each core type of processor complex cluster of cores 221 and 222, e.g. efficiency thread queue 215 (E-queue) and performance thread queue 220 (P-queue). Each queue type can have a plurality of queue entries, e.g. E-queue 215 can have E-threads 215-1, 215-2, . . . , 215-n pending in the E-queue 215, and P-queue 220 can have P-threads 220-1, 220-2, . . . , 220-n pending in the P-queue 220. Processor complex scheduler 210, E-queue 215, and P-queue 220 can communicate with processor complex 111 the components of processor complex 111. Processor complex scheduler 210 can further contain scheduling logic 725 to manage queues 215, 220, and 726, and implement DIPI using interrupt controller 755 and timers 760 and 765. In an embodiment, processor complex scheduler 210 can also include a global run queue 726 that enqueues threads that are runnable. In an embodiment, one or more run queue(s) 726[first/second data structures] can comprise an E-core run queue 215 and a performance core run queue 220, para[0133]/ n operation 1310, it can be determined whether the processor complex scheduler detects that (1) a P-eligible thread is enqueued and runnable, (2) no P-cores are idle, and (3) at least one E-core is idle. If no P-eligible threads are enqueued on the P-queue, or there are idle P-cores, or there are no idle E-cores, then method 1300 ends, otherwise method 1300 continues at operation 1315. In operation 1315, processor complex scheduler obtains a runnable P-eligible thread from the P-queue and enqueues the runnable P-eligible thread for running on an E-core, para[0083] to para[0084]/ In operation 920, processor complex scheduler 705 can enqueue one or more threads for execution. Processor complex scheduler 705 can have a thread queue for each core type, e.g. efficiency cores (E-cores) and performance cores (P-cores). By default, the processor complex scheduler can initially schedule threads of all thread groups for execution on an E-core queue for execution at a default DVFS state, para[0146]/ In operation 1520, the runnable P-eligible thread that is scheduled on the E-core scheduling queue is enqueued on the P-core scheduling queue, and the P-eligible thread is executed on a P-core, para[0149]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this schedules threads on an asymmetric multiprocessing system having multiple core types.
As to claim 4, DcDonald teaches wherein the kernel scheduler is to: schedule the thread for execution on the first processor by traversing the data structures of the plurality of ready queues a select the thread from threads represented in the data structures of the plurality of ready queues. ( para[0065], ln 6-15) for the same reason as to claim 1 above .
As to claim 5, DcDonald teaches the elements of each data structure are arranged in an order of thread priorities, and wherein the kernel scheduler is to identify, according to the order of thread priorities of the elements in each data structure, the thread in the ready queue to schedule for execution( para[0063], ln 3-9/ para[0063]/ para[0066], ln 1-20) for the same reason as to claim 1 above.
As to claim 6, DcDonald teaches each thread in the ordered list of threads is associated with a timestamp corresponding to a time the thread was placed in the ready queue and wherein the kernel scheduler is to identify the thread in the ready queue to schedule for execution further based on the timestamp(para[0053], ln 1-28) for the same reason as to claim 1 above.
As to claim 7, DcDonald teaches the threads in the ordered list of threads are arranged in order according to when the threads were placed in the ready queue( para[0051], ln 1-15) for the same reason as to claim 2 above.
As to claim 14, It is rejected for the same reason as to claim 1 above. In additional, McCrory teaches a scheduling executive, a given thread for execution based on selecting the given thread from the ready queues of the clusters of the collection of clusters( When a CPU becomes available to execute a thread for these or any other reasons, a dispatcher within the operating system typically determines which of multiple waiting threads will be dispatched to the available CPU for execution, para[0012], ln 15-20/ offers the user the capability to define additional run queues for arbitrary groups of CPUs. When a process is initiated, it is assigned to one of the run queues, and all threads spawned by the process are placed on that run queue when awaiting execution. The operating system thereafter preferentially dispatches threads of the process to the CPU or CPUs of its assigned run queue, and at a somewhat lower preference level, to CPUs within the same system node as the CPU (or CPUs) of the assigned run queue, para[0015, ln 3-15/ Dispatcher 304 selects a thread for dispatching from thread ready queue structure 305. Ready queue structure 305 is illustrated in greater detail in FIG. 4. As shown in FIG. 4, ready queue structure comprises multiple lists 401-403 of control blocks 410-412, of which three lists are shown for illustrative purposes in FIG. 4, it being understood that the actual number may vary. Each control block list 401-403 is arranged in a FIFO order. Control blocks 410-412 of a given list represent threads associated with a designated priority, which are ready and waiting to execute, para[0051], ln 1-11).
As to claims 15, 16, 17, they are rejected for the same reasons as to claims 2-3, 5 above.
As to claim 19, it is rejected for the same reason as to claim 15 above. In additional, Dorsey teaches non-transitory machine-readable storage medium( A non-transitory machine-readable medium , claim 12, ln 1-2) and McDonald teaches scheduling executive in an operating system (OS) kernel( Immediately above hardware is low-level operating system level 302, which in some operating systems is called a "kernel". …… Among the functions provided by low-level operating system 302 are paging function 303 and dispatching function 304. Pager 303 is called when an executing thread attempts to access data which is not currently in the system's distributed main memory, i.e., the data is not in any of the local memories 210 in the various nodes. …Dispatcher 304 dispatches threads waiting to be executed to processors for execution, as explained in greater detail herein. Dispatch ready queue structure 305 contains threads waiting for dispatch by dispatcher 304, para[0043]) for the same reason as to claim 1 above.
Claims 2, 3 are rejected under 35 U.S.C. 103 as being unpatentable over McCrory( US 6513057 B1) in view of McDonald( US 20030088608 A1) in view of DORSEY( US 20180349191 A1) and further in view of Weber( US 20160044092 A1).
As to claim 2, Weber teaches a first processor is associated with a first collection of clusters, the first collection of clusters comprising a first cluster that includes all processors of the plurality of processors, a second cluster that includes only the first processor, and a third cluster that includes processors having a first characteristic( each of the one or more storage devices 100 of the data storage cluster 1100 incorporates one or more of a processor component 150, para[0042], ln 1-3/ Multiple threads may be executed within each of the clusters 1100 and 1300 to achieve parallelism in the performance of data transfers and computations involving the data set 130 regardless of whether each of the clusters 1100 and 1300 are made up of a single computing device or multiple computing devices, para[0037], ln 10-16/ Although each of the processor components 550, 650 and 750 may include any of a variety of types of processor, it is envisioned that the processor component 650 of the graphics controller 600 of the embodiment of the computing device 500 of FIG. 2 may be somewhat specialized and/or optimized to perform tasks related to graphics, including graphics rendering, para[0094], ln 1-7).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the feature of a first processor is associated with a first collection of clusters, the first collection of clusters comprising a first cluster that includes all processors of the plurality of processors, a second cluster that includes only the first processor, and a third cluster that includes processors having a first characteristic because this allows large data sets begets the challenges of where to store and process the data contained within large data sets in a manner that is efficient.
As to claim 3, Weber teaches a second processor is associated with a second collection of clusters, the second collection of clusters comprising the first cluster that includes all processors of the plurality of processors, a fourth cluster that includes only the second processor, and a fifth cluster that includes processors having a second characteristic different from the first characteristic(para[0094], ln 1-7) for the same reason as to claim 2 above.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over McCrory( US 6513057 B1) in view of McDonald( US 20030088608 A1)in view of DORSEY( US 20180349191 A1) and further in view of Thomson( US 20110225590 A1).
As to claim 8, Thomson teaches the kernel scheduler is to: in response to a preemption of a thread scheduled for execution from the ordered list of threads, assign a specified timestamp to the preempted thread to maintain the preempted thread at a beginning of the ordered list of threads( Still referring to FIG. 5, the first bucket 504 may include a first thread 520 and a second thread 522. The first thread 520 may include a specified priority value 524, a quantized priority value 526, and a quantum value 528. A specified priority value 524 is a priority value specified by the thread. The specified priority value is used to give priority to the execution of threads. For example, a higher priority value may cause a particular thread to be executed before a thread having a lower priority value. A quantized priority value 526 may be a priority value determined at least partially based on the run information for the thread. The quantum value 528 may be a time-slice that a thread may be allowed to run before being preempted by another thread in the same bucket. As shown, the second thread 522 may include a specified priority value 530, a quantized priority value 532, and a quantum value 534, para[0040]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the feature of teaches the kernel scheduler is to: in response to a preemption of a thread scheduled for execution from the ordered list of threads, assign a specified timestamp to the preempted thread to maintain the preempted thread at a beginning of the ordered list of threads because this provides an improved system and method of executing a plurality of threads on one or more processors.
Claims 9, 18 are rejected under 35 U.S.C. 103 as being unpatentable over McCrory( US 6513057 B1) in view of McDonald( US 20030088608 A1) in view of DORSEY( US 20180349191 A1) and further in view of Kra( US 20070124568 A1).
As to claim 9, Kra teaches an element of the first data structure has a first thread priority and is associated with a first ordered list of threads, and an element of the second data structure also has the first thread priority and is associated with a second ordered list of threads, and wherein the kernel scheduler is to: use timestamps associated with one or more threads in the first ordered list of threads and one or more threads in the second ordered list of threads to decide which thread from the first ordered list of threads or the second ordered list of threads to schedule for execution on the first processor ( threads are selected according to priority, and among threads of equal priority, the thread which has been in the ready queue longest is selected first. However, other considerations could be used. For example, in some systems such as non-uniform memory architecture (NUMA) systems or systems which are logically partitioned, separate queues might be maintained for different processors or groups of processors within the system and/or threads dispatched based on some form of association with a processor or group of processors, para[0074], ln 4-16).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this provides improved techniques for processor operation and design which will avoid or mitigate some of the undesirable side effects of servicing such high-priority threads.
As to claim 18, it is rejected for the same reason as to claim 9 above.
Claims 10 ,11, 12 are rejected under 35 U.S.C. 103 as being unpatentable over McCrory( US 6513057 B1) in view of McDonald( US 20030088608 A1) in view of DORSEY( US 20180349191 A1) and further in view of Leonard(US 20040226015 A1).
As to claim 10, McCrory teaches data structures for corresponding clusters of the collection of clusters are associated with respective ready queues of the kernel scheduler(In the example of FIG. 2, "ready" threads include threads 214, 218 and 226. Ready threads 214, 218 and 226 are placed in ready queue 212 to wait their turn for an available processor. Ready queue 212 is often implemented as a linked list, col 4, ln 62-67/ Ready threads are those threads whose associated code is ready to execute but are not executing due to lack of an available processor. Ready queues 510, 512 and 514 track these ready threads for processing on processor families FAM1, FAM2 and FAM3, respectively. For example, ready queue 510 tracks threads for processors P1-FAM1318 and P1-FAM1320, col 7, ln 60-67 ) .
Leonard teaches the kernel scheduler is to schedule the thread for execution on the first processor by further accessing a third data structure of a third ready queue, the third data structure including an element representing threads ready for execution on the first processor( These processor sets 201 are shared among zones 130, 140 for executing processes , para[0043], ln 6-10/The kernel 601 manages a process execution queue for each processor set. A process queue contains processes that are waiting with requests for a set of work for a particular processor set. Each process has a priority that the kernel 601 uses to decide when each work request will run on the processor set. The process with the highest priority relative to the other processes in the queue runs its set of work on the processor set next. When a process releases a processor set, the kernel 601 begins a re-evaluation of its process queue for that processor set to adjust the process' priority in the queue. Processes that have used less of their allotted total will end up having a higher priority in the queue and those that have used a large amount of their allotted total will have a lower priority in the queue, para[0059]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the feature of data structures for corresponding clusters of the collection of clusters because this provides an improved system and method of data structures for corresponding clusters of the collection of clusters because this allows certain computing resources to be allocated to certain entities and it is possible to associate certain processors with certain groups of applications.
As to claim 11, McDonald teaches each respective cluster of the collection of clusters is further associated with a mask indicating which elements of the data structure for the respective cluster are associated with non-empty ordered lists of threads( para[0053], ln 1-2) for the same reason as to claim 1 above.
As to claim 12, McDonald teaches a non-empty ordered list of threads includes one or more threads( para[0015], ln 1-30) for the same reason as to claim 1 above.
Claims 13, 19 are rejected under 35 U.S.C. 103 as being unpatentable over McCrory( US 6513057 B1) in view of McDonald( US 20030088608 A1) in view of DORSEY( US 20180349191 A1) in view of Leonard(US 20040226015 A1) and further in view of Miller( US 20040068730 A1).
As to claim 13, Miller teaches the kernel scheduler is to use the mask to search the respective cluster for a thread to schedule, wherein the mask is to produce an index referring to an element of the respective cluster, the element referred to by the index associated with a non-empty ordered list of threads(the threads 260.sub.1 to 260.sub.K are program threads created in user applications such as the application 214. The threads 260.sub.1 to 260.sub.K may also include system threads or kernel threads that are created and run on behalf of the OS 240 or the virtual machine 230. Each of the threads 210.sub.1 to 260.sub.K maintains its own local variables and local resources such as program counter and stack, para[0041], ln 1-12/ the selection of the clusters of processors for affinitization depends on the number of active threads and the count threshold. The count threshold, however, is not used as the maximum number of threads affinitized to a cluster of processors. It is used to guide the thread distribution dynamically. The number of threads affinitized to each cluster of processors may not be limited by the count threshold. It may exceed the count threshold. The thread distribution is, therefore, more adaptive to the dynamic behavior of the overall system. In this technique, an index is computed to point to the cluster of processors to which the thread will be affinitized to. This index is determined by taking a ratio between the number of active threads and the count threshold and then applying the modulo-N operation on this ratio to ensure that the index is within a range of 1 to N, where N is the total number of cluster configurations for the thread affinity, para[0043]/ he index is determined by first computing a ratio as a function of the first thread count t.sub.C and the count threshold t.sub.x and then converting the ratio into the index such that the index is within a range of 1 and N, para[0045]/ Upon START, the process 370 computes the index as a function of the first thread count, the count threshold, and the total number of clusters of processors available for affinitization (Block 810). For example, index=[(t.sub.C-1)/t.sub.x] % N+1 as shown in equation (2), where % is a modulo function, t.sub.C is the first thread count, t.sub.x is the count threshold, and N is the number of clusters of processors. The modulo function ensures that the index value is within a range from 1 to N. Alternatively, the index may be obtained from a look-up table where the affinity has been determined in advance, para[0072]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the feature of the kernel scheduler is to use the mask to search the respective cluster for a thread to schedule, wherein the mask is to produce an index referring to an element of the respective cluster, the element referred to by the index associated with a non-empty ordered list of thread because this provides the flexibility in managing thread affinity and control of affinity granularity.
As to claim 20, it is rejected for the same reason as to claim 13. In additional, McDonald teaches each respective cluster of the collection of clusters is further associated with a mask indicating which elements of the data structure for the respective cluster are associated with non-empty ordered lists of threads( para[0053], ln 1-29) for the same reason as to claim 1 above.
Conclusion
US 20070124568 A1 teaches thread remains on wait queue 505 until some event on which it was waiting occurs. At that point, the thread is transferred to ready queue 504. Dispatcher 503 selects threads for dispatching from ready queue 504. Typically, threads are selected according to priority, and among threads of equal priority, the thread which has been in the ready queue longest is selected first. However, other considerations could be used. For example, in some systems such as non-uniform memory architecture (NUMA) systems or systems which are logically partitioned, separate queues might be maintained for different processors or groups of processors within the.
US 20180349191 A1 teaches processor complex scheduler 210 can include a thread queue manager 211, thread group performance data manager 212, thread group recommendation manager 213, and a plurality of thread queues for each of a plurality of processor core types. In an example processor complex 111, processor complex scheduler 210 can have an E-core thread queue 215 and a P-core thread queue 220.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LECHI TRUONG whose telephone number is (571)272-3767. The examiner can normally be reached 10-8 PM.
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/LECHI TRUONG/Primary Examiner, Art Unit 2194
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