Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/19/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1 & 15 are objected to because of the following informalities:
Claims 1 & 15 recite “a second MOSFET having a source terminal coupled to the source terminal of the first MOSFET, a second gate terminal, and a second drain terminal.” The phrases “a second gate terminal” and “a second drain terminal” are understood to refer to the gate terminal and drain terminal of the second MOSFET. However, because claim 1 already recites “a second MOSFET,” the claim would be clearer if amended to recite “a gate terminal” and “a drain terminal” for the second MOSFET. In addition, the source terminal of the second MOSFET is “coupled to the source terminal of the first MOSFET,” while also reciting that “a shunt resistor” is “coupled between the source terminals of the first and second MOSFETs.” Applicant is requested to clarify whether the source terminal of the second MOSFET is coupled to the source terminal of the first MOSFET through the shunt resistor. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, claim 8 depends from claim 6 and recites “wherein a resistance of the first gate resistor is greater than a resistance of the second gate resistor.” However, claim 6 does not previously recite “a first gate resistor” or “a second gate resistor.” Therefore, there is insufficient antecedent basis for “the first gate resistor” and “the second gate resistor,” rendering the scope of claim 8 unclear.
Regarding claim 9, claim 9 depends from claim 6 and recites “a first gate capacitor having a first terminal coupled to a common voltage, and a second terminal coupled between the gate terminal of the first MOSFET and the first gate resistor.” However, claim 6 does not previously recite “a first gate resistor.” Therefore, there is insufficient antecedent basis for “the first gate resistor,” rendering the scope of claim 9 unclear.
Applicant may overcome this rejection by amending claims 8 and 9 to depend from claim 7, or by otherwise amending the claims to provide proper antecedent basis for “the first gate resistor” and “the second gate resistor.”
Allowable Subject Matter
Claims 1-19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 1-7 and 10-19 would be allowable if rewritten or amended to overcome the objections and if claims 8 and 9 are amended to overcome the rejection under 35 U.S.C. 112(b), provided that no prior art rejection or other statutory rejection is maintained.
The following is an examiner’s statement of reasons for allowance. The examiner has considered the prior art of record, including the references cited in the Information Disclosure Statement filed 12/19/2024, including at least Ahlers et al. (U.S. 2024/0007084 A1) and Shiomi (U.S. 2021/0281185 A1) from the results of further searching through EP2P.
Ahlers et al. disclose a dual gate metal oxide semiconductor field effect transistor (MOSFET) device formed in a semiconductor material, as well as circuits and techniques for using the dual gate MOSFET device. In some examples, Ahlers et al. disclose that the dual gate MOSFET device may comprise a first MOSFET formed in the semiconductor material and a second MOSFET formed in the semiconductor material, where the first MOSFET and the second MOSFET are arranged in parallel in the semiconductor material, include a common drain node and a common source node, and define different transfer characteristics. Thus, Ahlers et al. relate generally to MOSFET structures and control techniques involving multiple MOSFET portions or transistor regions having different operating characteristics.
Shiomi discloses reducing transient current in a rectifier circuit. Shiomi discloses a rectifier circuit in which a first rectifier is provided between a first terminal and a second terminal. When a switch element is turned ON, a primary winding current flows from a power supply to a primary winding of a transformer. When the switch element is turned OFF, a second rectifier current flows from a secondary winding of the transformer to a second rectifier. During a period in which the second rectifier current is flowing, a reverse voltage is applied between the first terminal and the second terminal. Thus, Shiomi is directed to rectifier operation and transient current reduction in a power conversion circuit.
However, the prior art of record, including Ahlers et al. and Shiomi, does not teach or reasonably suggest the claimed current sensing architecture recited in independent claims 1 and 15. In particular, the prior art does not teach or reasonably suggest an apparatus for sensing current in a back-to-back MOSFET configuration in which a shunt resistor is coupled between the source terminals of first and second MOSFETs, the gate driver circuit includes a return terminal coupled to the source terminal of the first MOSFET, and gate drive return current from the gate terminal of the second MOSFET flows through the shunt resistor to the return terminal of the gate driver circuit.
The claimed configuration is not merely a conventional MOSFET switching arrangement or a conventional rectifier arrangement. Rather, the claimed configuration uses the placement of the shunt resistor and the gate driver return path together so that the source terminal of the second MOSFET is not directly tied to the gate driver return terminal. As a result, current associated with the second MOSFET side, including the gate drive return current from the gate terminal of the second MOSFET, flows through the shunt resistor to the return terminal of the gate driver circuit. This arrangement allows current through the shunt resistor to be sensed while maintaining a back-to-back MOSFET configuration and avoiding a return path that would bypass or short the shunt resistor.
Ahlers et al. do not teach or reasonably suggest this arrangement because Ahlers et al. are directed to a dual gate MOSFET device having first and second MOSFET portions arranged in parallel with a common drain node and a common source node. Ahlers et al. do not disclose a back-to-back MOSFET configuration having first and second MOSFET source terminals separated by a shunt resistor. Ahlers et al. also do not disclose a gate driver circuit having a return terminal coupled to the source terminal of the first MOSFET while a gate drive return current from the gate terminal of the second MOSFET flows through a shunt resistor to the return terminal of the gate driver circuit. Thus, Ahlers et al. do not teach the claimed use of a shunt resistor positioned between source terminals in a gate-drive-return-current sensing path.
Shiomi also does not teach or reasonably suggest the claimed arrangement because Shiomi is directed to transient current reduction in a rectifier circuit involving a transformer, rectifiers, and switching operation. Shiomi does not disclose sensing current in a back-to-back MOSFET configuration by placing a shunt resistor between source terminals of first and second MOSFETs. Shiomi also does not disclose configuring a gate driver return terminal such that gate drive return current from the gate terminal of the second MOSFET flows through the shunt resistor to the return terminal of the gate driver circuit. Therefore, Shiomi does not cure the deficiencies of Ahlers et al.
The combination of Ahlers et al. and Shiomi would not reasonably suggest the claimed structure because neither reference recognizes the specific current-sensing problem addressed by the present claims: that directly coupling common source terminals to the return terminal of a gate driver circuit can bypass or short a shunt resistor placed between the source terminals, thereby preventing effective current sensing. The claimed solution specifically routes the return path associated with the second MOSFET through the shunt resistor and back to the return terminal of the gate driver circuit. This arrangement permits sensing of current through the shunt resistor without requiring placement of the shunt resistor between a MOSFET drain terminal and the voltage source or load, thereby avoiding additional circuit complexity, isolation requirements, and potential degradation in current-sensing response.
Accordingly, the prior art of record does not teach or reasonably suggest, alone or in combination, at least the following limitations of independent claim 1:
a shunt resistor coupled between the source terminals of the first and second MOSFETs; wherein the gate driver circuit includes a return terminal coupled to the source terminal of the first MOSFET; and wherein a return current from the gate terminal of the second MOSFET flows through the shunt resistor to the return terminal of the gate driver circuit.
Similarly, the prior art of record does not teach or reasonably suggest, alone or in combination, at least the following limitations of independent claim 15: a shunt resistor coupled between the source terminals of the first and second MOSFETs; wherein the gate driver circuit includes a return terminal coupled to the source terminal of the first MOSFET; and wherein gate drive return current from the gate terminal of the second MOSFET flows through the shunt resistor to the return terminal of the gate driver circuit.
The dependent claims further recite additional limitations directed to the control signal input and gate drive signal generation, coupling of the MOSFET drain terminals to a voltage source and load, use of an AC voltage source, operational amplifier sensing of voltage drop across the shunt resistor, use of first and second gate drive output terminals with gate driver output resistors, gate resistors coupled between the MOSFET gate terminals and the gate drive output terminal, relative resistance values of the gate resistors, and use of a gate capacitor coupled between a common voltage and a node between the gate terminal of the first MOSFET and the first gate resistor. These additional limitations further define the claimed current-sensing architecture and are not shown by the prior art of record in a manner that would cure the deficiencies discussed above.
Claims 8 & 9 would be allowable if amended to correct the antecedent basis issues identified under 35 U.S.C. 112(b) and to include all limitations of the base and intervening claims. Once the antecedent basis issues are corrected, claims 8 and 9 would further define the timing and gate-control implementation of the allowable current-sensing architecture, including the relative resistance of the first and second gate resistors and the first gate capacitor arrangement.
Claims 2-7, 10-14 & 16-19 variously depending from claims 1 & 15 are allowable for the same above reasons.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance."
During an extensive search (see PE2E attached), the Examiner reviewed the following additional references relevant to the applicant's disclosure. However, these references do not anticipate the claims, nor do they, in combination, render the previously allowable limitations of claims 1-19 obvious.
U.S. 9,509,254 B1 to Cripe discloses a bi-directional Class D half-bridge power amplifier circuit incorporates soft switching components to reduce switching losses by commutating the voltage across the high and low switches of the half-bridge. The power amplifier may further be embodied in an AC power inverter configured to generate 60 Hz sinusoidal current from a DC power source. The AC power inverter may further incorporate an active filter circuit including a current shunt resistor and negative feedback loop to attenuate ripple current from the DC power source by supplying a compensating ripple voltage to the AC power inverter.
U.S. 2008/0037807 A1 to Honda discloses a digital audio driver having a floating PWM input and for controlling a stage of high voltage, high speed high- and low-side MOSFETs series connected at a node. The driver includes a floating input interface circuit having a protection circuit to provide secure protection sequence against over-current conditions; and high and low side circuits for driving the high- and low-side MOSFETs, each high and low side circuit including a bi-directional current sensing circuit which requires no external shunt resistors that enables capture of over-current conditions at either positive or negative load current direction. The R.sub.DS(ON) of the high- and low-side MOSFETs is used as current sensing resistors, once the R.sub.DS(ON) exceeds a pre-determined threshold, an over current output signal is fed to the protection block to shut down the MOSFET to protect the devices.
U.S. 10,715,138 B1 to Jiang discloses an open drain driver circuit includes an output terminal, an input terminal, a first transistor, a second transistor, and a third transistor. The first transistor includes a first terminal coupled to the output terminal, and a second terminal coupled to a reference voltage source. The second transistor includes a first terminal coupled to a third terminal of the first transistor, a second terminal coupled to a power supply rail, and a third terminal coupled to the reference voltage source. The third transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the reference voltage source, and a third terminal coupled to the third terminal of the first transistor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRUNG NGUYEN whose telephone number is (571)272-1966. The examiner can normally be reached on Mon- Friday 8AM - 4:00PM Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Examiner: /Trung Q. Nguyen/- Art 2858
May 28, 2026
/GIOVANNI ASTACIO-OQUENDO/Primary Examiner, Art Unit 2858 5/29/2026
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