N O N - F I N A L A C T I O N
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/13/24 complies with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election / Restriction – Election without Traverse
Applicant’s reply filed on 1/28/2026, elected Species I (representative of Fig. 1-2, 6, and 10) and Sub-Species F (representative of Fig. 23) drawn to claims 1-4 and 6-17, which is without traverse.
Therefore, claims 5 and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected embodiments, there being no allowable generic or linking claim.
Closest Prior Art
The prior art (cited on PTO-892) is considered pertinent to applicant's disclosure. Among these, the following references are considered to be the closest, collectively disclosing the state of the art concerned with pixel array circuitry and ADC circuitry for a solid state image sensor.
MATSUMOTO (US 20080170137) – applied to 35 USC 103 rejection, see Abstract, Fig. 1 & 3 in view of Fig. 8, 12-14, 16-17, and para [0102, 111, 144-148, 256, 258, 260-261, 272, 279, 317, 322, 326, 330-342], discloses pixel array 10, ADC 25/26, comparators 252, DAC 27/27a, ramp signal RAMP, counter 254, timing controller 20.
MORISAKI (US 20180027192) – see Abstract, Fig. 2-6, Fig. 12, and para [0104-105, 112-113, 121-122, 129-130, 221-222, 224, 244-246], discloses pixel array 21, ADC 23N/23S, comparators 72, DAC 51N/51S outputs ramp signal, counter 73, timing controller 52N/52S.
ZHOU YI-CHUN (CN-115665569-A) – applied to 35 USC 103 rejection, (English translation attached), see Abstract, Fig. 5-10, and pages 10-16.
NOTE: Examiner welcomes INTERVIEW(s) to discuss the instant application’s claimed invention as it corresponds to the specification embodiments, as well as, discussing the similarities/differences taught/not taught by prior art. In the interest of compact prosecution, Applicant’s arguments/amendments should not only address the cited closest art applied/relied on in the 35 USC 102/103 rejection (below), but also address the other cited closest art not applied/relied on.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections – 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over MATSUMOTO (US 20080170137) in view of ZHOU YI-CHUN (CN-115665569-A) -- hereafter, termed as shown “underlined”.
As per INDEPENDENT CLAIM 1, MATSUMOTO teaches an analog-digital (AD) conversion circuit for performing AD conversion on a pixel signal (Fig. 1 & 3 in view of Fig. 8, 12-14, 16-17: pixel array 10 and ADC 25/26), the AD conversion circuit comprising:
a plurality of comparators configured to receive a plurality of pixel signals and a ramp signal (Fig. 1 & 3: comparators 252 receives pixel signals from pixel array 10 and ramp signal RAMP from DAC 27/27a);
a count pulse controller configured to generate a counter input signal for counting an average value or a weighted average value of the plurality of pixel signals from a clock signal, based on outputs of the plurality of comparators (Fig. 1 & 3 in view of Fig. 8, 12-14, 16-17: timing controller 20 and counter 254 with count execution unit 504 based on outputs from comparators 252 in view of para [0102, 111, 144-148, 256, 258, 260-261, 272, 279, 317, 322, 326, 330-342]);
and a counter configured to count the average value or the weighted average value of the plurality of pixel signals based on the counter input signal (Fig. 1 & 3 in view of Fig. 8, 12-14, 16-17: timing controller 20 and counter 254 with count execution unit 504 in view of para [0102, 111, 144-148, 256, 258, 260-261, 272, 279, 317, 322, 326, 330-342]. Examiner interprets MATSUMOTO’s counter of “weighted addition” to teach average value or the weighted average value).
Regarding underlined limitation: “a counter configured to count the average value or the weighted average value of the plurality of pixel signals based on the counter input signal” – Examiner has interpreted MATSUMOTO’s counter of “weighted addition” to teach average value or the weighted average value. However, to more robustly/further show this feature was known in the art, Examiner evidences related prior art ZHOU (see FIG. 5-10 and pages 10-16) which discloses counter to count a weighted average of designated pixel groups to achieve a pixel combining binning effect.
Thus, when considering the collective knowledge bestowed by each applied prior art, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to COMBINE the teachings of ZHOU into suitable modification with the teachings of MATSUMOTO to produce Applicant’s claimed invention with the structural arrangement / functional configuration stated in said underlined limitation for the MOTIVATED REASON to achieve a pixel combining binning effect in the analogous art of pixel array circuitry and ADC circuitry for a solid state image sensor.
As per CLAIM 10, MATSUMOTO in view of ZHOU teaches the AD conversion circuit of claim 1, wherein the plurality of pixel signals are pixel signals simultaneously read from a plurality of pixels connected to a same row control line (This feature is consider obvious over the prior art combined teachings. MATSUMOTO, see Fig. 8, 12-14, 16-17; and ZHOU, pages 11-12 and 14-16).
As per CLAIM 11, MATSUMOTO in view of ZHOU teaches the AD conversion circuit of claim 1, wherein the plurality of pixel signals are pixel signals simultaneously read from a plurality of pixels connected to different row control lines (This feature is consider obvious over the prior art combined teachings. MATSUMOTO, see Fig. 8, 12-14, 16-17; and ZHOU, pages 11-12 and 14-16).
As per CLAIM 12, MATSUMOTO in view of ZHOU teaches the AD conversion circuit of claim 11, wherein the plurality of pixel signals are output, from a plurality of pixels arranged in a same column and respectively connected to a plurality of read signal lines, simultaneously through the plurality of read signal lines (This feature is consider obvious over the prior art combined teachings. MATSUMOTO, see Fig. 8, 12-14, 16-17; and ZHOU, pages 11-12 and 14-16).
As per CLAIM 13, MATSUMOTO in view of ZHOU teaches the AD conversion circuit of claim 11, wherein the plurality of pixel signals are output, from a plurality of pixels arranged in a same column and connected to one read signal line, sequentially through the one read signal line (This feature is consider obvious over the prior art combined teachings. MATSUMOTO, see Fig. 8, 12-14, 16-17; and ZHOU, pages 11-12 and 14-16).
Allowable Subject Matter
Claims 15-17 are allowed.
Claims 2-4, 6-9, and 14 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the EXAMINER should be directed to AKSHAY TREHAN whose telephone number is (571) 270-5252. The examiner can normally be reached between the hours of 10am – 6pm during the weekdays Monday – Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TWYLER HASKINS can be reached on (571) 272-7406. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/AKSHAY TREHAN/
Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639
Prosecution Insights