DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, 13, 15-16 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (USPN 6,559,679).
With respect to claim 1, Kim discloses, in Figs. 3-6, a circuit for supplying a clock signal (Fig. 3 operational details disclosed in Figs. 4-6) comprising:
a selector (30) to receive a selection control signal (SEL, SEL is received by 30 via 12, 13 and 20 as the SEL_CLOCK signal) to select one selected clock (output of 30/TEMP_CLOCK) signal out of a plurality of clock signal (CLOCK_A; CLOCK_B) based on the selection control signal (one of CLOCK_A and CLOCK_B being output as TEMP_CLOCK based on both the SEL and SEL_CLOCK signals, see Col. 2 line 52 to Col. 3 line 3 and Fig. 4);
a switch (43, e.g., 43 switches between CLOCK_OUT being produced/output and CLOCK_OUT being prevented from being output, see Fig. 4. Thus, it is a controlled switch) between the selector and an output node (output/CLOCK_OUT node of 43) for outputting a selected clock signal (CLOCK_OUT signal; when ENABLE_2DELAY the selected clock/TEMP_CLOCK is output from 43 as CLOCK_OUT, see Fig. 4);
wherein the circuit is configured so that an application of the selection control signal to select one of the plurality of clock signals causes (application of SEL, see Fig. 4), in order, the turning off of the switch (when ENABLE_2DELAY is low the AND gate can no longer produce CLOCK_OUT and the switch is disabled, see “ENABLE LOW” of ENABLE_2DELAY of Fig. 4, which is responsive to the SEL signal, see SEL, SEL_2Delay, CHANGE, ENABLE, COUNT, SEL_CLOC, TEMP_CLOCK, ENABLE_2DELAY and CLOCK_OUT of Fig. 4), the selection of the one signal out of a plurality of clock signal via the selector (when SEL_CLOCK is high, based on the application of SEL, see CLOCK CONVERSION of Fig. 4 which occurs after ENABLE LOW, wherein ENABLE LOW is responsive to SEL), and the turning on of the switch (when ENABLE_2DELAY is returned high and CLOCK_OUT is generated by the AND gate as an oscillating signal, e.g., see CLOCK_B REGION of Fig. 4, the change is responsive to the SEL signal as shown in FIG. 4).
With respect to claim 2, the circuit of claim 1, wherein the circuit is further configured to turn off the switch when a change in the selection control signal is detected (12-15, 22, 41 and 42 turn off the AND, e.g., produces ENABLE_2DELAY as a low according to detecting a change in the SEL signal, see Fig. 4).
With respect to claim 5, the circuit of claim 2,wherein the circuit is further configured to generate, with a first circuit, a first signal when the change is detected (e.g., 52 generating ENABLE_2DELAY).
With respect to claim 13, the circuit of claim 1, wherein the switch is configured to be on when an output of a first logic block is at a high level, the selected clock signal then also being present on the output node (the switch is on when the first signal SEL/SEL_2DELAY and the other D flip flop signals are high, furthermore when the switch is on the selected clock signal is presented to the output node, see Fig. 4).
Claims 15-16 are rejected for essentially the same reasons as claims 1-2. Note the selection control signal is received at the selector via 12-13 and 20.
With respect to claim 20, a microcontroller comprising the circuit for supplying a clock signal of claim 1 (the clock generator is used in an ASIC, see Col. 1 lines 15-18. An ASIC is a microcontroller due to the broadest reasonable interpretation, since an ASIC controls the circuit for which is applies its application specific control/processing. Furthermore, such devices a constructed from electronics which are miniaturized at small/micro scale. Thus, the ASIC is a microcontroller. Furthermore, the above limitation is merely intended use for which the circuit for supplying the clock is operating. The circuit of Kim is capable of being used with or within a microcontroller).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4, 6, 10 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (USPN 6,559,679).
With respect to claim 3, the circuit of claim 2, wherein the circuit is further configured to select one of the selected clock signal (one of CLOCK_A and CLOCK_B as TEMP_CLOCK according to the SEL_CLOCK signal) after a first delay according to rising edges of a shift signal (delay according to the count value 20 according to the rising edges the shift signal output from 13, note the output of 13 is shifted according to SEL and CLOCK_A. Furthermore, the output of 12 is shifted to 20 as SEL_2DELAY, wherein 20 counts the pulsing of SEL_2DELAY to generate SEL_CLOCK to perform the selection via SEL_CLOCK ,see, Col. 3 lines 55-59), following a detection of the change (the counting occurs at least for sone time period after the detection of the change that controls ENABLE LOW, see Fig. 4. Note the recitation of “following the detection of the change” is merely functional and only requires that the counting occurs at least some point after the detection of the change. The counting is provided after the detection of the change).
Kim fails to disclose how many times the count is performed and thus Kim fails to disclose the counting of “of at least two” of the rising edges following the detection of the change. Nevertheless, the counting, at least in part, occurs after the detection and ENABLE LOW is asserted (see Fig. 4). Furthermore, Kim discloses that the count may be adjustable and thus any desired amount of pulses, see Col. 3 lines 39-43.
It would have been obvious to one of ordinary skill in the art at the time of the invention to adjust the count value such that the selection of the clock signal occurs after two rising edges/pulses of the shift signal for the purpose of setting a desired switch time of the multiplexer and therefore providing a desired timing margin of the switching of the multiplexer that ensures glitches will not occur due to the switching of the multiplexer.
With respect to claim 4, the circuit of claim 3, wherein the circuit is further configured to turn on the switch after a second delay following the selection (the ENABLE_2DELAY signal is configured to switch at a second delay time following the selection, see when ENABLE_2DELAY is pulsed high after the CLOCK CONVERSION of Fig. 4. The above delay is controlled by the counting of 22 which is controlled according to the output of 13, the SEL_2DEALY signal, and 15, see Col. 3 lines 64-67 and Col. 4 lines 21-38. Furthermore, the recitation of “at a second delay time following the selection” is merely a functional limitation and only requires that the turn on of the switch happens according to a delay time after the selection).
Kim fails to disclose that the second delay is equal to “at least two rising edges of the shift signal after the selection”. However, as discussed above, Kim discloses the count value for the delays being adjustable, see Col. 3 lines 39-43.
It would have been obvious to one of ordinary skill in the art at the time of the invention to adjust the count value such that turning on of the switch occurs after two rising edges/pulses of the shift signal after the selection for the purpose of setting a desired switch time of the multiplexer and therefore providing a desired timing margin of the switching of the multiplexer that ensures glitches will not occur due to the switching of the multiplexer.
With respect to claim 6, the circuit of claim 3, wherein the circuit is further configured to generate, with a second circuit, a second signal, originating from a first signal, and time-shifted by the first delay (SEL_CLOCK generated by 20 time shifted from the first delay).
With respect to claim 10, the circuit of claims 3, wherein the shift signal is a clock signal having a frequency smaller than or equal to that of the signal, among the plurality of clock signals, having the smallest frequency (the frequency is equal to CLOCK_A, since 12-14 and 22 are clocked by CLOCK_A).
Claims 17-19 are rejected for essentially the same reasons as claims 3-4.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (USPN 6,559,679) in view of Tohsche (USPN 7,109,772).
With respect to claim 8, Kim discloses, the circuit comprising a third circuit (e.g., 12) configured to authorize a propagation of the selection control signal (SEL input to 12) to the signal selector (via 13 and 20) according to a D-flip flop operation (see Col. 3 lines 9-10).
Kim fails to disclose the operation of the D-flip flop and thus fails to disclose that 12 operates/propagates the input signal (SEL) according to “an output of a first logic block capable of performing a NOR function based on a signal present at the output of an inverter and on a second signal.”
However, Tohsche discloses the specific construction of a D-flip flop (Fig. 4) that propagates the input (D) of the D flip flop according to an output of a first logic block (2c, 13 and 14 propagate the input of D to outputs Q/QN based on the first logic block of 1C) capable of performing a NOR function (22 provides a NOR function) based on a signal present at the output of an inverter (output of 5) and on a second signal (/R).
The D flip-flop of Tohsche has a low propagation delay (see Col. 2 lines 17-49). It would have been obvious to replace the generic D flip-flops of Kim with the specific D flip-flops of Tohsche for the purpose of, among other things, reducing propagation delays.
With respect to claim 9, the circuit of claim 8, the third circuit comprising one latch per control signal forming the selection control signal (2c comprises the at least one latch per control signal. Note, the instant claim uses the term “comprising” which allows for additional elements), each latch having:
a gate input coupled to the output of the first logic block (one of 18 and 17);
a data input configured to receive a corresponding control signal (R and/or /R); and
an output coupled to the signal selector (outputs connected to the output of the D flip-flop which is connected to the signal selector of Kim as modified above).
Allowable Subject Matter
Claims 7, 11-12 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 1/30/2026 have been fully considered but they are not persuasive.
The argument that Kim does not disclose “a selector to receive a selection control signal and to select one selected clock signal out of a plurality of clock signals based on the selection control signal” is not persuasive It can be seen in the rejections above that the selector 30 is connected and operative as claimed responsive to the selection control signal SEL that is received by the multiplexer via 12-13 and 20. It is further noted that Applicant’s selector (320) does not directly receive a selection control signal (MUX_CTRL<8:0>), but rather a processed selection signal controlled/delayed by 340, 310, 325 and 360. This is similar to that of the processing of the SEL selection control signal of Kim.
Furthermore, Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Moreover, Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
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