DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments/amendments filed Jan. 06, 2026 have been fully considered but are not persuasive.
Claim Objections
2. The claim(s) is/are objected to because of the following informalities:
Regarding claim 15, the claim limitation “…at least one capacitor cells…” should be “…at least one capacitor cell…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1, 2 and 8-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura (2013/0093524).
Regarding claim 1, Nakamura discloses a phase-locked loop (PLL) circuit (Fig.13 or 16, please refer to the whole reference for detailed), comprising: an oscillator (DCO in Figs.1, 13 and 16) including a first capacitor cell array (CRFAC) and a second capacitor cell array (CINT), each including a plurality of capacitor cells (at least CFRAC and CINT in Fig.1) having different capacitances from each other (Fig.14; please refer to at least ¶ 47, 57-59 and 93); and a control logic circuit (TDC, DLPF MMD and SDM in Fig.1) connected to the oscillator, the control logic circuit configured to generate a control code (BIT_CF and BIT_CI) configured to control the oscillator such that the oscillator is configured to output a signal (OscP/OscM in Fig.1 (or) PLLOUT in Fig.13 and 16) with a target frequency (REF in Fig.13 and 16), the control code (BIT_CF and BIT_CI) generated based on a first frequency of a first signal output from the oscillator and the target frequency (REF; which is a function of feedback loop control provided by TDC, DLPF and MMD in Fig.13 (or) TDC, DLPF, ADD1, MMD, SDM and ADD2 in Fig.16), control at least some of the capacitor cells included in the first capacitor cell array (CRFAC) based on a first partial code (BIT_CF) generated based on a specified number of bits (BIT_CF[i] in Fig.1 and 3) of the control code, and control at least some of the capacitor cells included in the second capacitor cell array (CINT) based on a second partial code (BIT_CI) generated based on bits (BIT_CI[n] in Fig.1 and 2) other than the specified number of bits of the control code, wherein the oscillator configured to output a second signal (PLLOUT) with a second frequency (when DAT-DIVN in Fig.13 is changed; ¶ 7, 91 and 99) through an electrical path including capacitor cells configured to be turned on, from among the plurality of capacitor cells (at least CFRAC and CINT in Fig.1) included in the oscillator, and wherein each of the capacitor cells in the first capacitor cell array (CRFAC in Fig.12) and the second capacitor cell array (CINT in Fig.11) has a same area as each other (according to Figs.11 and 12 and ¶ 48, which states “the fractional value capacitor block CFBK in the capacitor bank CFRAC is configured by combining capacitor units having the same circuit configuration as the unitary capacitor unit CIU in the capacitor bank CINT and substantially the same layout configuration as that in plural form”, thus each capacitor units (capacitor cells) in the first capacitor array (CFRAC) and the second capacitor array (CIU) has a same area as each other) and different capacitance changes from each other (please refer to at least ¶ 47, 48, 57-59 and 93; Note: due to the CFRAC is configured by combining capacitor units, thus there has different capacitance changes compare to the CIU, where the capacitance changes is depending on the control signals to the CFRAC and CIU).
Regarding claim 2, Nakamura discloses the control logic (TDC, DLPF MMD and SDM in Fig.1) is configured to, in response to controlling one capacitor cell (CFBK) of the first capacitor cell array (CRFAC), change a capacitance of the first capacitor cell array by a first capacitance (using BIT_CF), and in response to controlling one capacitor cell (CIU) of the second capacitor cell array (CINT), change a capacitance of the second capacitor cell array by a second capacitance (using BIT_CI), a value of the second capacitance (capacitance of CIU) obtained based on multiplying a first integer by the first capacitance (capacitance of CFBK; according to ¶ 56, which states “a fractional-value capacitor block CFBK that realizes an amount of change in capacitance equivalent to ½ of ∆CINT takes a configuration equipped with the unitary capacitor units CIU[1] and CIU[2]”, which meant a value of second capacitance (capacitance of CIU) obtained based on multiplying two by the first capacitance (capacitance of CFBK)).
Regarding claim 8, Nakamura discloses a plurality of row control lines and a plurality of column control lines connected to the capacitor cells included in the second capacitor cell array (CINT in Fig.8); a row decoder (DEC in Fig.8) configured to select at least some of the plurality of row control lines by decoding a row component of the second partial code; and a column decoder (DEC) configured to select at least some of the plurality of column control lines by decoding a column component of the second partial code (Fig.8, and please refer to at least ¶ 67 and 71).
Regarding claim 9, Nakamura discloses each of the capacitor cells included in the first capacitor cell array (CRFAC) and each of the capacitor cells included in the second capacitor cell array (CINT) have a same area (Fig.9, 11 and 12 shows CFBK (capacitor cells of CRFAC) and CIU (capacitor cells of CINT) in Fig.1 have a same area).
Regarding claim 10, Nakamura discloses each of a plurality of capacitor cells (at least CFRAC and CINT in Fig.1) included in the oscillator (DCO) includes at least two or more capacitors connected in series with each other and a transistor connected between the capacitors (CIU and CFBK in Figs.1, 11 and 12), and the control logic circuit is configured to turn on a transistor of a capacitor cell selected based on the control code (BIT_CF and BIT_CI), from among the plurality of capacitor cells.
Regarding claim 11, Nakamura discloses a control method of a phase-locked loop (PLL) circuit (Fig.13 or 16, please refer to the whole reference for detailed), the method comprising: generating a control code (BIT_CF and BIT_CI) for controlling at least some of a plurality of capacitor cells (at least CFRAC and CINT in Fig.1) included in an oscillator (DCO in Figs.1, 13 and 16) based on a first frequency of a first signal output from the oscillator and a target frequency (REF in Fig.13 and 16; which is a function of feedback loop control provided by TDC, DLPF and MMD in Fig.13 (or) TDC, DLPF, ADD1, MMD, SDM and ADD2 in Fig.16); controlling at least some capacitor cells of a first capacitor cell array (CRFAC) included in the oscillator based on a first partial code (BIT_CF) generated based on a specified number of bits (BIT_CF[i] in Fig.1 and 3) of the control code; controlling at least some capacitor cells of a second capacitor cell array (CINT) included in the oscillator based on a second partial code (BIT_CI) generated based on bits (BIT_CI[n] in Fig.1 and 2) other than the specified number of bits of the control code; and outputting, by the oscillator, a second signal (PLLOUT) with a second frequency (when DAT-DIVN in Fig.13 is changed; ¶ 7, 91 and 99) through an electrical path including capacitor cells, which are turned on, from among the plurality of capacitor cells (CFRAC and CINT in Fig.1), and wherein the first capacitor cell array and the second capacitor cell array include different numbers of capacitor cells with different capacitances from each other (Fig.14; please refer to at least ¶ 47, 57-59 and 93), and wherein each of the capacitor cells in the first capacitor cell array (CRFAC in Fig.12) and the second capacitor cell array (CINT in Fig.11) has a same area as each other (according to Figs.11 and 12 and ¶ 48, which states “the fractional value capacitor block CFBK in the capacitor bank CFRAC is configured by combining capacitor units having the same circuit configuration as the unitary capacitor unit CIU in the capacitor bank CINT and substantially the same layout configuration as that in plural form”, thus each capacitor units (capacitor cells) in the first capacitor array (CFRAC) and the second capacitor array (CIU) has a same area as each other) and different capacitance changes from each other (please refer to at least ¶ 47, 48, 57-59 and 93; Note: due to the CFRAC is configured by combining capacitor units, thus there has different capacitance changes compare to the CIU, where the capacitance changes is depending on the control signals to the CFRAC and CIU).
Regarding claim 12, Nakamura discloses in response to controlling one capacitor cell (CFBK) of the first capacitor cell array (CRFAC), changing a capacitance of the first capacitor cell array by a first capacitance (using BIT_CF), and in response to controlling one capacitor cell (CIU) of the second capacitor cell array (CINT), changing a capacitance of the second capacitor cell array by a second capacitance (using BIT_CI), a value of the second capacitance (capacitance of CIU) obtained based on multiplying a first integer by the first capacitance (capacitance of CFBK; according to ¶ 56, which states “a fractional-value capacitor block CFBK that realizes an amount of change in capacitance equivalent to ½ of ∆CINT takes a configuration equipped with the unitary capacitor units CIU[1] and CIU[2]”, which meant a value of second capacitance (capacitance of CIU) obtained based on multiplying two by the first capacitance (capacitance of CFBK)).
5. Claims 1-3, 5, 7-9 and 11-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (IEEE Title: “A Compact 22-Gb/s Transmitter for Optical Links with All-Digital Phase-Locked Loop”, cited by Applicant in the IDS submitted on April 04, 2025) (hereinafter “Kim”).
Regarding claim 1, Kim discloses a phase-locked loop (PLL) circuit (PLL in Fig.3, please refer to the whole reference for detailed), comprising: an oscillator (LC DCO in Fig.3 and LC-type oscillator in Fig.4(a)) including a first capacitor cell array (Fine Tuning Cells in Fig.4(a)) and a second capacitor cell array (Coarse Tuning Cells in Fig.4(a)), each including a plurality of capacitor cells having different capacitances from each other (section “B. Digitally Controller Oscillator”, which states “coarse tuning cell has four times larger capacitance than that of the fine tuning cell”); and a control logic circuit (TDC, DLF, DSM and dividers in Fig.3) connected to the oscillator, the control logic circuit configured to generate a control code (control code output from “Fine”, “Row Decoder” and “Column Decoder” based on INT_CTRL[9:0] in Fig.4(a)) configured to control the oscillator such that the oscillator is configured to output a signal with a target frequency (REF_CLK in Fig.3), the control code generated based on a first frequency of a first signal output from the oscillator and the target frequency (due to feedback loop control provided by PLL), control at least some of the capacitor cells included in the first capacitor cell array based on a first partial code (code output from “Fine” based on INT_CTRL[1:0] in Fig.4(a)) generated based on a specified number of bits (INT_CTRL [1:0]) of the control code, and control at least some of the capacitor cells included in the second capacitor cell array (Coarse Tuning Cells in Fig.4(a)) based on a second partial code (code output from “Row Decoder” and “Column Decoder” based on INT_CTRL[9:2] in Fig.4(a)) generated based on bits (INT_CTRL[9:2]) other than the specified number of bits of the control code, wherein the oscillator is configured to output a second signal with a second frequency (by switching the MIM_TUNE[1:0] in Fig.4(a)) through an electrical path including capacitor cells configured to be turned on, from among the plurality of capacitor cells included in the oscillator (Fig.4(a)), and wherein each of the capacitor cells in the first capacitor cell array (Coarse Tuning Cells in Fig.4(b)) and the second capacitor cell array (Fine Tuning Cells in Fig.4(b)) has a same area as each other (Fig.4(b) shows each of the capacitor cells in the Coarse Tuning Cells and Fine Tuning Cells has a same area as each other) and different capacitance changes from each other (according to section “B. Digitally Controlled Oscillator” on page 2858, which discloses “The coarse tuning cell has four times larger capacitance than that of the fine tuning cell and takes a thermometer decoded frequency control word of 8 MSBs from DLF. The fine tuning cell accepts a thermometer decoded frequency control word from 2 LSBs from DLF”, thus the capacitance changes in coarse tuning cells would be different from the capacitance changes in fine tuning cells due to at least two different capacitance sizes are used in the coarse tuning cells and the fine tuning cells).
Regarding claim 2, Kim discloses the control logic (TDC, DLF, DSM and dividers in Fig.3) is configured to, in response to controlling one capacitor cell of the first capacitor cell array (Fine Tuning Cells in Fig.4(a)), change a capacitance of the first capacitor cell array by a first capacitance, and in response to controlling one capacitor cell of the second capacitor cell array (Coarse Tuning Cells in Fig.4(a)), change a capacitance of the second capacitor cell array by a second capacitance, a value of the second capacitance obtained based on multiplying a first integer by the first capacitance (section “B. Digitally Controller Oscillator”, which states “coarse tuning cell has four times larger capacitance than that of the fine tuning cell”).
Regarding claim 3, Kim discloses the control code includes thermometer code, and the control logic circuit is configured to control at least some of the plurality of capacitor cells such that capacitance of the oscillator is configured to change based on a capacitance corresponding to the thermometer code (please refer to section “B. Digitally Controller Oscillator”).
Regarding claim 5, Kim discloses the first capacitor cell array (Fine Tuning Cells in Fig.4(a)) includes a first number of capacitor cells, and when the control code is less than or equal to the first number, the control logic circuit is configured to control a number of capacitor cells, the number corresponding to the control code, from among the first capacitor cell array based on the first partial code (code output from “Fine” based on INT_CTRL[1:0] in Fig.4(a)).
Regarding claim 7, Kim discloses the control logic circuit includes: a comparator (TDC in Fig.3) configured to generate the control code by comparing the first frequency (frequency based on output of LC DCO) with the target frequency (REF_CLK); a dithering circuit (DSM) configured to generate a dithering signal by dithering the control code; a first decoder (Fine in Fig.4(a)) configured to generate the first partial code (code output from “Fine” based on INT_CTRL[1:0] in Fig.4(a)) by decoding the specified number of bits (INT_CTRL [1:0]) of the dithering signal; and a second decoder (Row Decoder and Column Decoder) configured to generate the second partial code (code output from “Row Decoder” and “Column Decoder” based on INT_CTRL[9:2] in Fig.4(a)) by decoding bits other than the specified number of bits (INT_CTRL[9:2]) of the dithering signal.
Regarding claim 8, Kim discloses a plurality of row control lines and a plurality of column control lines (Fig.4(a)) connected to the capacitor cells included in the second capacitor cell array; a row decoder (Row Decoder in Fig.4(a)) configured to select at least some of the plurality of row control lines by decoding a row component of the second partial code; and a column decoder (Column Decoder in Fig.4(a)) configured to select at least some of the plurality of column control lines by decoding a column component of the second partial code.
Regarding claim 9, Kim discloses each of the capacitor cells included in the first capacitor cell array and each of the capacitor cells included in the second capacitor cell array have a same area (coarse tuning cells and fine tuning cells in Fig.4(a)).
Regarding claim 11, Kim discloses a control method of a phase-locked loop (PLL) circuit (PLL in Fig.3, please refer to the whole reference for detailed), the method comprising: generating a control code (control code output from “Fine”, “Row Decoder” and “Column Decoder” based on INT_CTRL[9:0] in Fig.4(a)) for controlling at least some of a plurality of capacitor cells (Fine Tuning Cells and Coarse Tuning Cells) included in an oscillator (LC type oscillator in Fig.4(a); LCDCO in Fig.3) based on a first frequency of a first signal output from the oscillator and a target frequency (REF_CLK); controlling at least some capacitor cells of a first capacitor cell array (Fine Tuning Cells in Fig.4(a)) included in the oscillator based on a first partial code (code output from “Fine” based on INT_CTRL[1:0] in Fig.4(a)) generated based on a specified number of bits (INT_CTRL [1:0]) of the control code; controlling at least some capacitor cells of a second capacitor cell array (Coarse Tuning Cells in Fig.4(a)) included in the oscillator based on a second partial code (code output from “Row Decoder” and “Column Decoder” based on INT_CTRL[9:2] in Fig.4(a)) generated based on bits (INT_CTRL[9:2]) other than the specified number of bits of the control code; and outputting, by the oscillator, a second signal with a second frequency (by switching the MIM_TUNE[1:0] in Fig.4(a)) through an electrical path including capacitor cells, which are turned on, from among the plurality of capacitor cells (Fig.4(a)), wherein the first capacitor cell array and the second capacitor cell array include different numbers of capacitor cells with different capacitances from each other (section “B. Digitally Controller Oscillator”, which states “coarse tuning cell has four times larger capacitance than that of the fine tuning cell”), and wherein each of the capacitor cells in the first capacitor cell array (Coarse Tuning Cells in Fig.4(b)) and the second capacitor cell array (Fine Tuning Cells in Fig.4(b)) has a same area as each other (Fig.4(b) shows each of the capacitor cells in the Coarse Tuning Cells and Fine Tuning Cells has a same area as each other) and different capacitance changes from each other (according to section “B. Digitally Controlled Oscillator” on page 2858, which discloses “The coarse tuning cell has four times larger capacitance than that of the fine tuning cell and takes a thermometer decoded frequency control word of 8 MSBs from DLF. The fine tuning cell accepts a thermometer decoded frequency control word from 2 LSBs from DLF”, thus the capacitance changes in coarse tuning cells would be different from the capacitance changes in fine tuning cells due to at least two different capacitance sizes are used in the coarse tuning cells and the fine tuning cells).
Regarding claim 12, Kim discloses in response to controlling one capacitor cell of the first capacitor cell array (Fine Tuning Cells in Fig.4(a)), changing a capacitance of the first capacitor cell array by a first capacitance, and in response to controlling one capacitor cell of the second capacitor cell array (Coarse Tuning Cells in Fig.4(a)), changing a capacitance of the second capacitor cell array by a second capacitance, a value of the second capacitance obtained by multiplying a first integer by the first capacitance (section “B. Digitally Controller Oscillator”, which states “coarse tuning cell has four times larger capacitance than that of the fine tuning cell”).
Regarding claim 13, Kim discloses the control code includes thermometer code, and the method comprises: controlling at least some of the plurality of capacitor cells such that capacitance of the oscillator changes based on a capacitance corresponding to the thermometer code (please refer to section “B. Digitally Controller Oscillator”).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (IEEE Title: “A Compact 22-Gb/s Transmitter for Optical Links with All-Digital Phase-Locked Loop”, cited by Applicant in the IDS submitted on April 04, 2025) (hereinafter “Kim”) in view of Nakamura (2013/0093524).
Regarding claim 10, Kim is used to reject claim 1 above.
Kim doesn’t disclose each of a plurality of capacitor cells included in the oscillator (DCO) includes at least two or more capacitors connected in series with each other and a transistor connected between the capacitors, and the control logic circuit is configured capacitanceto turn on a transistor of a capacitor cell selected based on the control code, from among the plurality of capacitor cells.
Nakamura discloses each of a plurality of capacitor cells (at least CFRAC and CINT in Fig.1) included in the oscillator (DCO) includes at least two or more capacitors connected in series with each other and a transistor connected between the capacitors (CIU and CFBK in Figs.1, 11 and 12), and the control logic circuit is configured to turn on a transistor of a capacitor cell selected based on the control code (BIT_CF and BIT_CI), from among the plurality of capacitor cells.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teaching of Nakamura to provide each of a plurality of capacitor cells included in the oscillator (DCO) includes at least two or more capacitors connected in series with each other and a transistor connected between the capacitors, and the control logic circuit is configured to turn on a transistor of a capacitor cell selected based on the control code, from among the plurality of capacitor cells. The suggestion/motivation would have been to use functionally equivalent method to set the capacitor cells.
Allowable Subject Matter
9. Claims 4, 6 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
10. Claims 17-20 are allowed.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/Richard Tan/Primary Examiner 2849