DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
However, should applicant desire to obtain the benefit of foreign priority under 35
U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of
the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and
41.202(e).
Failure to provide a certified translation may result in no benefit being accorded
for the non-English application.
Information Disclosure Statement
The information disclosure statement (IDS) filed on September 13, 2024 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-8 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Tanaka, US PGPub 2021/0045242 A1.
Regarding Claim 1, Tanaka discloses a wiring board comprising (FIG. 16, wiring board 510, [0103]):
a first interconnect structure including a first interconnect layer and a first insulating layer (See annotated FIG. 16, first interconnect layer 60 connected to and filling through hole 270X, conductor layer 40, insulating layer 370 together make first interconnect structure in solid lined box, [0103]);
a second interconnect structure, including a second interconnect layer and a second insulating layer, and laminated on one side of the first interconnect structure (See annotated FIG. 16, interconnect layer 90 connected to and filling through holes 80X and 80Y, solder resist layer 130, all together make second interconnect structure in short-dashed box on one side of first interconnect structure, [0103]);
and a third interconnect structure, including a third interconnect layer and a third insulating layer, and laminated on the other side of the first interconnect structure (See annotated FIG. 16, interconnect layer 20 connected to and filling through holes 30X, insulating layer 30 together make third interconnect structure in long-dashed box on other side of first interconnect structure, [0072, 0103]),
wherein the second interconnect layer has an interconnect density higher than interconnect densities of the first interconnect layer and the third interconnect layer (See annotated FIG. 16, short-dashed box has higher interconnect density than solid and long-dashed boxes, as seen in interconnect layer 90, where 90 is connected to and filling through holes 80X and 80Y, and short-dashed box is thinner than, for example, the solid lined box (layers 270, 370 are both at least 40-100µm, whereas the interconnect layer 90 through 80X, 80Y is at least 10-30µm) and contains more interconnections (all four shown portions of interconnect layer 90 and associated filled through holes 80X, 80Y), [0058, 0062, 0107, 0109]),
the first insulating layer has a through hole penetrating the first insulating layer (See annotated FIG. 16, opening 100 (through holes 270Y, 370Y) in insulating layer 370, [0110]),
an electronic component electrically connected to the second interconnect layer is disposed inside the through hole (See annotated FIG. 16, electronic component 110 in opening 100, connected to interconnect layer 90 connected to and filling through holes 80Y via electrode 111, [0104, 0111]),
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an embedding resin covering the electronic component is provided inside the through hole, and the embedding resin extends from inside the through hole to cover the first insulating layer, and fills in between the first insulating layer and the second insulating layer (See annotated FIG. 16, insulating layer 80 (i.e., a layer of insulating resin or the like) filling opening 100 around embedded electronic component 110 and filling between insulating layer 370 and solder resist layer 130, [0039, 0111]).
Regarding Claim 2, Tanaka discloses the wiring board as claimed in claim 1, as discussed above.
Tanaka further discloses wherein: the first interconnect layer includes an electronic component mounting pad, at least a portion of an upper surface of the electronic component mounting pad is exposed inside the through hole, and the electronic component is disposed on the upper surface of the electronic component mounting pad exposed inside the through hole (See annotated FIG. 16, FIG. 15A, in solid lined box, metal layer 42, an upper surface of 42 is exposed in opening 100, electronic component 110 is disposed on the exposed upper surface of 42 in opening 100, [0086-0089, 0104]).
Regarding Claim 4, Tanaka discloses the wiring board as claimed in claim 1, as discussed above.
Tanaka further discloses wherein: the embedding resin is formed integrally with the second insulating layer in contact with the first insulating layer (See annotated FIG. 16, insulating layer 80 and solder resist layer 130 can be formed of the same material (insulating resins, for example) and thus would be “formed integrally,” insulating layer 80/solder resist layer 130 is in contact with insulating layer 370, [0039, 0062]),
and an electrode of the electronic component is directly connected to the second interconnect layer (See annotated FIG. 16, electrodes 111 of electronic component 110 is directly connected to second interconnect layer 90 by through holes 80Y).
Regarding Claim 5, Tanaka discloses the wiring board as claimed in claim 4, as discussed above.
Tanaka further discloses wherein: the first interconnect layer includes a first via interconnect (See annotated FIG. 16, interconnect layer 60, 60 is connected to and filling through hole (i.e., via) 270X),
an upper surface of the first via interconnect is exposed from an upper surface of the first insulating layer in contact with the second insulating layer (See annotated FIG. 16, upper surface of through hole (i.e., via) 270X indicated by solid arrow is exposed from (i.e., not covered or overlapped by) the upper surface of insulating layer 370 in contact with insulating layer 80/solder resist layer 130 (the interface highlighted by the small short-and-long-dashed boxes)),
the upper surface of the first via interconnect coincides with the upper surface of the first insulating layer in contact with the second insulating layer (See annotated FIG. 16, upper surface of 270X indicated by solid arrow coincides with (i.e., occurs at same time) an interface or contact between insulating layer 370 and insulating layer 80/solder resist 130 (again, see examples of such contact by small short-and-long-dashed boxes),
and the first via interconnect is directly connected to a lowermost layer of the second interconnect layer (See annotated FIG. 16, through holes 270X directly connected to a lowermost layer (e.g., lowermost portion of through holes 80X of second interconnect layer 90)).
Regarding Claim 6, Tanaka discloses the wiring board as claimed in claim 1, as discussed above.
Tanaka further discloses wherein: the first interconnect layer includes a first via interconnect (See secondly annotated FIG. 16 below, interconnect layer 60, connected to and filling through hole (i.e., via) 270X),
an upper surface of the first via interconnect is exposed from an upper surface of the embedding resin in contact with the second insulating layer (See secondly annotated FIG. 16 below, upper surface of 270X indicated by solid arrow is exposed from (i.e., not covered or overlapped by) an upper surface of insulating layer 80 in contact with solder resist layer 130 (examples of such contact highlighted with short-and-long-dashed boxes)),
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the upper surface of the first via interconnect coincides with the upper surface of the embedding resin in contact with the second insulating layer (See secondly annotated FIG. 16 below, upper surface of 270X (indicated with the solid arrow) coincides with (i.e., occurs at the same time) an upper surface of insulating layer 80 in contact with solder resist layer 130 (again highlighted by, for example, short-and-long-dashed boxes)),
and the first via interconnect is directly connected to a lowermost layer of the second interconnect layer (See secondly annotated FIG. 16 above, through holes 270X directly connected to a lowermost layer (e.g., lowermost portion of through holes 80X of second interconnect layer 90)).
Regarding Claim 7, Tanaka discloses the wiring board as claimed in claim 1, as discussed above.
Tanaka further discloses wherein: the first interconnect structure includes a plurality of the first insulating layers (See annotated FIG. 16, solid lined box contains a plurality (i.e., at least two) insulating layers 270, 370),
and the electronic component is disposed inside the through hole that penetrates an uppermost layer of the first insulating layer (See annotated FIG. 16, opening 100 penetrates an uppermost layer (insulating layer 370) of the first insulating layers 370/270).
Regarding Claim 8, Tanaka discloses a semiconductor device comprising: the wiring board according to claim 1; as discussed above.
Tanaka further discloses and a semiconductor chip provided on the second interconnect structure of the wiring board (See annotated FIG. 16, pads P2 “function as a pad for mounting and electrically connecting an electronic component such as a semiconductor chip or the like, on the wiring board 10,” [0063]).
Claims 1-2, 4-8 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Shimizu, US PGPub 2016/02333167 A1.
Regarding Claim 1, Shimizu discloses a wiring board comprising (FIGs. 1, 3, Semiconductor element built-in wiring board 1):
a first interconnect structure including a first interconnect layer and a first insulating layer (See annotated FIG. 3, solid lined box occupying base substrate 20 including via conductor 208, conductor layers 201, 203, plane layer 207, insulating layers 200, 202, [0027-0030, 0035-0036]);
a second interconnect structure, including a second interconnect layer and a second insulating layer, and laminated on one side of the first interconnect structure (See annotated FIG. 3, short-dashed box, second build-up layer 40, via conductors 209, 210, 402, conductor layer 205, conductor pads 401, insulating layers 204, 400, solder resist layer 403, [0037, 0040-0041, 0044-0045]);
and a third interconnect structure, including a third interconnect layer and a third insulating layer, and laminated on the other side of the first interconnect structure (See annotated FIG. 3, long-dashed box, build-up layer 30, conductor pads 301, via conductors 302, insulating layer 300, [0038-0039, 0043]),
wherein the second interconnect layer has an interconnect density higher than interconnect densities of the first interconnect layer and the third interconnect layer (See annotated FIG. 3, short-dashed box showing second interconnect layer has higher interconnect density than solid and long-dashed boxes),
the first insulating layer has a through hole penetrating the first insulating layer (See annotated FIG. 3, recess 206 penetrating insulating layers 200, 20, [0030]),
an electronic component electrically connected to the second interconnect layer is disposed inside the through hole (See annotated FIG. 3, semiconductor element 10 disposed inside recess 206, with terminals 11 connected electrically with via conductors 210 of second interconnect layer, i.e., short-dashed box, [0030-0031]),
an embedding resin covering the electronic component is provided inside the through hole, and the embedding resin extends from inside the through hole to cover the first insulating layer, and fills in between the first insulating layer and the second insulating layer (See annotated FIG. 3, semiconductor element 10 inside recess 206 covered by insulating layer 204 (and can be of “a resin material”) and fills between insulating layers 200/202 and insulating layer 400, [0033]).
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Regarding Claim 2, Shimizu discloses the wiring board as claimed in claim 1, as discussed above.
Shimizu further discloses wherein: the first interconnect layer includes an electronic component mounting pad, at least a portion of an upper surface of the electronic component mounting pad is exposed inside the through hole, and the electronic component is disposed on the upper surface of the electronic component mounting pad exposed inside the through hole (See annotated FIG. 3, solid lined box including plane layer 207, a portion of an upper surface of 207 exposed in recess 206, semiconductor element 10 disposed on that upper surface of 207, [0030, 0032]).
Regarding Claim 4, Shimizu discloses the wiring board as claimed in claim 1, as discussed above.
Shimizu further discloses wherein: the embedding resin is formed integrally with the second insulating layer in contact with the first insulating layer (See annotated FIG. 3, insulating layers 204 and 400 both are formed of resin materials and so can be considered as “formed integrally”, and in contact with insulating layers 202/200, [0033, 0040]),
and an electrode of the electronic component is directly connected to the second interconnect layer (See annotated FIG. 3, terminal 11 of semiconductor element 10 directly connected to via conductors 210 of second interconnect layer (i.e., short-dashed box)).
Regarding Claim 5, Shimizu discloses the wiring board as claimed in claim 4, as discussed above.
Shimizu further discloses wherein: the first interconnect layer includes a first via interconnect (See annotated FIG. 3, solid lined box with via conductor 208),
an upper surface of the first via interconnect is exposed from an upper surface of the first insulating layer in contact with the second insulating layer (See annotated FIG. 3, upper surface of via conductor 208 (highlighted with solid arrow) is exposed from (i.e., not covered or overlapped by) upper surface of insulating layers 202/200 in contact with insulating layers 204/400 (highlighted by short-and-long-dashed box)),
the upper surface of the first via interconnect coincides with the upper surface of the first insulating layer in contact with the second insulating layer (See annotated FIG. 3, upper surface of via conductor 208 coincides with (i.e., occurs are same time as) upper surface of insulating layers 202/200 in contact with insulating layers 204/400 (highlighted by short-and-long-dashed box)),
and the first via interconnect is directly connected to a lowermost layer of the second interconnect layer (See annotated FIG. 3, via conductor 208 directly connected with conductor layer 205 (i.e., lowermost layer) of second interconnect layer (short-dashed box)).
Regarding Claim 6, Shimizu discloses the wiring board as claimed in claim 1, as discussed above.
Shimizu further discloses wherein: the first interconnect layer includes a first via interconnect (See secondly annotated FIG. 3 below, solid lined box with via conductor 208),
an upper surface of the first via interconnect is exposed from an upper surface of the embedding resin in contact with the second insulating layer (See secondly annotated FIG. 3 below, upper surface of via conductor 208 (highlighted with solid arrow) is exposed from (i.e., not covered or overlapped by) upper surface of insulating layer 204 in contact with insulating layer 400 (highlighted by short-and-long-dashed box)),
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the upper surface of the first via interconnect coincides with the upper surface of the embedding resin in contact with the second insulating layer (See secondly annotated FIG. 3 below, upper surface of via conductor 208 coincides with (i.e., occurs are same time as) upper surface of insulating layers 204 in contact with insulating layer 400 (highlighted by short-and-long-dashed box)),
and the first via interconnect is directly connected to a lowermost layer of the second interconnect layer (See secondly annotated FIG. 3 above, via conductor 208 directly connected with conductor layer 205 (i.e., lowermost layer) of second interconnect layer (short-dashed box)).
Regarding Claim 7, Shimizu discloses the wiring board as claimed in claim 1, as discussed above.
Shimizu further discloses wherein: the first interconnect structure includes a plurality of the first insulating layers (See annotated FIG. 3, solid lined box includes a plurality (i.e., at least two) insulating layers 202/200),
and the electronic component is disposed inside the through hole that penetrates an uppermost layer of the first insulating layer (See annotated FIG. 3, semiconductor element 10 in recess 206, recess 206 penetrates uppermost layer (insulating layer 202) of first insulating layer (insulating layers 202/200), [0030]).
Regarding Claim 8, Shimizu discloses a semiconductor device comprising: the wiring board according to claim 1 as discussed above.
Shimizu further discloses and a semiconductor chip provided on the second interconnect structure of the wiring board (See annotated FIG. 3, chip 4 on second interconnect structure (short-dashed box), of wiring board 1, i.e., chip 4 connected through solder bumps 54 to conductor pads 401 of second interconnect structure/short-dashed box).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Tanaka as applied to Claim 2 above.
Regarding Claim 3, Tanaka discloses the wiring board as claimed in claim 2, as discussed above.
Tanaka does not explicitly show wherein the electronic component mounting pad forms a portion of an electrical path connecting the electronic component and the third interconnect layer.
Although not explicitly shown in the modification of FIG. 16, Tanaka does disclose metal layer 42 be an interconnect pattern and connected to other layers through via interconnects (e.g., like through 30X between interconnect layers 20 and 41).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the disclosed modification to connect metal layer 42 to interconnect layer 20 for the purposes of, for example, providing an interconnect path or routing for power supply or ground, such that
wherein the electronic component mounting pad forms a portion of an electrical path connecting the electronic component and the third interconnect layer (See annotated FIG. 16, metal layer 42 can be “electrically connected to another interconnect layer or conductor layer through the via interconnect or the like, for example”, [0045]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu as applied to Claim 2 above.
Regarding Claim 3, Shimizu discloses the wiring board as claimed in claim 2, as discussed above.
Shimizu does not explicitly show in the first embodiment (i.e., FIG. 3) wherein the electronic component mounting pad forms a portion of an electrical path connecting the electronic component and the third interconnect layer.
However, the third embodiment as seen in FIG. 5 does show such an electrical path with via conductor 305 providing electrical connection between plane layer 207 and conductor pads 301 wherein such a modification would be beneficial for efficient transfer of heat and thus suppressing of thermal stress, [0058, 0060]
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first embodiment as seen in FIG. 3 with the via conductor 305 of the third embodiment, which forms a portion of an electrical path between the plane layer 207 and conductor pads 301 of the third interconnect layer for the benefit of improved heat transfer and management, such that
wherein the electronic component mounting pad forms a portion of an electrical path connecting the electronic component and the third interconnect layer (See annotated FIG. 3, FIG. 5, plane layer 207, via conductor 305 forming portion of electrical patch between plane layer 207 and conductor pads 301 of the third interconnect layer (long-dashed box)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sato, US PGPub 2023/0199967 A1, which is directed to embedded printed circuit boards, wherein electronic components are embedded in the wiring board.
Choi et al., US PGPub 2015/0062850 A1, which is directed to a printed circuit board of multiple interconnect layers and with embedded electronic components for reduced chip-to-board distance.
Furuta, US PGPub 2009/0140415 A1, which is directed to a similar wiring board with embedded electronic components in through-holes and covered in insulating layers or resins.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Austin T. Woodard whose telephone number is (571)270-1958. The examiner can normally be reached M-F, 8am to 5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Austin T Woodard/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
