Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This office action is in response to the application filed on 09/13/2024.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawing
The drawing filed on 09/13/2024 is acceptable.
Claims 1-6 are pending and have been examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/13/2024 is in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MacLean
et al. (US 6,965,223 B1), hereinafter ‘MacLean.
In re to claim 1, MacLean disclose a load drive circuit (i.e. 200, fig. 2, see col. 3, lines 43-47) comprising: an n-channel output transistor (i.e. 236) of which the drain is connected to a power supply (i.e. VIN), and which applies an output from the source to a load (i.e. RO) when the output is ON (i.e. see col. 3, lines 48-53); and a soft start reference block (i.e. 210, see col. 3, lines 48-53) that applies a soft start voltage between the gate and the source of the output transistor (i.e. 236) in a predetermined period from when the output is started to be ON (i.e. see col. 4, lines 4-16); wherein the soft start reference block applies, between the gate and the source of the output transistor (i.e. 236), a soft start voltage corresponding to the gate-source voltage of a reference transistor (i.e. 222) through which a current from a current source is made to flow, and the size of the reference transistor is smaller than that of the output transistor (i.e. see col. 4, lines 1-35).
In re to claim 2, MacLean disclose the load drive circuit (i.e. 200, fig. 2, see col. 3, lines 43-47) according to claim 1, wherein the reference transistor has similar characteristics to the output transistor (i.e. the reference transistor 222 and the output transistor are n-channel/NMOS transistors, see fig. 2).
In re to claims 3-6, MacLean disclose the load drive circuit (i.e. 200, fig. 2, see col. 3, lines 43-47) according to claim 1, wherein the soft start reference block (i.e. 210) applies a soft start voltage between the gate and the source of the output transistor (i.e. 236) by making a current corresponding to the gate-source voltage of the reference transistor flow through a resistor arranged between the gate and the source of the output transistor (i.e. see col. 4, lines 4-35). wherein a predetermined period from when the output is started to be ON is a period until the gate-source voltage of the output transistor (i.e. 236) reaches a predetermined value after the output is ON (i.e. col. lines 42-47); further comprising a full-on control block that applies a full-on voltage between the gate and the source of the output transistor (i.e. 236) after a predetermined period has elapsed from when the output is started to be ON (i.e. see col. 4, lines 17-45); wherein the full-on control block applies a full-on voltage between the gate and the source of the output transistor (i.e. 236) by making a predetermined current flow through a resistor (i.e. RX) arranged between the gate and the source of the output transistor (i.e. 236, see fig. 2).
Remarks
The examiner has cited columns, line numbers, paragraph numbers, references, or
figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YEMANE MEHARI whose telephone number is (571)270-7603. The examiner can normally be reached M-F 9AM TO 6 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 5712701276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YEMANE MEHARI/Primary Examiner, Art Unit 2838
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