Prosecution Insights
Last updated: May 29, 2026
Application No. 18/884,635

MULTI-PHASE SIGNAL GENERATION

Non-Final OA §102§112
Filed
Sep 13, 2024
Priority
Aug 03, 2018 — continuation of 10/678,296 +3 more
Examiner
NGUYEN, PHIL K
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
Huawei Technologies Co., Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
446 granted / 541 resolved
+27.4% vs TC avg
Moderate +14% lift
Without
With
+14.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
20 currently pending
Career history
560
Total Applications
across all art units

Statute-Specific Performance

§101
3.2%
-36.8% vs TC avg
§103
69.7%
+29.7% vs TC avg
§102
20.4%
-19.6% vs TC avg
§112
2.2%
-37.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 541 resolved cases

Office Action

§102 §112
DETAILED ACTION Claims 1 – 20 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-18 of U.S. Patent 12124289 B2. Although the conflicting claims are not identical, they are not patentably distinct from each other because the claims are directed to substantially the same subject matter involving to switch a local oscillator between first mode and second mode to output either 2^n phase signal or 2^(n-1) phase signal. Instant Application 18884635 US Patent 12124289 B2 An apparatus comprising: a local oscillator comprising 2^n phase signal generation stages, the local oscillator configured to operate in a first mode and a second mode, wherein in the first mode the local oscillator outputs a 2^(n) phase signal and when in the second mode the local oscillator outputs a 2^(n-1) phase signal; a frequency mixer coupled to the local oscillator; and a controller coupled to the local oscillator; the controller configured to switch the local oscillator between the first mode and the second mode to transition between providing the 2^(n) phase signal and the 2^(n-1) phase signal from the local oscillator to the frequency mixer with a deterministic phase shift between the 2^(n) phase signal and the 2^(n-1) phase signal. A transmitter, comprising: a low pass filter, configured to receive and filter a signal produced by a digital to analog converter and to output the filtered signal to a mixer; a local oscillator comprising a clock generator and a phase generator circuit, wherein the clock generator is configured to provide a clock signal to the phase generator circuit, wherein the phase generator circuit is configured to output a 2^(n-1) phase oscillator signal and a 2^n phase oscillator signal oscillator signal to the mixer, the phase generator circuit comprising 2^n stages configured to generate the 2^n phase oscillator signal, the 2^n stages comprising 2^(n-1) stages configured to generate the 2^(n-1) phase oscillator signal, wherein n is an integer greater than 1; and wherein the phase generator circuit is coupled to the mixer through an electrical path that is configured to conduct both the 2^(n-1) phase oscillator signal and the 2^n phase oscillator signal, wherein the mixer is configured to receive the 2^(n-1) phase oscillator signal and the 2^n phase oscillator signal through overlapped input. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Regarding claims 1-20, these claims recite the limitation “configured to output a 2^(n-1) phase oscillator signal and a 2^n phase oscillator signal” renders the claim indefinite because “n” is not defined. For example, whether “n” is a whole number integer greater than 1. For the purpose of examination, Examiner interprets “n” is a whole number greater than 1. Regarding claims 2 and 16, these claims recite the limitation “approximately 0 degrees” renders the claims indefinite because “approximately” is a relative term and not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “approximately 0 degree” can broadly be interpreted as 1 degree or 10 degrees depending on the total magnitude or scale of the degree. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3,10-12, 15-17 and 20 are rejected under AIA 35 U.S.C. 102(a)(1) as being anticipated by Mirzaei1 (US Patent Application Publication 2014/0321576 A1). Regarding claim 1, Mirzaei discloses an apparatus [Figs. 3, 5- 8] comprising: a local oscillator comprising 2^n phase signal generation stages, the local oscillator configured to operate in a first mode and a second mode, wherein in the first mode the local oscillator outputs a 2^(n) phase signal and when in the second mode the local oscillator outputs a 2^(n-1) phase signal [0046: local oscillation clock signals generated by local oscillation module 274. Each LO clock signal waveform is shifted in phase and each corresponds to a respective phase in the clock cycle. By way of example, if the clock cycle include four clock phases, then each waveform is shifted in phase by 25% (or one-fourth of the clock cycle). Conversely, the number of LO clock signals is equivalent to the number of phases in the clock cycle. As such, a four-phase clock cycle would include four LO clock signals, each having a duty cycle that is one-fourth of the clock cycle.] [0047] [0079] [0080: the clock cycle can include eight phases (e.g., 12.5% duty cycle). As such, transmitter circuit 800 can be configured for beam-forming that utilizes the eight phases in the clock cycle] [0084]; a frequency mixer [mixer 282] coupled to the local oscillator; and a controller coupled to the local oscillator, the controller configured to switch the local oscillator between the first mode and the second mode to transition between providing the 2^(n) phase signal and the 2^(n-1) phase signal from the local oscillator to the frequency mixer with a deterministic phase shift between the 2^(n) phase signal and the 2^(n-1) phase signal [0046: Each LO clock signal waveform is shifted in phase and each corresponds to a respective phase in the clock cycle. By way of example, if the clock cycle include four clock phases, then each waveform is shifted in phase by 25% (or one-fourth of the clock cycle). Conversely, the number of LO clock signals is equivalent to the number of phases in the clock cycle. As such, a four-phase clock cycle would include four LO clock signals, each having a duty cycle that is one-fourth of the clock cycle.] [0047] [0079] [0080: the clock cycle can include eight phases (e.g., 12.5% duty cycle). As such, transmitter circuit 800 can be configured for beam-forming that utilizes the eight phases in the clock cycle] [0084]. Regarding claim 2, Mirzaei discloses the apparatus of claim 1, wherein the deterministic phase shift between the 2^(n) phase signal and the 2^(n-1) phase signal is approximately 0 degrees [0046-0047] [0079-0080] [phase shift between LO clock signals]. Regarding claim 3, Mirzaei discloses the apparatus of claim 1, wherein: the apparatus comprises a radio frequency (RF) transmitter, the RF transmitter comprising the frequency mixer; and the controller is further configured to transition between providing the 2^(n) phase signal and providing the 2^(n-1) phase signal from the local oscillator to the frequency mixer while the RF transmitter is transmitting a wireless RF signal [Figs. 3, 5- 8][RF transmitter with phase shifting]. Regarding claim 10, Mirzaei discloses the apparatus of claim 1, wherein the 2^(n) phase signal is an eight-phase signal and the 2^(n-1) phase signal is a four-phase signal [0046-0047] [0079-0080] [4 clock phases and 8 clock phases]. Regarding claim 11, this claim is rejected for the same reasons as set forth in claim 1. Regarding claim 12, Mirzaei discloses the method of claim 11, further comprising: transmitting, by a transmitter, a wireless signal while transitioning between providing the 2^(n) phase signal and providing the 2^(n-1) phase signal from the local oscillator to the frequency mixer, wherein the frequency mixer resides in the transmitter [0046-0047] [0079-0080] [4 clock phases and 8 clock phases] [mixer 282 inside transmitter]. Regarding claims 15-17 and 20, these claims are rejected for the same reasons as set forth in claims 1-3 and 10 above. Allowable Subject Matter Claims 4-9, 13-14,18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if (1) overcome 112(b) rejection above and (2) rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior arts of record do not disclose nor suggest the limitations recited in claims 4-9, 13-14,18-19. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PHIL K NGUYEN/Primary Examiner, Art Unit 2176 1 Mirzaei is cited in the IDS.
Read full office action

Prosecution Timeline

Sep 13, 2024
Application Filed
Feb 13, 2026
Non-Final Rejection mailed — §102, §112
May 13, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
96%
With Interview (+14.0%)
2y 8m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 541 resolved cases by this examiner. Grant probability derived from career allowance rate.

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