DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-9 are pending for examination.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) are: “a first monitor configured to” in claims 3, 6 and 8, and “a second monitor configured to” in claims 4, 6 and 8.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Claim limitations “a first monitor” in claims 3, 6 and 8, and “a second monitor” in claims 4, 6 and 8 invokes 35 U.S.C. 112(f). The specification paragraph [0111] that discloses “The arithmetic device 1 includes an operation core number adjustment unit 34, the monitor 11, and the monitor 23 in addition to the plurality of arithmetic units 10” and [0132] of the specification discloses “The operation core number adjustment unit 34 obtains a usage rate UCij of each Corei,j from the monitor 11 of each Corei,j”. However, said “a first monitor” and “a second monitor” without the detail about the means to accomplish the functions are not an adequate disclosure of corresponding structure. MPEP § 2181(II)(B) specifically indicated that “For a computer-implemented 35 U.S.C. 112(f) claim limitation, the specification must disclose an algorithm for performing the claimed specific computer function, or else the claim is indefinite under 35 U.S.C. 112(b). See Net MoneyIN, Inc. v. Verisign. Inc., 545 F.3d 1359, 1367, 88 USPQ2d 1751, 1757 (Fed. Cir. 2008). See also In re Aoyama, 656 F.3d 1293, 1297, 99 USPQ2d 1936, 1939 (Fed. Cir. 2011) ("[W]hen the disclosed structure is a computer programmed to carry out an algorithm, ‘the disclosed structure is not the general purpose computer, but rather that special purpose computer programmed to perform the disclosed algorithm.’") (quoting WMS Gaming, Inc. v. Int’l Game Tech., 184 F.3d 1339, 1349, 51 USPQ2d 1385, 1391 (Fed. Cir. 1999))” and “The corresponding structure is not simply a general purpose computer by itself but the special purpose computer as programmed to perform the disclosed algorithm. Aristocrat, 521 F.3d at 1333, 86 USPQ2d at 1239. Thus, the specification must sufficiently disclose an algorithm to transform a general purpose microprocessor to the special purpose computer” Therefore, the claims (i.e., 3-8) are indefinite and is rejected under 35 U.S.C. 112(b).
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f);
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3-8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement.
The claims 3-4, 6 and 8 contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. As described above in 112(f) (i.e., first and second monitors), the disclosure does not provide adequate structure to perform the claimed functions. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. See MPEP § 2181(II)(B) “When a claim containing a computer-implemented 35 U.S.C. 112(f) claim limitation is found to be indefinite under 35 U.S.C. 112(b) for failure to disclose sufficient corresponding structure (e.g., the computer and the algorithm) in the specification that performs the entire claimed function, it will also lack written description under 35 U.S.C. 112(a)”.
Claims 5 and 7, they are depend on claims 4 and 6 and do not overcome the deficiencies thereof, therefore they are rejected for the same reason as claims 4 and 6 above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 3-8 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
As per claims 3-8:
As described above in 112(f) (i.e., “a first monitor” in claims 3, 6 and 8, and “a second monitor” in claims 4, 6 and 8 without the detail about the means to accomplish the functions are not an adequate disclosure of corresponding structure. The MPEP § 2181(II)(B) specifically indicated that “For a computer-implemented 35 U.S.C. 112(f) claim limitation, the specification must disclose an algorithm for performing the claimed specific computer function, or else the claim is indefinite under 35 U.S.C. 112(b). See Net MoneyIN, Inc. v. Verisign. Inc., 545 F.3d 1359, 1367, 88 USPQ2d 1751, 1757 (Fed. Cir. 2008). See also In re Aoyama, 656 F.3d 1293, 1297, 99 USPQ2d 1936, 1939 (Fed. Cir. 2011) ("[W]hen the disclosed structure is a computer programmed to carry out an algorithm, ‘the disclosed structure is not the general purpose computer, but rather that special purpose computer programmed to perform the disclosed algorithm.’") (quoting WMS Gaming, Inc. v. Int’l Game Tech., 184 F.3d 1339, 1349, 51 USPQ2d 1385, 1391 (Fed. Cir. 1999))”. Therefore, the claims (i.e., 3-8) are indefinite and is rejected under 35 U.S.C. 112(b).
As per claims 5 and 7:
They are depend on claims 4 and 6 and do not overcome the deficiencies thereof, therefore they are rejected for the same reason as claims 4 and 6 above.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Teig et al. (US Pub. 2019/0123023 A1) in view of Garg et al. (US Pub. 2004/0059875 A1) and further in view of Baskaran et al. (US Pub. 2015/0309779 A1).
As per claim 1, Teig teaches the invention substantially as claimed including A cache memory equipped arithmetic device comprising (Teig, Fig. 7, 700):
a first semiconductor die configured to include a plurality of arithmetic circuits (Teig, [0085] FIG. 7 illustrates yet another 3D processor 700 of some embodiments. This processor 700 is identical to the processor 600 of FIG. 6, except that it only has two layers of caches, L1 and L2, on a second die 710 that is face-to-face mounted on a first die 705 that has eight processor cores 722. (as a plurality of arithmetic circuits) As shown, each L1 cache 726 overlaps just one core 722. Unlike the L1 caches 726, the L2 cache 728 is shared among all the cores 722 and overlaps each of the cores 722. In some embodiments, each core connects to each L1 or L2 cache that it overlaps through (1) numerous z-axis DBI connections that connect the top interconnect layers of the dies 705 and 721);
a second semiconductor die stacked over the first semiconductor die, and configured to include a plurality of cache memories, a cache memory of the plurality of cache memories forming a pair with an arithmetic circuit of the plurality of arithmetic circuits (Teig, Fig. 7, 700, 615, 620, 710, 705; [0085] FIG. 7 illustrates yet another 3D processor 700 of some embodiments. This processor 700 is identical to the processor 600 of FIG. 6, except that it only has two layers of caches, L1 and L2, on a second die 710 that is face-to-face mounted on a first die 705 that has eight processor cores 722. As shown, each L1 cache 726 overlaps just one core 722. Unlike the L1 caches 726, the L2 cache 728 is shared among all the cores 722 and overlaps each of the cores 722. In some embodiments, each core connects to each L1 or L2 cache that it overlaps through (1) numerous z-axis DBI connections that connect the top interconnect layers of the dies 705 and 721, and (2) the interconnects and vias that carry the signals from these DBI connections to other metal and substrate layers of the dies 705 and 710. The DBI connections in some embodiments allow the data buses between the caches and the cores to be much wider and faster than traditional data buses between the caches and the cores); and
wherein the arithmetic circuit and the cache memory, which form the pair, at least partially overlap each other in plan view (Teig, [0085] FIG. 7 illustrates yet another 3D processor 700 of some embodiments. This processor 700 is identical to the processor 600 of FIG. 6, except that it only has two layers of caches, L1 and L2, on a second die 710 that is face-to-face mounted on a first die 705 that has eight processor cores 722. As shown, each L1 cache 726 overlaps just one core 722…each core connects to each L1 or L2 cache that it overlaps through (1) numerous z-axis DBI connections that connect the top interconnect layers of the dies 705 and 721, and (2) the interconnects and vias that carry the signals from these DBI connections to other metal and substrate layers of the dies 705 and 710. The DBI connections in some embodiments allow the data buses between the caches and the cores to be much wider and faster than traditional data buses between the caches and the cores).
Teig fails to specifically teach an operation management circuit configured to manage operation of the first semiconductor die and the second semiconductor die, and wherein the operation management circuit selectively operates one of the arithmetic circuit and the cache memory paired with the arithmetic circuit, based on arithmetic intensity needed for the plurality of arithmetic circuits.
However, Garg teaches an operation management circuit configured to manage operation of the first semiconductor die and the second semiconductor die (Garg, [0041] FIG. 5 illustrates one embodiment of a cache sharing mechanism that includes configurable or dynamically adjustable power and replacement mode mechanisms. The embodiment of FIG. 5 may implement any of the various partitioning or operating modes described above. In general, global control logic 550 (as an operation management circuit) is coupled to both caches 510-1 and 510-2 via respectively cache controllers 520-1 and 520-2. The control logic 550 provides access cycles to the cache 510-1 and 510-2 via respectively signal lines 544 and 542. Therefore, the control logic 550 may perform a selection function to select which one or both of the caches 510-1 and 510-2 should receive access cycles; [0042] the control logic 550 includes power mode logic 552 and replacement mode logic 554. The power mode logic 552 may select one of the four operating modes described above with respect to Table 1. In some embodiments, a subset or a superset of these modes may be implemented by the power mode logic 552. The power mode logic 552 may choose the power mode based on measured temperature, operating system inputs, utilization measurements, user input, power consumption measurements, etc. The power mode logic 552 generates various enable signals to enable or disable the various cores and caches according to the mode selected; please note: first semiconductor die and the second semiconductor die was taught by Teig);
wherein the operation management circuit selectively operates one of the arithmetic circuit and the cache memory paired with the arithmetic circuit (Garg, [0028] With respect to overall operating modes, the modes shown in Table 1 may be used for various embodiments. 1TABLE 1 Operating Modes Mode Description Power Performance 1 Both cores and L2 caches available and High High operating individually 2 One core and both L2 caches available Medium Medium 3 One core and one L2 cache available Low Low 4 Both cores share both L2 caches High Higher; [0029] In the first operating mode, both cores operate with each core using its own cache as a dedicated private cache. In the second mode, one core is disabled, and the other core is allowed to take advantage of the cache of the disabled core. In this mode, a first type of sharing occurs wherein the cache of a disable processor is shared with an active processor such that the active processor has additional cache capacity available. In the embodiment of FIG. 2a, the cache of the second processor is used to increase the total number of cache sets available to the active processor. Therefore, the selectors 230 and 232 use an Nth bit of the address (or the tag) to determine which cache to access. [0042] the control logic 550 includes power mode logic 552 and replacement mode logic 554. The power mode logic 552 may select one of the four operating modes described above with respect to Table 1. In some embodiments, a subset or a superset of these modes may be implemented by the power mode logic 552. The power mode logic 552 may choose the power mode based on measured temperature, operating system inputs, utilization measurements, user input, power consumption measurements, etc. The power mode logic 552 generates various enable signals to enable or disable the various cores and caches according to the mode selected).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Teig with Garg because Garg’s teaching of control mechanism that allow sharing between caches that are associated with individual processor cores would have provided Teig’s system with the advantage and capability to allow the system to easily selecting the different operation mode to meet particular performance or power consumption constraints which improving the system resource efficiency and performance. (see Garg [0018]).
Teig and Garg fail to specifically teach when selectively operates, it is based on arithmetic intensity needed for the plurality of arithmetic circuits.
However, Baskaran teaches when selectively operates, it is based on arithmetic intensity needed for the plurality of arithmetic circuits (Baskaran, [0052] EWC performs two tasks: (1) creates regions of code called “energy windows” and inserts “power control operations” for each window and (2) statically characterizes the identified region or energy window to evaluate “power control metrics.” The total number of loads and stores and the total number of compute operations within the energy window may be collected statically to calculate the “arithmetic intensity” (a function of computation to memory load/store) of the window and use it as the power control metric. The total number of memory and compute operations can be either completely determined statically or may be abstracted statically to be evaluated quickly at runtime. The power control operations are operations applied at runtime to set one or more parameters (e.g., voltage, frequency, switched ON, switched OFF, etc.) of key system components to appropriate levels for energy optimization; [0055] the shape and size of the region is statically analyzed with polyhedral machinery to identify the volume of operations (loads, stores, and compute operations) within the region. If the size of the region is parameterized with runtime program parameters, the total number of memory and compute operations can be represented as an affine expression of the parameters that can be quickly evaluated at runtime to calculate the actual value. If the size is statically known, the total number of memory and compute operations is statically calculated. We calculate the arithmetic intensity A of a window from the number of memory and compute operations. We classify a window as compute bound (CPU bound) or memory bound depending on its arithmetic intensity A and a statically defined platform-specific i.e., based on one or more characteristics of a data processing system to be used for executing the program, threshold value T.sub.A. Windows with A≧T.sub.A are generally called CPU bound, while windows with A<T.sub.A are memory bound; also see [0056]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Teig and Garg with Baskaran because Baskaran’s teaching of inserts power control operations for each window based on arithmetic intensity would have provided Teig and Garg’s system with the advantage and capability to allow the system to easily managing the power and energy consumption which optimizing the resource utilization and improving system efficiency (see Baskaran [0052]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Teig, Garg and Baskaran, as applied to claim 1 above, and further in view of Hetherington et al. (US Pub. 2006/0004942 A1).
As per claim 2, Teig, Garg and Baskaran teach the invention according to claim 1 above. Garg teaches wherein the operation management circuit determines one of the arithmetic circuit and the cache memory to be operated in the pair of a plurality of pairs (Garg, [0028] With respect to overall operating modes, the modes shown in Table 1 may be used for various embodiments. 1TABLE 1 Operating Modes Mode Description Power Performance 1 Both cores and L2 caches available and High High operating individually 2 One core and both L2 caches available Medium Medium 3 One core and one L2 cache available Low Low 4 Both cores share both L2 caches High Higher; [0029] In the first operating mode, both cores operate with each core using its own cache as a dedicated private cache. In the second mode, one core is disabled, and the other core is allowed to take advantage of the cache of the disabled core. In this mode, a first type of sharing occurs wherein the cache of a disable processor is shared with an active processor such that the active processor has additional cache capacity available. In the embodiment of FIG. 2a, the cache of the second processor is used to increase the total number of cache sets available to the active processor. Therefore, the selectors 230 and 232 use an Nth bit of the address (or the tag) to determine which cache to access. [0042] the control logic 550 includes power mode logic 552 and replacement mode logic 554. The power mode logic 552 may select one of the four operating modes described above with respect to Table 1. In some embodiments, a subset or a superset of these modes may be implemented by the power mode logic 552. The power mode logic 552 may choose the power mode based on measured temperature, operating system inputs, utilization measurements, user input, power consumption measurements, etc. The power mode logic 552 generates various enable signals to enable or disable the various cores and caches according to the mode selected).
Teig, Garg and Baskaran fail to specifically teach when determining, it is based on a list for specifying, in advance, one of the arithmetic circuit and the cache memory to be operated.
However, Hetherington teaches when determining, it is based on a list for specifying, in advance, one of the arithmetic circuit and the cache memory to be operated (Hetherington, [0076] At some point as the boot-up routine progresses, configuration register 175 may be read (block 702) to determine which processor cores 100 and banks 125 of L2 cache 120 are available for use. With the information read from configuration register 175, an indication or `map` of usable hardware may be created (block 704). In one embodiment, such a map may include a representation in bits or bytes of data of the effectively operable and inoperable functional units of processor 10, as indicated by configuration register 175. For example, in an embodiment of processor 10 including 8 L2 cache banks 125 and 8 processor cores 100, the map may include respective bytes (i.e., 8 bits) corresponding to cache banks and processor cores, where an asserted bit in a byte of the map indicates that a corresponding cache bank 125 or processor core 100 is enabled for operation. The map may then be provided to operating system software (block 706). The operating system may use the map to determine which processor cores 100 are enabled and therefore may be provided with instructions. In some embodiments, the operating system may also use the map to determine which banks 125 of L2 cache 120 may be used for storage, although in other embodiments the management of enabled and disabled banks 125 may be performed transparently to an operating system by core/bank mapping logic 115 as described below; also see [0066] to [0068] and [0077]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Teig, Garg and Baskaran with Hetherington because Hetherington’s teaching of providing a map that include respective bytes corresponding to cache banks and processor cores with an asserted bit in a byte of the map indicates that a corresponding cache bank or processor core is enabled for operation would have provided Teig, Garg and Baskaran’s system with the advantage and capability to allow the system to easily determining and identifying which cache banks and corresponding processor cores are enabled for operation which improving the system performance and efficiency.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Teig, Garg and Baskaran, as applied to claim 1 above, and further in view of Min (US Pub. 2018/0088997 A1).
As per claim 3, Teig, Garg and Baskaran teach the invention according to claim 1 above. Garg teaches wherein the operation management circuit selectively operates one of the arithmetic circuit and the cache memory paired with each other (Garg, [0028] With respect to overall operating modes, the modes shown in Table 1 may be used for various embodiments. 1TABLE 1 Operating Modes Mode Description Power Performance 1 Both cores and L2 caches available and High High operating individually 2 One core and both L2 caches available Medium Medium 3 One core and one L2 cache available Low Low 4 Both cores share both L2 caches High Higher; [0029] In the first operating mode, both cores operate with each core using its own cache as a dedicated private cache. In the second mode, one core is disabled, and the other core is allowed to take advantage of the cache of the disabled core. In this mode, a first type of sharing occurs wherein the cache of a disable processor is shared with an active processor such that the active processor has additional cache capacity available. In the embodiment of FIG. 2a, the cache of the second processor is used to increase the total number of cache sets available to the active processor. Therefore, the selectors 230 and 232 use an Nth bit of the address (or the tag) to determine which cache to access. [0042] the control logic 550 includes power mode logic 552 and replacement mode logic 554. The power mode logic 552 may select one of the four operating modes described above with respect to Table 1. In some embodiments, a subset or a superset of these modes may be implemented by the power mode logic 552. The power mode logic 552 may choose the power mode based on measured temperature, operating system inputs, utilization measurements, user input, power consumption measurements, etc. The power mode logic 552 generates various enable signals to enable or disable the various cores and caches according to the mode selected).
Teig, Garg and Baskaran fail to specifically teach a first monitor configured to obtain first information regarding a usage rate of at least one of the plurality of arithmetic circuits, when selectively operates, it is according to the first information.
However, Min teaches a first monitor configured to obtain first information regarding a usage rate of at least one of the plurality of arithmetic circuits (Min, [0042] The virtual machine manager 102 includes resource monitoring circuitry 250 communicably coupled to the one or more CPUs 110, the one or more physical cores 114, and/or the one or more caches 116. The resource monitoring circuitry 250 collects and communicates information and/or data representative of some or all CPU 110 physical resource parameters, such as core utilization, core temperature, core frequency, cache utilization, cache turnover, cache access time, etc., to the resource allocation determination circuitry 260 via one or more signals 252. In some implementations, the resource monitoring circuitry 250 may additionally or alternatively communicate information and/or data representative of some or all CPU 110 physical resource parameters, such as core utilization, core temperature, core frequency, cache utilization, cache turnover, cache access time, etc. to the resource allocation determination circuitry 260 via one or more signals 252; also see [0055] and [0056]).
when selectively operates, it is according to the first information (Min, [0055] The storage device 280 may include threshold data used by the virtual machine manager 102 in making the determination to consolidate physical cores 114 and/or caches 116 based at least in part on virtual CPU 122 utilization information and/or data received by the performance monitoring circuitry 230, physical core utilization information and/or data received by the resource monitoring circuitry 250, and/or physical cache utilization information and/or data received by the resource monitoring circuitry 250. Such threshold information may be used, in whole or in part, by the virtual machine manager 102 in making the decision to consolidate physical CPU cores 114 and/or physical caches 116).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Teig, Garg and Baskaran with Min because Min’s teaching of consolidating physical cores and caches based at least in part on virtual CPU utilization would have provided Teig, Garg and Baskaran’s system with the advantage and capability to allow the system to easily selecting/consolidating different pairs of the CPU and caches for operation based on CPU utilization which reducing the possibility of cache pollution, cache conflicts, and potential data loss or questionable data integrity within the physical caches (see Min [0031]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Teig, Garg, Baskaran and Min, as applied to claim 3 above, and further in view of PARK et al. (US Pub. 2016/0203083 A1).
As per claim 4, Teig, Garg, Baskaran and Min teach the invention according to claim 3 above. Garg teaches wherein the operation management circuit selectively operates one of the arithmetic circuit and the cache memory paired with each other (Garg, [0028] With respect to overall operating modes, the modes shown in Table 1 may be used for various embodiments. 1TABLE 1 Operating Modes Mode Description Power Performance 1 Both cores and L2 caches available and High High operating individually 2 One core and both L2 caches available Medium Medium 3 One core and one L2 cache available Low Low 4 Both cores share both L2 caches High Higher; [0029] In the first operating mode, both cores operate with each core using its own cache as a dedicated private cache. In the second mode, one core is disabled, and the other core is allowed to take advantage of the cache of the disabled core. In this mode, a first type of sharing occurs wherein the cache of a disable processor is shared with an active processor such that the active processor has additional cache capacity available. In the embodiment of FIG. 2a, the cache of the second processor is used to increase the total number of cache sets available to the active processor. Therefore, the selectors 230 and 232 use an Nth bit of the address (or the tag) to determine which cache to access. [0042] the control logic 550 includes power mode logic 552 and replacement mode logic 554. The power mode logic 552 may select one of the four operating modes described above with respect to Table 1. In some embodiments, a subset or a superset of these modes may be implemented by the power mode logic 552. The power mode logic 552 may choose the power mode based on measured temperature, operating system inputs, utilization measurements, user input, power consumption measurements, etc. The power mode logic 552 generates various enable signals to enable or disable the various cores and caches according to the mode selected).
In addition, Min teaches a second monitor configured to obtain second information regarding a usage rate of at least one of the plurality of cache memories, when selectively operates, it is according to between the first information and the second information (Min, [0042] The virtual machine manager 102 includes resource monitoring circuitry 250 communicably coupled to the one or more CPUs 110, the one or more physical cores 114, and/or the one or more caches 116. The resource monitoring circuitry 250 collects and communicates information and/or data representative of some or all CPU 110 physical resource parameters, such as core utilization, core temperature, core frequency, cache utilization, cache turnover, cache access time, etc., to the resource allocation determination circuitry 260 via one or more signals 252. In some implementations, the resource monitoring circuitry 250 may additionally or alternatively communicate information and/or data representative of some or all CPU 110 physical resource parameters, such as core utilization, core temperature, core frequency, cache utilization, cache turnover, cache access time, etc. to the resource allocation determination circuitry 260 via one or more signals 252. [0043] The resource monitoring circuitry 250 may include any number and/or combination of any currently available or future developed electronic devices and/or semiconductor components capable of monitoring one or more performance aspects and/or parameters of the CPUs 110, the physical cores 114, and/or the caches 116; [0055] storage device 280 may include threshold data used by the virtual machine manager 102 in making the determination to consolidate physical cores 114 and/or caches 116 based at least in part on virtual CPU 122 utilization information and/or data received by the performance monitoring circuitry 230, physical core utilization information and/or data received by the resource monitoring circuitry 250, and/or physical cache utilization information and/or data received by the resource monitoring circuitry 250. Such threshold information may be used, in whole or in part, by the virtual machine manager 102 in making the decision to consolidate physical CPU cores 114 and/or physical caches 116; also see [0056]).
Teig, Garg, Baskaran and Min fail to specifically teach when selectively operates, it is according to a result of comparison between the first information and the second information.
However, PARK teaches when selectively operates, it is according to a result of comparison between the first information and the second information (PARK, [0028] As illustrated in FIG. 1, the cache controller 101 may comprise a cache scheduler 140, a cache interconnect 111, and a plurality of cache monitors 126, 128, and 130 for monitoring the performance of L2 cache 112, 118, and 124, respectively. Cache interconnect 111 comprises an interconnect or bus with associated logic for maintaining coherency between main memory 144 and L2 cache 112, 118, and 124. As described below in more detail, the cache scheduler 140 generally comprises logic configured to monitor processor and cache performance and optimally manage task scheduling to the processor clusters 101, 104, and 106 according to power and performance requirements of the system 100; [0029] FIG. 2 is a block diagram illustrating the data inputs and outputs of an embodiment of the cache scheduler 140. The cache scheduler 140 may receive as data inputs, from each processor cluster, processor usage input data 202 and L2 cache usage/miss rate input data 204. It should be appreciated that processor usage input data 202 may indicate processor workload based on one or more of the following or other parameters received from processor clusters 102, 104, and 106: instructions per cycle (IPC), million instructions per second (MIPS), frequency, CPU active duration percentage. L2 cache input data 204 may indicate L2 cache workload or performance based on one or more of the following or other parameters received via cache monitors 126, 128, and 130: cache misses per 1000 instructions (MPKI), cache accesses per 1000 instructions (APKI), L2 cache miss rate (MPKI/APKI), CPU stall time/ratio or stall clocks due to cache misses, and million cycles per second (MCPS) indicating an amount of CPU stalls due to cache misses (as for result of comparison); [0030] Based on the input data 202 and 204, the cache scheduler 140 determines whether a processing bottleneck or other system limitation is being (or will be) caused by (1) processor/CPU performance or (2) the size of the L2 cache. For example, the cache scheduler 140 may determine that a current task associated with the Little processor cluster 102 is limited by CPU performance… If there are no performance issues with the current task, then the cache scheduler 140 may initiate a default split L2 mode 210 for keeping the current task with L2 cache 112 of the Little processor cluster).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Teig, Garg, Baskaran and Min with PARK because PARK’s teaching of determining the result of the comparison between CPU and cache utilization would have provided Teig, Garg, Baskaran and Min’s system with the advantage and capability to allow the system to easily identifying the processing bottleneck or other system limitation in order to adjusting the operations which improving the system performance and efficiency.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Teig, Garg, Baskaran, Min and PARK, as applied to claim 4 above, and further in view of Tang et al. (US Pub. 2014/0201357 A1).
As per claim 8, Teig, Garg, Baskaran, Min and PARK teach the invention according to claim 4 above. Min teaches wherein the first monitor and the second monitor obtain the first information and the second information (Min, [0042] The virtual machine manager 102 includes resource monitoring circuitry 250 communicably coupled to the one or more CPUs 110, the one or more physical cores 114, and/or the one or more caches 116. The resource monitoring circuitry 250 collects and communicates information and/or data representative of some or all CPU 110 physical resource parameters, such as core utilization, core temperature, core frequency, cache utilization, cache turnover, cache access time, etc., to the resource allocation determination circuitry 260 via one or more signals 252. In some implementations, the resource monitoring circuitry 250 may additionally or alternatively communicate information and/or data representative of some or all CPU 110 physical resource parameters, such as core utilization, core temperature, core frequency, cache utilization, cache turnover, cache access time, etc. to the resource allocation determination circuitry 260 via one or more signals 252. [0043] The resource monitoring circuitry 250 may include any number and/or combination of any currently available or future developed electronic devices and/or semiconductor components capable of monitoring one or more performance aspects and/or parameters of the CPUs 110, the physical cores 114, and/or the caches 116).
Teig, Garg, Baskaran, Min and PARK fail to specifically teach obtain the first information and the second information at a predetermined time interval during arithmetic processing executed by any of the plurality of arithmetic circuits.
However, Tang teaches obtain the first information and the second information at a predetermined time interval during arithmetic processing executed by any of the plurality of arithmetic circuits (Tang, [0005] Two kinds of registers help monitoring performance: performance control register (PMC) and performance data register (PMD). PMC monitors CPU at regular time intervals, and saves monitored data into PMD. PMC is event-based or time-based to consolidate the collected event information and report the monitoring results to higher software layers. Advantages of hardware monitoring are: (1) in the past, certain software-based monitors require to continuously change the source code of the monitored software to reach its goal, e.g. optimizing a Java virtual machine routine. On the contrary, hardware-based monitoring requires no source code. (2) The performance of monitored software is not affected by monitoring activities; [0155] (1) Host user space monitoring primarily monitors the processes running in the host user space. For example, the PMU base tool helps to acquire for each process, the CPU usage data, cache usage data, and TLB miss data; [0158] System external resource monitor 105 acquires data by soliciting two relative performance data and subtracting them at certain time interval, based on performance monitor base tool; the flow of system external resource monitor 105 is as follows).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Teig, Garg, Baskaran, Min and PARK with Tang because Tang’s teaching of obtaining the CPU usage data, cache usage data by monitoring the processes running in the host user space would have provided Teig, Garg, Baskaran, Min and PARK’s system with the advantage and capability to allow the system to easily identifying the current resource utilization and usage for the CPU and caches which improving the system resource utilization and efficiency.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Teig, Garg and Baskaran, as applied to claim 1 above, and further in view of BRONSON et al. (US Pub. 2011/0320729 A1).
As per claim 9, Teig, Garg and Baskaran teach the invention according to claim 1 above. Teig, Garg and Baskaran fail to specifically teach wherein the plurality of cache memories operates as one cache memory as a whole.
However, BRONSON teaches wherein the plurality of cache memories operates as one cache memory as a whole (BRONSON, Fig. 2, 214 and 216; [0028] Each of the processors 202, 204, 206, 208, 201, 212 is communicatively coupled to one or more lower level caches 214, 216 such as an L4 cache, which in one embodiment is an EDRAM cache. Each lower level cache 214, 216 is communicatively coupled to the communication fabrics 110, 112, 114 associated with that node as shown in FIG. 1. It should be noted that even though two lower level caches 214, 216 are shown these two lower level caches 214, 216, in one embodiment, are logically a single cache).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Teig, Garg and Baskaran with BRONSON because BRONSON’s teaching of two lower level caches are logically a single cache would have provided Teig, Garg and Baskaran’s system with the advantage and capability to allow the system to easily managing the caches and reduce key collisions which improving the system performance and efficiency.
Allowable Subject Matter
Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if overcomes the rejections under 35 U.S.C. 112 and rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons of Allowable Subject Matter:
The closest prior arts of record Teig et al. (US Pub. 2019/0123023 A1) teaches a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap which allowing more transistors to be defined in an IC chip.
Garg et al. (US Pub. 2004/0059875 A1) teaches a cache sharing for a chip multiprocessor that includes multiple processor cores, each having an associated cache. In addition, a control mechanism is provided to allow sharing between caches that are associated with individual processor cores.
Baskaran et al. (US Pub. 2015/0309779 A1) teaches a mechanism that adjusting power/energy consumption of the data processor, so as to minimize the overall power/energy consumption of the data processor during the execution of the program based on the arithmetic intensity.
Min (US Pub. 2018/0088997 A1) teaches a computing system that provide power management circuitry that factors one or more cache parameters (e.g., cache utilization) of an application or VM when determining pCPU-vCPU core remapping. By considering a more robust mix of both processor and cache memory related parameters, system performance and stability are increased by improving CPU and cache utilization and efficiency while reducing cache related issues such as collisions and/or pollution.
PARK et al. (US Pub. 2016/0203083 A1) teaches a dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.
The feature “wherein the operation management circuit controls a ratio of the arithmetic circuit to be operated among the plurality of arithmetic circuits in the pair of a plurality of pairs according to the result of comparison between the first information and the second information.”, “wherein the first monitor and the second monitor obtain the first information and the second information, respectively, in first arithmetic processing executed by any of the plurality of arithmetic circuits, and wherein the operation management circuit selectively operates one the arithmetic circuit and the cache memory according to the result of comparison between the first information and the second information in second arithmetic processing executed by any of the plurality of arithmetic circuits after the first arithmetic processing” and “wherein the second arithmetic processing includes arithmetic processing to be processed, and wherein the first arithmetic processing includes arithmetic processing for adjustment that is executed prior to the second arithmetic processing and includes a smaller number of commands than a number of commands in the second arithmetic processing” when taken in the context of the claims as a whole, were not found in the prior art teachings.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZUJIA XU whose telephone number is (571)272-0954. The examiner can normally be reached M-F 9:30-5:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee J Li can be reached at (571) 272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZUJIA XU/Primary Examiner, Art Unit 2195
Prosecution Insights