DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/13/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-24 of U.S. Patent No. 12,111,779. Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter in the instant application is at least fully disclosed in the reference patent.
Claim 1 of the instant application is anticipated by the patent’s claims 1 and 7 in that claims 1 and 7 of the patent contain all the limitation of claim 1 of the instant application. Please see the table below for the claim comparison.
Further, the limitation of claims 2-20 are found with minor variations in the teaching of the patent claims 1-24.
Instant Application (18/884,934)
Patent No. 12,111,779
Claim 1: A system comprising:
a plurality of tiles arranged in a configurable topology, wherein a first tile of the plurality of tiles comprises:
Claim 1: A system comprising:
an array of functional units connected via a mesh network;
a first functional unit in the array of function units comprising:
a memory; and
one or more processing devices operatively coupled with the memory, the one or more processing devices to:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
receive a first message comprising a coordinate identifier of a target tile of the plurality of tiles, the coordinate identifier representing a location of the target tile in the configurable topology;
transmitting, over the mesh network to a second functional unit in the array of functional units, a message comprising a node identifier of a target functional unit; and
update a configuration value associated with the target tile based on the coordinate identifier; and
loading configuration registers of the second functional unit with the node identifier of the target functional unit responsive to receiving the message, wherein the node identifier comprises a first coordinate identifier and a second coordinate identifier identifying a location of the target functional unit in the array of functional units.
transmit a second message to the target tile based on the configuration value.
Claim 7: transmitting the configuration information and the one or more messages to the second functional unit over the mesh network.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, the claim recites “transmit a message to the target device based on the configuration information and the coordinate identifier”. There is insufficient antecedent basis for “the configuration information” in the claim.
Other claims are rejected because they are dependent of the rejected claim above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-11 and 13-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Olofsson publication US 20100111088.
Regarding claim 1, Olofsson teaches a system (see figure 1A) comprising:
a plurality of tiles arranged in a configurable topology (see the abstract, a mesh network has a plurality of nodes that can be arranged in a two- or three-dimensional arrangement), wherein a first tile of the plurality of tiles comprises:
a memory; and one or more processing devices operatively coupled with the memory (see para 0031, each processing node has a processing element (PE) 140 and an interface (IF) (150). The processing element could be a software programmable processor, a hardware accelerator, or a piece of memory), the one or more processing devices to:
receive a first message comprising a coordinate identifier of a target tile of the plurality of tiles, the coordinate identifier representing a location of the target tile in the configurable topology (see para 0031, The processing element is able to send and receive mesh transactions that are compatible with the mesh network. A mesh transaction is a single cycle transaction and includes in the case of a read transaction, a read indicator, a source address, and a destination address.);
update a configuration value associated with the target tile based on the coordinate identifier (see para 0031, The coordinates of the node initiating a read transaction are sent along with the read transaction to fetch the data. When the data is fetched, the read transaction is turned into a write transaction and the original source coordinates are used as a destination address e.g. updating the destination address value based on the source address value); and
transmit a second message to the target tile based on the configuration value (see para 0031, a write transaction and the original source coordinates are used as a destination address to be sent along with the data).
Regarding claim 2, Olofsson further teaches the coordinate identifier comprises an x-coordinate of the target tile in the configurable topology and a y-coordinate of the target tile in the configurable topology (see para 0012, The circuit uses a 3D grid of elements addressable by dedicated X, Y, and Z coordinate fields within the transaction address).
Regarding claim 3, Olofsson further teaches retrieve from the memory, configuration information pertaining to the configurable topology of the plurality of tiles, wherein the second message is transmitted to the target tile based on the configuration value and the configuration information (see para 0040, the preference of horizontal versus vertical routing is determined based on a random bit in the router node configuration register. The random bit is updated on every clock cycle, but can be read from and written to using a memory mapped transaction).
Regarding claim 4, Olofsson further teaches the configuration information comprises one or more of product information associated with the configurable topology of the plurality of tiles, or revision information associated with the configurable topology of the plurality of tiles (see para 0040, the routing algorithm is configurable by the user through writing to a memory mapped mesh control register 430 contained within each processing node e.g. routing algorithm is construed as a product/revision information).
Regarding claim 5, Olofsson further teaches the configuration information comprises one or more of a payload, a target type identifier, an information type identifier, a linear identifier, or a protocol identifier (see para 0040, the routing scheme can be configured as fixed, adaptable, or random e.g. type and/or protocol identifier).
Regarding claim 6, Olofsson further teaches the first message further comprises configuration information pertaining to the target tile (see para 0031, a mesh transaction is a single cycle transaction and includes in the case of a read transaction, a read indicator, a source address, and a destination address), the one or more processing devices further to: store the configuration information pertaining to the configurable topology of the plurality of tiles in the memory, wherein the second message is transmitted to the target tile based on the configuration value and the configuration information (see para 0037, an output buffer 320 registers the data before sending in onwards to the next mesh node).
Regarding claim 8, Olofsson teaches a device (see figure 1A, processing node 140) comprising:
a memory (see para 0031, each processing node has a processing element (PE) 140 and an interface (IF) (150). The processing element could be a software programmable processor, a hardware accelerator, or a piece of memory);
a register (see para 0050, transaction registers 910, 920); and
one or more processing devices operatively coupled with the memory and the register (see para 0031 e.g. the processor of node 140), the one or more processing devices to:
retrieve from the memory, a coordinate identifier of a target device of a plurality of devices, the coordinate identifier representing a location of the target device in a configurable topology of the plurality of devices (see para 0031, The processing element is able to send and receive mesh transactions that are compatible with the mesh network. A mesh transaction is a single cycle transaction and includes in the case of a read transaction, a read indicator, a source address, and a destination address);
update a configuration value of the register based on the coordinate identifier (see para 0031, The coordinates of the node initiating a read transaction are sent along with the read transaction to fetch the data. When the data is fetched, the read transaction is turned into a write transaction and the original source coordinates are used as a destination address e.g. updating the transaction’s destination address value based on the source address value); and
transmit a message to the target device based on the configuration information and the coordinate identifier (see para 0031, a write transaction and the original source coordinates are used as a destination address to be sent along with the data).
Regarding claim 9, Olofsson further teaches the coordinate identifier comprises an x-coordinate of the target tile in the configurable topology and a y-coordinate of the target tile in the configurable topology (see para 0012, The circuit uses a 3D grid of elements addressable by dedicated X, Y, and Z coordinate fields within the transaction address).
Regarding claim 10, Olofsson further teaches the configuration information comprises one or more of product information associated with the configurable topology of the plurality of devices, or revision information associated with the configurable topology of the plurality of devices (see para 0040, the routing algorithm is configurable by the user through writing to a memory mapped mesh control register 430 contained within each processing node e.g. routing algorithm is construed as a product/revision information).
Regarding claim 11, Olofsson further teaches the configuration information comprises one or more of a payload, a target type identifier, an information type identifier, a linear identifier, or a protocol identifier (see para 0040, the routing scheme can be configured as fixed, adaptable, or random e.g. type and/or protocol identifier).
Regarding claim 13, Olofsson further teaches the plurality of devices comprises one or more of a processor, a memory controller, a graphics processor, a last level cache tile, a public key accelerator, a regular expression tile, a management gateway, a peripheral component interconnect express (PCIE) request node, or a memory subsystem (see para 0031, the processing element could be a software programmable processor, a hardware accelerator, or a piece of memory).
Regarding claims 14-19, the claims recite the method executed by the system of claims 1-6 addressed above. Please refer to the rejection of claims 1-6 since the claimed subject matter is substantially similar.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Olofsson as applied to claims above, and further in view of Zaccaria et al US 20160127207.
Regarding claim 7, Olofsson teaches all the features with respect to claim 1 as outlined above.
But Olofsson fails to teach the first message further comprises information identifying a type of the target tile, the one or more processing devices to: program the first tile based on the information identifying the type of the target tile.
However, Zaccaria teaches a message comprises information identifying a type of a target tile, and one or more processing devices to: program the first tile based on the information identifying the type of the target tile (see para 0014, send a second communication to the device via the communication interface, wherein the second communication includes a message configured to be processed by a subset of the device types that includes the identified device type, and wherein the second communication directs the device to provide a data value or range of data values).
Therefore, it would have been obvious to modify the transaction of Olofsson and further incorporate device type information.
The motivation for doing so is to improve device detection and discovery by providing useful information regarding the device type as taught by Zaccaria (see para 0008).
Regarding claims 12 and 20, please refer to the rejection of claim 7 above since the claimed subject matter is substantially similar.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Paneah et al US Patent No. 10,394,747 discloses implementing hierarchical PCI Express switch topology over coherent mesh interconnect
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/PHONG H DANG/Primary Examiner, Art Unit 2184