DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status
This present application was filed September 13, 2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 13, 2024 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Allowable Subject Matter
Claims 9 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In particular, the prior art does not teach or suggest a system/interface wherein the “transmit path of the first circuitry component comprises: a redriver connected and in series with the buffer; and a transmit transformer connected to the first output of the first device and is in series with the redriver” in combination with the limitations of the base claim and the intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over C. Song, H. Jung, K. Chang, K. Cho, S. Yoon and Y. -C. Jang, "A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 4, pp. 714-727, April 2024 (hereinafter Song) in view of US Pat. Pub. 20170019186 George Alan Wiley (hereinafter Wiley) in view of Altera 8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet, November 2001 (hereinafter Altera) further in view of .
Regarding claim 1, Song teaches A system, comprising:
a first device operable to communicate at a first line code; wherein the first device is a legacy hardware unit; (Song teaches a first device camera module (b) supporting C-PHY version 1.1 using serial data requiring a 8b/10b encoder mapped to a legacy hardware unit because it is older than C-PHY and different:
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a second device operable to communicate at a second line code; (Song teaches a second device, cameral module (a) supporting D-PHY requiring a 8b/10b encoder version 2.0 of the mobile industry processor interface (MIPI))
a [[bi-directional full-duplex]] interface connected to the first device and to the second device for communicating between the first device and the second device; [[wherein the bi-directional full-duplex interface is transformer coupled and operable to decode or encode a signal between the first device and the second device in the first line code or in the second line code.]] (Song teaches on page 715, third paragraph, a receiver bridge chip that enables simultaneous evaluation of camera modules “using both the MIPI D-PHY and C-PHY” The FPGA interface also performs serialization. Although Song teaches an FPGA that interacts with both D-PHY an C-PHY camera modules to receive both types of protocols and evaluate cameras, the FPGA is a “receive” interface that does not interact with the camera modules.)
Song does NOT teach that the interface is “bi-directional full duplex” or “wherein the bi-directional full-duplex interface is transformer coupled and operable to decode or encode a signal between the first device and the second device in the first line code or in the second line code”
In the same field of endeavor, Wiley teaches a bi-directional full-duplex interface connected to the first device and to the second device for communicating between the first device and the second device; wherein the bi-directional full-duplex interface [[is transformer coupled]] and operable to decode or encode a signal between the first device and the second device in the first line code or in the second line code. (Wiley teaches in Fig. 9 and Fig. 12 enables D-PHY or C-PHY protocols. Wiley para. [0097] teaches “The first bridge 1206 and the second bridge 1218 may also communicate data in accordance with C-PHY or D-PHY protocols. For example, in a low-power mode of operation, the first bridge 1206 may be configured to implement the LP mode protocol of C-PHY or D-PHY such that LP communications can be bridged to connectors of the auxiliary bus 1224. In the latter example, the second bridge 1218 may be configured to merge data received from the auxiliary bus 1224 back onto the C-PHY or D-PHY interface.” Further Fig. 11 illustrates a bidirectional multilink interface to couple an image sensor 1102 to an application processor 1120 which includes a C-PHY or D-PHY encoder. A deserializer 1118 converts the output to parallel from a receiver/decoder 1122. The bidirectional channel 1124 enables low power signals in both directions over the C-PHY or D-PHY interface.)
Although Wiley teaches a full duplex bidirectional path between “The first bridge 1206 and the second bridge 1218 may also communicate data in accordance with C-PHY or D-PHY protocols” Wiley does not identify the bidirectional path as “full duplex”.
In the analogous art of IEEE 802.3 communications, Altera teaches wherein a bi-directional full-duplex interface. (Altera teaches an 8b10 encoder/decoder MegaCore function capable of bidirectional full duplex communications on page 2:
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It would have been obvious to one of ordinary skill in the art prior to the effective date to have combined Song with Altera to include a MegaCore function to enable bidirectional full duplex communications between the devices. Each of Song and Altera are in the field of data communications. One of ordinary skill in the art would have been motivated to combine Altera with Song in order to enable 8-bit parallel data and 10-bit line-coded serial data in both directions and implement the physical layer coding for Gigabit Ethernet as taught in Altera page 1, lines 1-2.
It would have been obvious to one of ordinary skill in the art prior to the effective date of the invention to have combined Song and Wiley to teach a bidirectional full duplex interface to couple a C-PHY and D-PHY in full duplex. Each of Song and Wiley are in the field of MIPI and one of ordinary skill in the art would have been motivated to combine Song and Wiley in order to extend the receiver bridge of Song to interact with cameras as taught in Wiley para. [0005] which states that “some interfaces require that bidirectional and/or low-power modes of operation be implemented, neither of which requirements can be met by a conventional optical interface, which is unidirectional by nature.”
Song does NOT teach that the interface is “transformer coupled”.
In the analogous art of communication transceivers, Yang teaches “transformer coupled”. (Yang teaches a bidirectional full duplex transceiver shown inf Fig. 3:
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Yang does not illustrate a transformer in the figure, but teaches using “hybrid transformers” in column 1, lines 30-38 wherein send signals and received signals are connected out of face to enable high trans-hybrid loss so little of the send audio appears on the receive port. Hybrid transformers were well known for isolating send and receive signals as taught in Yang.
It would have been obvious to one of ordinary skill in the art prior to the effective date of the invention to have combined Yang and Song to include a hybrid transformer into an interface coupling MIDI related cameras. Transformer coupling was a conventional part of full duplex interfaces/transceivers as taught in Yang to separate transmit and receive signals on a line as explicitly taught in Yang, Col. 1 lines 30-38.
Regarding claim 2, Song does NOT teach The system of claim 1, wherein when the bi-directional full-duplex interface receives a first data signal at the first line code from the first device, the bi-directional full-duplex interface is operable to convert the first data signal to the second line code for the second device; and wherein when the bi-directional full-duplex interface receives a second data signal at the second line code from the second device, the bi-directional full-duplex interface is operable to convert the second data signal to the first line code for the first device.
In the analogous art of IEEE interfaces, Altera teaches wherein when the bi-directional full-duplex interface receives a first data signal at the first line code from the first device, the bi-directional full-duplex interface is operable to convert the first data signal to the second line code for the second device; (Altera teaches an 8b10 encoder/decoder MegaCore function capable of bidirectional full duplex communications on page 2:
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and
wherein when the bi-directional full-duplex interface receives a second data signal at the second line code from the second device, the bi-directional full-duplex interface is operable to convert the second data signal to the first line code for the first device. (Altera illustrates bidirectional full duplex interfacing wherein the line code is converted second to first line code and first line code to second line code.)
It would have been obvious to one of ordinary skill in the art prior to the effective date to have combined Song with Altera to include a MegaCore function to enable bidirectional full duplex communications between the devices. Each of Song and Altera are in the field of data communications. One of ordinary skill in the art would have been motivated to combine Altera with Song in order to enable 8-bit parallel data and 10-bit line-coded serial data in both directions and implement the physical layer coding for Gigabit Ethernet as taught in Altera page 1, lines 1-2.
Regarding claim 3, Song in view of Wiley, Altera, Yang and teach The system of claim 1 as stated.
Song does NOT teach wherein the bi-directional full-duplex interface comprises: a first circuitry component connected with a first input of the first device and a first output of the first device;
and
a second circuitry component operable with the first circuitry component and connected with a second input of the second device and a second output of the second device.
As shown, Song teaches a receive circuit coupled to the different camera modules:
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(As shown, Song teaches that the FPGA can be coupled to camera modules of different protocols.)
In the same field of endeavor, Wiley teaches wherein the bi-directional full-duplex interface comprises: a first circuitry component connected with a first input of the first device and a first output of the first device; (Wiley teaches as shown in Fig. 9 both D/PHY and C/PHY in a bidirectional full duplex circuitry wherein the CCI link 920 connects the input of a first device of a camera module to the first output of the camera module:
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a second circuitry component operable with the first circuitry component and connected with a second input of the second device and a second output of the second device. (Wiley Fig. 9 illustrates second circuitry component that shows the application processor 912 is coupled to both an input and an output of D/PHY and C/PHY via 910 and output over the input/output 920. Likewise, in low power mode, shown in Fig. 11, both protocols interact over bidirectional CCI 1124:
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It would have been obvious to one of ordinary skill in the art prior to the effective date of the invention to have combined Song and Wiley to teach a bidirectional full duplex interface to couple a C-PHY and D-PHY in full duplex. Each of Song and Wiley are in the field of MIPI and one of ordinary skill in the art would have been motivated to combine Song and Wiley in order to extend the receiver bridge of Song to interact with cameras as taught in Wiley para. [0005] which states that “some interfaces require that bidirectional and/or low-power modes of operation be implemented, neither of which requirements can be met by a conventional optical interface, which is unidirectional by nature.”
Regarding claim 4, Song does NOT teach wherein the bi-directional full-duplex interface further comprises: a receive path that connects the first output of the first device with the second input of the second device, wherein a first data signal is communicated along the receive path; and a transmit path that connects the second output of the second device with the first input of the first device, wherein a second data signal is communicated along the transmit path.
In the analogous art of data communications, Wiley teaches a receive path that connects the first output of the first device with the second input of the second device, wherein a first data signal is communicated along the receive path; (Wiley teaches in Fig. 11 a first device and second device as an application processor 1120 and image sensor 1100 wherein bidirectional data is sent and received over CCI_SDA wherein the inputs and outputs bidirectional)
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Likewise, Wiley teaches a transmit path that connects the second output of the second device with the first input of the first device, wherein a second data signal is communicated along the transmit path; (Wiley teaches in Fig. 11 that the same CCI_SDA is bidirectional coupling the Master and Slave.)
It would have been obvious to one of ordinary skill in the art prior to the effective date of the invention to have combined Song and Wiley to teach a bidirectional full duplex interface to couple a C-PHY and D-PHY in full duplex. Each of Song and Wiley are in the field of MIPI and one of ordinary skill in the art would have been motivated to combine Song and Wiley in order to extend the receiver bridge of Song to interact with cameras as taught in Wiley para. [0005] which states that “some interfaces require that bidirectional and/or low-power modes of operation be implemented, neither of which requirements can be met by a conventional optical interface, which is unidirectional by nature.”
Regarding claim 10, Song teaches The system of claim 1, wherein the first line code and the second line code are in different formats. (Song teaches that the line codes are in different formats in that the data is C-PHY for the first line code and D-PHY for the second line code as shown in Fig. 1, above.)
Regarding claim 11, Song does NOT teach The system of claim 1, wherein the bi-directional full-duplex interface is equipped to the second device and separate from the first device.
In the same field of endeavor, Wiley teaches the bi-directional full-duplex interface is equipped to the second device and separate from the first device. (Wiley teaches in Fig. 22 and para. [0130] teaches that any portion of an element, or any combination of elements may be implemented in a processing circuit. As such, the bi-directional full-duplex interface may be in a processing circuit inherent to either the first device or the second device.)
It would have been obvious to one of ordinary skill in the art prior to the effective date of the invention to have combined Song and Wiley to teach a bidirectional full duplex interface equipped on either the first device or the second device. Each of Song and Wiley are in the field of MIPI and one of ordinary skill in the art would have been motivated to combine Song and Wiley in order to extend the receiver bridge of Song to interact with cameras as taught in Wiley para. [0005] which states that “some interfaces require that bidirectional and/or low-power modes of operation be implemented, neither of which requirements can be met by a conventional optical interface, which is unidirectional by nature.”
Claims 12, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Wiley and Altera
Regarding claim 12, Song teaches [[A bi-directional full-duplex]] interface that is connected to a first device and to a second device (Song teaches a first device camera module (b) supporting C-PHY version 1.1 and a second device, cameral module (a) supporting D-PHY requiring a 8b/10b encoder version 2.0 of the mobile industry processor interface (MIPI):
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Song does NOT teach that the interface is “bi-directional full duplex” or “a first circuitry component connected with a first input of the first device and a first output of the first device; and a second circuitry component operable with the first circuitry device and connected with a second input of the second device and a second output of the second device; wherein the bi-directional full-duplex interface is operable to decode or encode a signal between the first device and the second device in the first line code or the second line code.”
In the same field of endeavor, Wiley teaches a bi-directional full-duplex interface connected to a first circuitry component connected with a first input of the first device and a first output of the first device; and a second circuitry component operable with the first circuitry device and connected with a second input of the second device and a second output of the second device; wherein the bi-directional full-duplex interface is operable to decode or encode a signal between the first device and the second device in the first line code or the second line code. (Wiley teaches in Fig. 12 enables D-PHY or C-PHY protocols. Para. [0097] teaches “The first bridge 1206 and the second bridge 1218 may also communicate data in accordance with C-PHY or D-PHY protocols. For example, in a low-power mode of operation, the first bridge 1206 may be configured to implement the LP mode protocol of C-PHY or D-PHY such that LP communications can be bridged to connectors of the auxiliary bus 1224. In the latter example, the second bridge 1218 may be configured to merge data received from the auxiliary bus 1224 back onto the C-PHY or D-PHY interface.” Further Fig. 11 illustrates a bidirectional multilink interface to couple an image sensor 1102 to an application processor 1120 which includes a C-PHY or D-PHY encoder. A deserializer 1118 converts the output to parallel from a receiver/decoder 1122. The bidirectional channel 1124 enables low power signals in both directions over the C-PHY or D-PHY interface.
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Wiley Fig. 9 illustrates second circuitry component that shows the application processor 912 is coupled to both an input and an output of D/PHY and C/PHY via 910 and output over the input/output 920. Likewise, in low power mode, shown in Fig. 11, both protocols interact over bidirectional CCI 1124:
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It would have been obvious to one of ordinary skill in the art prior to the effective date of the invention to have combined Song and Wiley to teach a bidirectional full duplex interface equipped on either the first device or the second device. Each of Song and Wiley are in the field of MIPI and one of ordinary skill in the art would have been motivated to combine Song and Wiley in order to extend the receiver bridge of Song to interact with cameras as taught in Wiley para. [0005] which states that “some interfaces require that bidirectional and/or low-power modes of operation be implemented, neither of which requirements can be met by a conventional optical interface, which is unidirectional by nature.”
Although Wiley teaches a full duplex bidirectional path between “The first bridge 1206 and the second bridge 1218 may also communicate data in accordance with C-PHY or D-PHY protocols” Wiley does not identify the bidirectional path as “full duplex”.
In the analogous art of IEEE 802.3 communications, Altera teaches wherein a bi-directional full-duplex interface. (Altera teaches an 8b10 encoder/decoder MegaCore function capable of bidirectional full duplex communications on page 2:
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)
It would have been obvious to one of ordinary skill in the art prior to the effective date to have combined Song with Altera to include a MegaCore function to enable bidirectional full duplex communications between the devices. Each of Song and Altera are in the field of data communications. One of ordinary skill in the art would have been motivated to combine Altera with Song in order to enable 8-bit parallel data and 10-bit line-coded serial data in both directions and implement the physical layer coding for Gigabit Ethernet as taught in Altera page 1, lines 1-2.
Regarding claim 13, Song does NOT teach The bi-directional full-duplex interface of claim 12, wherein when the bi-directional full-duplex interface receives a first data signal at a first line code from the first device, the bi-directional full-duplex interface is operable to convert the first data signal to a second line code for the second device; and wherein when the bi-directional full-duplex interface receives a second data signal at the second line code from the second device, the bi-directional full-duplex interface is operable to convert the second data signal to the first line code for the first device.
In the analogous art of IEEE 802.3 interfaces, Altera teaches wherein when the bi-directional full-duplex interface receives a first data signal at the first line code from the first device, the bi-directional full-duplex interface is operable to convert the first data signal to the second line code for the second device; (Altera teaches an 8b10 encoder/decoder MegaCore function capable of bidirectional full duplex communications on page 2:
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and
wherein when the bi-directional full-duplex interface receives a second data signal at the second line code from the second device, the bi-directional full-duplex interface is operable to convert the second data signal to the first line code for the first device. (Altera illustrates bidirectional full duplex interfacing wherein the line code is converted second to first line code and first line code to second line code.)
It would have been obvious to one of ordinary skill in the art prior to the effective date to have combined Song with Altera to include a Altera function to enable bidirectional full duplex communications between the devices. Each of Song and Altera are in the field of data communications. One of ordinary skill in the art would have been motivated to combine Altera with Song in order to enable 8-bit parallel data and 10-bit line-coded serial data in both directions and implement the physical layer coding for Gigabit Ethernet as taught in Altera page 1, lines 1-2.
Regarding claim 14, Song does NOT teach The bi-directional full-duplex interface of claim 12, wherein the bi-directional full-duplex interface further comprises: a receive path that connects the first output of the first device with the second input of the second device, wherein a first data signal is communicated along the receive path; and a transmit path that connects the second output of the second device with the first input of the first device, wherein a second data signal is communicated along the transmit path.
In the same field of endeavor, Wiley teaches a receive path that connects the first output of the first device with the second input of the second device, wherein a first data signal is communicated along the receive path; (Wiley teaches in Fig. 11 a first device and second device as an application processor 1120 and image sensor 1100 wherein bidirectional data is sent and received over CCI_SDA wherein the inputs and outputs bidirectional)
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Likewise, Wiley teaches a transmit path that connects the second output of the second device with the first input of the first device, wherein a second data signal is communicated along the transmit path; (Wiley teaches that the same CCI_SDA is bidirectional coupling the Master and Slave)
It would have been obvious to one of ordinary skill in the art prior to the effective date of the invention to have combined Song and Wiley to teach a bidirectional full duplex interface to couple a C-PHY and D-PHY in full duplex. Each of Song and Wiley are in the field of MIPI and one of ordinary skill in the art would have been motivated to combine Song and Wiley in order to extend the receiver bridge of Song to interact with cameras as taught in Wiley para. [0005] which states that “some interfaces require that bidirectional and/or low-power modes of operation be implemented, neither of which requirements can be met by a conventional optical interface, which is unidirectional by nature.”
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Wiley, Altera and Yang, further in view of US Pat. Pub. 20200313840 to Gerrit Willem Den Besten, (hereinafter Den Besten).
Regarding claim 5, Song does NOT teaches The system of claim 4, wherein the receive path of the first circuitry component comprises: a receive transformer connected to the first output of the first device; and an equalizer connected and in series with the receive transformer.
In the analogous art of communication circuitry, Den Besten teaches a receive transformer connected to the first output of the first device; and an equalizer connected and in series with the receive transformer. (Den Besten para. [0049] teaches that a communications device may include a transceiver with an equalizer 464 coupled to “at least one transformer”.)
It would have been obvious to one of ordinary skill in the art prior to the effective date of the invention to combine Den Besten and Song to include an equalizer in series with a receive path. Each of Den Besten and Song are in field of communications circuitry. One of ordinary skill in the art would have been motivated to include the Den Besten transformer in series with an equalizer to perform a known technique.
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Wiley, and Altera, further in view of Den Besten.
Regarding claim 15, Song does NOT teaches The bi-directional full-duplex interface of claim 14, wherein the receive path of the first circuitry component comprises: a receive transformer connected to the first output of the first device; and an equalizer connected and in series with the receive transformer.
In the analogous art of communication circuitry, Den Besten teaches : a receive transformer connected to the first output of the first device; and an equalizer connected and in series with the receive transformer. (Den Besten para. [0049] teaches that a communications device may include a transceiver with an equalizer 464 coupled to “at least one transformer”.)
It would have been obvious to one of ordinary skill in the art prior to the effective date of the invention to combine Den Besten and Song to include an equalizer in series with a receive path. Each of Den Besten and Song are in field of communications circuitry. One of ordinary skill in the art would have been motivated to include the Den Besten transformer in series with an equalizer to perform a known technique.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Wiley, Altera ,Yang, and Den Besten and further in view of US Pat. Pub. 20110164624 to Paul Kelleher et al. (hereinafter Kelleher)
Regarding claim 6, Song does NOT teaches The system of claim 5, wherein the receive path of the second circuitry component comprises: a clock data recovery unit connected and in series with the equalizer; a reference clock operable with the clock data recovery unit; a receive framing logic component connected and in series with the clock data recovery unit; and a decoder connected to the second input of the second device and in series with the receive framing logic component.
In the analogous art of IEEE 802.3 communications, Kelleher teaches wherein the receive path of the second circuitry component comprises: a clock data recovery unit connected [[and in series with the equalizer]]; a reference clock operable with the clock data recovery unit; a receive framing logic component connected and in series with the clock data recovery unit; and a decoder connected to the second input of the second device and in series with the receive framing logic component. (Kelleher teaches as follows:
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As shown Kelleher teaches a clock data recover, framing logic, 8b/10b encoder/decoder and a line driver as shown which are well known in the art.)
Song does NOT teach “[[and in series with the equalizer]]”.
In the analogous art of communication circuitry, Den Besten teaches “in series with an equalizer” (Den Besten para. [0049] teaches that a communications device may include a transceiver with an equalizer 464 coupled to “at least one transformer”.)
It would have been obvious to one of ordinary skill in the art prior to the effective date of the invention to combine Den Besten and Song to include an equalizer in series with a receive path. Each of Den Besten and Song are in field of communications circuitry. One of ordinary skill in the art would have been motivated to include the Den Besten transformer in series with an equalizer to perform a known technique.
It would have been obvious to one of ordinary skill in the art to have combined Song and Kelleher to teach a reference clock operable with the clock data recovery unit; a receive framing logic component connected and in series with the clock data recovery unit; and a decoder connected to the second input of the second device and in series with the receive framing logic component. Each of Song and Kelleher are in the art communication circuitry. One of ordinary skill in the art would have been motivated to combine Kelleher and Song in order to prevent EMI power and repetitiveness caused by 8b/10b encoding schemes at taught in Kelleher para. [0004].
Regarding claim 7, Song does NOT teach The system of claim 6, wherein the clock data recovery unit of the second circuitry component comprises: a transceiver that is operable with the reference clock; and a clock data recovery block (CDR) connected and in series with the transceiver.
In the analogous art of MIPI M-PHY standards, Kelleher teaches a transceiver that is operable with the reference clock; and a clock data recovery block (CDR) connected and in series with the transceiver. (Kelleher teaches in para. [0003] that the interface illustrated above is connected to a radio frequency integrated circuit (RFIC) transceiver.)
It would have been obvious to one of ordinary skill in the art to have combined Song and Kelleher to teach a reference clock operable with the clock data recovery unit; a receive framing logic component connected and in series with the clock data recovery unit; and a decoder connected to the second input of the second device and in series with the receive framing logic component. Each of Song and Kelleher are in the art communication circuitry. One of ordinary skill in the art would have been motivated to combine Kelleher and Song in order to prevent EMI power and repetitiveness caused by 8b/10b encoding schemes at taught in Kelleher para. [0004].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Wiley, Altera ,Yang, and Kelleher
Regarding claim 8, Song does NOT teach The system of claim 4, wherein the transmit path of the second circuitry component comprises: a transmit framing logic component connected to the second output of the second device; an encoder connected and in series with the transmit framing logic component; a serializer connected and in series with the encoder; and a buffer connected and in series with the serializer.
In analogous art of MIPI M-PHY standards, Kelleher teaches a transmit framing logic component connected to the second output of the second device; an encoder connected and in series with the transmit framing logic component; a serializer connected and in series with the encoder; and a buffer connected and in series with the serializer (Kelleher teaches an 8b/10b encoder in series with framing logic and PAR-2SER logic 250 which generates serial data as taught in para. [0027], which is provided to line driver 215 over interface 205. Fig. 2 further illustrates storage element 220 which is a type of buffer in series in with the serializer, as shown below:
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It would have been obvious to one of ordinary skill in the art to have combined Song and Kelleher to teach a reference clock operable with the clock data recovery unit; a receive framing logic component connected and in series with the clock data recovery unit; and a decoder connected to the second input of the second device and in series with the receive framing logic component. Each of Song and Kelleher are in the art communication circuitry. One of ordinary skill in the art would have been motivated to combine Kelleher and Song in order to prevent EMI power and repetitiveness caused by 8b/10b encoding schemes at taught in Kelleher para. [0004].
Claims 16, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Wiley, Altera, Den Besten and Kelleher
Regarding claim 16, Song does NOT teach The bi-directional full-duplex interface of claim 15, wherein the receive path of the second circuitry component comprises: a clock data recovery unit connected and in series with the equalizer; a reference clock operable with the clock data recovery unit; a receive framing logic component connected and in series with the clock data recovery unit; and a decoder connected to the second input of the second device and in series with the receive framing logic component.
In analogous art of MIPI M-PHY standards, Kelleher teaches wherein the receive path of the second circuitry component comprises: a clock data recovery unit connected [[and in series with the equalizer]]; a reference clock operable with the clock data recovery unit; a receive framing logic component connected and in series with the clock data recovery unit; and a decoder connected to the second input of the second device and in series with the receive framing logic component. (Kelleher teaches as follows:
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As shown Kelleher teaches a clock data recover, framing logic, 8b/10b encoder/decoder and a line driver as shown which are well known in the art.)
Song does NOT teach “[[and in series with the equalizer]]”.
In the analogous art of communication circuitry, Den Besten teaches “in series with an equalizer” (Den Besten para. [0049] teaches that a communications device may include a transceiver with an equalizer 464 coupled to “at least one transformer”.)
It would have been obvious to one of ordinary skill in the art prior to the effective date of the invention to combine Den Besten and Song to include an equalizer in series with a receive path. Each of Den Besten and Song are in field of communications circuitry. One of ordinary skill in the art would have been motivated to include the Den Besten transformer in series with an equalizer to perform a known technique.
It would have been obvious to one of ordinary skill in the art to have combined Song and Kelleher to teach a reference clock operable with the clock data recovery unit; a receive framing logic component connected and in series with the clock data recovery unit; and a decoder connected to the second input of the second device and in series with the receive framing logic component. Each of Song and Kelleher are in the art communication circuitry. One of ordinary skill in the art would have been motivated to combine Kelleher and Song in order to prevent EMI power and repetitiveness caused by 8b/10b encoding schemes at taught in Kelleher para. [0004].
Regarding claim 17, Song does NOT teach The bi-directional full-duplex interface of claim 16, wherein the clock data recovery unit of the second circuitry component comprises: a transceiver that is operable with the reference clock; and a clock data recovery block (CDR) connected and in series with the transceiver.
In the analogous art of MIPI M-PHY standards, Kelleher teaches a transceiver that is operable with the reference clock; and a clock data recovery block (CDR) connected and in series with the transceiver. (Kelleher teaches in para. [0003] that the interface illustrated above is connected to a radio frequency integrated circuit (RFIC) transceiver.)
Regarding claim 18, Song does NOT teach The bi-directional full-duplex interface of claim 14, wherein the transmit path of the second circuitry component comprises: a transmit framing logic component connected to the second output of the second device; an encoder connected and in series with the transmit framing logic component; a serializer connected and in series with the encoder; and a buffer connected and in series with the serializer.
In the analogous art of MIPI standards, Kelleher teaches a transmit framing logic component connected to the second output of the second device; an encoder connected and in series with the transmit framing logic component; a serializer connected and in series with the encoder; and a buffer connected and in series with the serializer (Kelleher teaches an 8b/10b encoder in series with framing logic and PAR-2SER logic 250 which generates serial data as taught in para. [0027], which is provided to line driver 215 over interface 205. Fig. 2 further illustrates storage element 220 which is a type of buffer in series in with the serializer, as shown below:
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It would have been obvious to one of ordinary skill in the art to have combined Song and Kelleher to teach a reference clock operable with the clock data recovery unit; a receive framing logic component connected and in series with the clock data recovery unit; and a decoder connected to the second input of the second device and in series with the receive framing logic component. Each of Song and Kelleher are in the art communication circuitry. One of ordinary skill in the art would have been motivated to combine Kelleher and Song in order to prevent EMI power and repetitiveness caused by 8b/10b encoding schemes at taught in Kelleher para. [0004].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Wiley, Altera ,Yang, and Kelleher further in view of
Regarding claim 9, Song does NOT teach wherein the transmit path of the first circuitry component comprises: a redriver connected and in series with the buffer; and a transmit transformer connected to the first output of the first device and is in series with the redriver.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wiley in view of Altera.
Regarding claim 20, Wiley teaches A method, comprising: connecting a bi-directional full-duplex interface with a first input of a first device and a first output of the first device; (Wiley teaches in Fig. 12 enables D-PHY or C-PHY protocols. Para. [0097] teaches “The first bridge 1206 and the second bridge 1218 may also communicate data in accordance with C-PHY or D-PHY protocols. For example, in a low-power mode of operation, the first bridge 1206 may be configured to implement the LP mode protocol of C-PHY or D-PHY such that LP communications can be bridged to connectors of the auxiliary bus 1224. In the latter example, the second bridge 1218 may be configured to merge data received from the auxiliary bus 1224 back onto the C-PHY or D-PHY interface>)
connecting the bi-directional full-duplex interface with a second input of a second device and a second output of the second device; . (Wiley teaches in Fig. 12 enables D-PHY or C-PHY protocols. Para. [0097] teaches “The first bridge 1206 and the second bridge 1218 may also communicate data in accordance with C-PHY or D-PHY protocols. For example, in a low-power mode of operation, the first bridge 1206 may be configured to implement the LP mode protocol of C-PHY or D-PHY such that LP communications can be bridged to connectors of the auxiliary bus 1224.)
receiving a first data signal at a first line code from the first device; converting the first data signal to a second line code for the second device; receiving a second data signal at the second line code from the second device; and converting the second data signal to the first line code for the first device. (Further Fig. 11 illustrates a bidirectional multilink interface to couple an image sensor 1102 to an application processor 1120 which includes a C-PHY or D-PHY encoder. A deserializer 1118 converts the output to parallel from a receiver/decoder 1122. The bidirectional channel 1124 enables low power signals in both directions over the C-PHY or D-PHY interface.)
Although Wiley teaches a full duplex bidirectional path between “The first bridge 1206 and the second bridge 1218 may also communicate data in accordance with C-PHY or D-PHY protocols” Wiley does not identify the bidirectional path as “full duplex”.
In the analogous art of IEEE 802.3 communications, Altera teaches wherein a bi-directional full-duplex interface. (Altera teaches an 8b10 encoder/decoder MegaCore function capable of bidirectional full duplex communications on page 2:
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It would have been obvious to one of ordinary skill in the art prior to the effective date to have combined Song with Altera to include a MegaCore function to enable bidirectional full duplex communications between the devices. Each of Song and Altera are in the field of data communications. One of ordinary skill in the art would have been motivated to combine Altera with Song in order to enable 8-bit parallel data and 10-bit line-coded serial data in both directions and implement the physical layer coding for Gigabit Ethernet as taught in Altera page 1, lines 1-2.
It would have been obvious to one of ordinary skill in the art prior to the effective date of the invention to have combined Song and Wiley to teach a bidirectional full duplex interface to couple a C-PHY and D-PHY in full duplex. Each of Song and Wiley are in the field of MIPI and one of ordinary skill in the art would have been motivated to combine Song and Wiley in order to extend the receiver bridge of Song to interact with cameras as taught in Wiley para. [0005] which states that “some interfaces require that bidirectional and/or low-power modes of operation be implemented, neither of which requirements can be met by a conventional optical interface, which is unidirectional by nature.”
Conclusion
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/MARGARET MARIE ANDERSON/Examiner, Art Unit 2412 /CHARLES C JIANG/Supervisory Patent Examiner, Art Unit 2412
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