Prosecution Insights
Last updated: October 02, 2026
Application No. 18/885,150

METHODS AND APPARATUS TO SENSE A STATE OF ISOLATION IN GATE DRIVER CIRCUITRY

Non-Final OA §103
Filed
Sep 13, 2024
Examiner
ISLAM, MUHAMMAD S
Art Unit
2837
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
544 granted / 617 resolved
+20.2% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
29 currently pending
Career history
633
Total Applications
across all art units

Statute-Specific Performance

§101
3.0%
-37.0% vs TC avg
§103
36.2%
-3.8% vs TC avg
§102
29.7%
-10.3% vs TC avg
§112
27.9%
-12.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 617 resolved cases

Office Action

§103
DETAILED ACTION This action is responsive to the following communications: Application filed on 09/13/2024. Claims 1-20 are presented for Examination. Claims 1, 8 and 15 are independent. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-20 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Wang (F. Qi, L. Xu, G. Zhao and J. Wang, "Transformer isolated gate drive with protection for SiC MOSFET in high temperature application," 2014 IEEE Energy Conversion Congress and Exposition (ECCE), Pittsburgh, PA, USA, 2014, pp. 5723-5728, doi: 10.1109/ECCE.2014.6954186.) in view of LeComte. Regarding Independent claim 1, Wang teaches that an apparatus comprising charge injection circuitry having a first terminal, a second terminal, and a control terminal Wang teaches a transmitter circuit ( Fig. 4, elements Q1-Q3) that functions to inject charge into a transformer. The differential pair Q2-Q3 has input terminals (bases), output terminals (collectors), and a common terminal controlled by the current source Q1, which in turn is controlled by a PWM input signal. This circuit is therefore a charge injection circuitry) first inductor-capacitor (LC) circuitry having a first terminal and a second terminal, the first terminal of the first LC circuitry coupled to the first terminal of the charge injection circuitry, the second terminal of the first LC circuitry coupled to the second terminal of the charge injection circuitry; (Wang teaches a pulse transformer (Section III.C, "Pulse Transformer Design") whose primary winding is coupled to the collectors of the transmitter transistors Q2 and Q3 (Wang, Fig. 4). A transformer winding is an inductor (L), which in combination with parasitic or explicit capacitance forms an LC circuitry) second LC circuitry magnetically coupled to the first LC circuitry (Wang teaches that the pulse transformer has secondary windings that are explicitly magnetically coupled to the primary winding to transmit the gate signal (Wang, Fig. 4). The secondary winding is also an inductor and thus forms the second LC circuitry) Wang does not explicitly teach current sense circuitry having an input terminal coupled to the control terminal of the charge injection circuitry. However, Wang does teach the importance of protection circuitry, disclosing a secondary-side Vds monitoring circuit for over-current protection (Wang, Fig. 6). LeComte, in contrast, teaches a solid-state power controller that explicitly uses a current sense amplifier (LeComte, Fig. 1, element 16) to monitor the load current for protection (LeComte, Col. 3, ll. 55-68). It would have been obvious to a person of ordinary skill in the art before the effective date of the invention to modify the circuit of Wang to include the current sense circuitry as taught by LeComte. The motivation for this combination would be to provide a more comprehensive protection scheme. While Wang's secondary-side sensing protects the SiC MOSFET, it does not protect the primary-side transmitter circuit itself from fault conditions. A person of ordinary skill, seeking to create a robust and reliable gate driver, would have found it obvious to add primary-side current sensing, as taught by LeComte, to monitor the health and status of the charge injection circuitry directly. Regarding claim 2, Wang teaches the specific transistor arrangement of the charge injection circuitry. The current source circuitry is taught by transistor Q1, the first transistor is taught by Q2, and the second transistor is taught by Q3. The interconnections described in the claim are all explicitly shown in Wang's transmitter circuit schematic (Wang, Fig. 4). Regarding claim 3, Wang teaches that Q1 functions as a current source for the differential pair Q2-Q3. The claim recites this current source is a third transistor, which is explicitly shown as transistor Q1 in Wang's Fig. 4. Coupling its control terminal (the base of Q1) to the input of the current sense circuitry is the modification rendered obvious by LeComte, as described for claim 1. Regarding claim 4, Wang’s pulse transformer primary is an inductor. In a practical high-frequency circuit, this inductor will have an associated parallel capacitor (either parasitic or explicitly added) to form a resonant tank. This is a fundamental aspect of such circuits, making the claimed structure inherent to or an obvious implementation of Wang’s transformer. Regarding claim 5, LeComte teaches a protection circuit that uses a transistor, comparator circuitry, and logic. For example, LeComte's thermal shutdown circuit includes an input transistor, a reference, and a comparator (LeComte, Fig. 1, element 20) whose output can be used to trigger a fault. The use of a transistor, comparator, and inverter is a standard and obvious topology for implementing the current sense circuitry taught by LeComte. A person of ordinary skill would select these components as a matter of routine design to implement the desired sensing and signal conditioning function. Regarding claim 6, the further addition of a resistor, level shifter, and buffer are fundamental "glue" components in circuit design. A person of ordinary skill implementing the sense circuit of LeComte in the context of Wang's system would obviously use resistors for biasing and gain, level shifters to interface between different voltage domains (e.g., analog sensor and digital logic), and buffers to ensure signal integrity, all as a matter of standard engineering practice. Regarding claim 7, Wang teaches receiver circuitry (Wang, Fig. 4, elements Q4-Q7) and protection logic. The concept of filtering unwanted noise is critical in isolated systems. A deglitch circuitry is a standard and well-known circuit for removing spurious short pulses from a signal path. It would have been obvious to a person of ordinary skill to add a deglitcher to the output of Wang's receiver to improve noise immunity before the signal is passed to the final gate drive stage, thereby preventing false turn-on or turn-off events. Regarding claims 8-14, these claims recite substantially the same invention as claims 1-7 but use the term transformer instead of first and second LC circuits. Wang explicitly discloses a pulse transformer (Wang, Section III.C). Therefore, claims 8-14 are rejected for the same reasons as claims 1-7. Regarding Independent claim 15, Wang teach that a gate driver circuitry configured to: receive a pulse width modulation (PWM) signal: Wang explicitly states, "The buffer in the block diagram obtains the PWM signal from the upper level controller" (Wang, Section IV, para. 1). generate a current based on a logical state of the PWM signal( Wang's transmitter circuit (Wang, Fig. 4) generates current pulses in the transformer primary in response to the PWM input) generate a sinusoidal signal in response to the current(The pulsed current in the transformer results in a pulsed voltage signal on the secondary, which is composed of sinusoidal frequencies And, as made obvious by the combination with LeComte, a current sense circuitry to sense the generation of the current and set a logical state of a safe signal. Wang's protection circuit already generates a "fault signal" (Wang, Section IV.A), which is functionally a safe signal. The modification of sensing current instead of voltage is rendered obvious by LeComte, as explained for claim 1. Regarding claim 16, Wang's gate driver operates by injecting current into the transformer, which is an LC circuitry, as explained for claim 1. Regarding claim 17, Wang’s protection circuit (Wang, Fig. 6) sets a fault signal to a first state upon detecting an over-current condition and a second state when the condition is cleared, teaching the claimed functionality. Regarding claim 18, adding an inverter to achieve a desired signal polarity is a trivial and obvious design choice for any person of skill in the art. Regarding claim 19, Wang explicitly teaches that disabling the gate driver in response to a fault: wherein the current sense circuitry is further configured to disable the gate driver circuitry in response to setting the safe signal to a logical state matching the logical state of the PWM signal ( "Once a fault is detected, the output of Q1 will be pulled down and the SiC MOSFET will be turned off immediately..." (Wang, Section IV.A). Regarding claim 20, Wang’s entire design is based on transmitting a signal across an isolation barrier (the transformer) and generating a new PWM signal on the secondary. The addition of deglitching, as argued for claim 7, would be an obvious improvement to ensure signal integrity. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUHAMMAD S ISLAM whose telephone number is (571)272-8439. The examiner can normally be reached 9:30am to 6:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eduardo Colon-Santana can be reached on 571-272-2060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MUHAMMAD S ISLAM/Primary Examiner, Art Unit 2837
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Prosecution Timeline

Sep 13, 2024
Application Filed
Jun 30, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+8.9%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 617 resolved cases by this examiner. Grant probability derived from career allowance rate.

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