DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 12/29/2025 have been fully considered but they are not persuasive.
Applicant’s first argument is the claims require a tag region dynamically usable for storing normal data and that Beale teaches structural separation of tag and data regions.
Examiner respectfully disagrees. The argument is not persuasive. The claims merely recite: 1. A tag region storing tag data; 2. A data region storing normal data; and 3. That when a tag operation is not required, the memory operation on normal data is performed in one of the tag region and the data region.
The claims do not require:
* A same physical region exclusively designated as tag storage being repurposed;
* Elimination of structural separation;
* Nor do they exclude pre-allocated regions.
Beale discloses: A memory controller controlling a memory device including a tag area 504 and a data area 502, area descriptors defining base address and length of memory areas, and memory operations directed to specific areas based on descriptor selection.
Beale expressly teaches that memory areas are defined and accessed via area descriptors, which include base address and length. The descriptor system allows flexible allocation and addressing of memory regions. Nothing in the claims excludes the structure taught in Beale.
Further, the claims do not require that the tag region be exclusively dedicated or permanently repurposed. They merely recite that memory operations may be performed in one of the tag region and the data region.
Beale inherently allows memory operations to be directed to any defined region via descriptor selection. Therefore, the claimed “dynamic” use is met.
Applicant’s argument attempts to import a limitation requiring interchangeability of physical storage without structural separation. Such limitation is not present in the claims.
Applicant’s second argument is Beale does not disclose conditional selection of region based on whether a tag operation is required.
Examiner respectfully disagrees. Beale discloses: 1) Memory requests processed using area descriptors; 2) Tag operations and data operations being handled via separate but addressable regions, and 3) Descriptor-based access permitting selective operations.
Beale teaches that I/O operations become simplified because tags are sequentially organized in a memory area separate from data (Col. 10, lines 65–67). This necessarily implies conditional handling of tag and data accesses. When tag operations are performed, accesses are directed to tag area 504. When normal data operations are performed, accesses are directed to data area 502. Thus, Beale performs region selection based on the type of operation requested.
The claims do not require a particular algorithmic decision logic beyond selecting a region based on operation type. Beale meets this limitation.
Applicant’s third argument is Beale does not disclose fixing start positions of tag and data regions by the processor in the claimed manner.
Examiner respectfully disagrees. As set forth in the Office Action (page 4 ), Beale teaches: 1) Area descriptors including base address and length, 2) Creation and storage of descriptors in a collection, and 3) Use of descriptors to define memory areas.
Also, the “base address” corresponds to the claimed “start position.”
Beale’s processor returns an area descriptor token identifying the memory region. The descriptor includes the base address and defines the region.
Therefore, start positions are defined, addresses are generated, and operations are performed based on the defined region. The fact that virtual address management may involve the operating system does not negate that the memory controller operates on defined base addresses.
The claims do not require that the processor operate independently of an OS. Accordingly, Beale discloses the claimed address fixing and generation limitations.
Applicant further asserts that Beale never discloses performing normal data operations in the tag area.
The claims do not require that normal data must actually be stored in the tag region in Beale’s embodiment. They merely recite that: “the memory operation on the normal data is performed in one of the tag region and the data region.”
Beale teaches performing memory operations directed to specific regions defined by descriptors. Because both regions are memory areas accessible via descriptors, Beale inherently discloses performing memory operations in either region.
Applicant’s argument seeks to impose a limitation requiring physical interchangeability not recited in the claims. The rejection is therefore maintained.
Applicant’s argument regarding the dependent claims are by virtue of dependency. The argument is not persuasive.
Beale teaches the base memory controller and tag region architecture. On the other hand, Steinmacher-Burow teaches: 1) Invalidating cache lines corresponding to specific addresses, and 2) Data cache block invalidation operations.
The combination is proper because: both references relate to memory management systems, both address region-based memory operations, and Modifying Beale to include known cache invalidation techniques of Steinmacher-Burow would have been obvious to improve consistency and memory coherency.
Applicant has not identified any structural limitation in the dependent claims not met by the combination. The rejection under §103 is therefore maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9, 12-15 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Beale et al. [US 9,823,851 B2].
Regarding Claim 1, Beale teaches “A system-on-chip comprising:” as “embodiments of the present disclosure may be practiced in an electrical circuit comprising discrete electronic elements, packaged or integrated electronic chips containing logic gates, a circuit utilizing a microprocessor, or on a single chip containing electronic elements or microprocessors.” [Col 27, lines 29-34]
“a memory controller configured to control a memory device including a tag region storing tag data and a data region storing normal data; and” as “In this example, a separate memory area 502 and a tag area 504 are allocated in response to a request for a tagged area of 32K bytes in length.” [Col 14, lines 4-7]
“a processor configured to control a memory operation of the memory controller on the memory device,” as “ as used by the intelligent processor module 108, memory areas will be addressed by way of area descriptors, which have virtual addresses and lengths managed by the underlying native architecture.” [Col 14, lines 29-32]
“wherein the processor is further configured to fix a start position of the tag region and a start position of the data region in the memory device, and transmit an access request and a first address indicating a memory region of the memory device to the memory controller,” as “the area descriptor including a base address and a length of the memory area;” [Col 3, lines 24-25]
“wherein the memory operation on the normal data is to be performed on the memory region in one of the tag region and the data region, and” as “ In this arrangement, I/O operations become simplified, because the tags are sequentially organized in an area of memory separate from the data, and therefore a common operation (setting tag values to zero) can be accomplished by an efficient operation, e.g., by a memset operation, available from the underlying commodity platform 102.” [Col 10, line 65-Col 11, line 4]
“wherein the memory controller is further configured to perform the memory operation on the normal data based on the first address in response to the access request.” as “The operator returns an area descriptor (AD) token (included in the area descriptor collection 202) assigned, and an area descriptor 404 includes control bits (defining attributes of the memory area), a length, and data area virtual address indicating a location of the data.” [Col 13, lines 62-67]
Regarding Claim 2, Beale teaches “wherein the processor is further configured to transmit, to the memory controller, the first address indicating a region for performing the memory operation on the normal data in the data region and a tag command for performing a memory operation on the tag data corresponding to the normal data, and wherein the memory controller is further configured to perform a memory operation on the normal data on the data region based on the first address and perform a memory operation on the tag data on the tag region based on the first address.” as “creating an area descriptor associated with a memory area included within the portion of the memory, the area descriptor including a base address and a length of the memory area; storing the area descriptor in an area descriptor collection; receiving a memory request associated with the memory area, the memory request including a memory location defined by the area descriptor and an offset within the memory area associated with the area descriptor; translating the memory location to an address in the memory managed by the operating system; and performing the memory request at the address.” [Col 3, lines 22-33]
Regarding Claim 3, Beale teaches “when the memory controller receives the first address and the tag command,” as “ it is noted that a concept of tagged memory may be implemented. In a tagged memory implementation, tags are used that identify a memory word as a specific type or kind of word.” [Col 10, lines 14-17]
“the memory controller is further configured to generate a second address indicating a location of at least a part of the tag region, on which the memory operation on the tag data is to be performed, based on the first address and perform the memory operation on the tag data based on the second address.” as “creating an area descriptor associated with a memory area included within the portion of the memory, the area descriptor including a base address and a length of the memory area; storing the area descriptor in an area descriptor collection; receiving a memory request associated with the memory area, the memory request including a memory location defined by the area descriptor and an offset within the memory area associated with the area descriptor; translating the memory location to an address in the memory managed by the operating system; and performing the memory request at the address.” [Col 3, lines 22-33]
Regarding Claim 4, Beale teaches “wherein the memory controller is further configured to generate the second address based on the first address, the start position of the tag region, and the start position of the data region.” as “ the area descriptor including a base address and a length of the memory area; storing the area descriptor in an area descriptor collection; ” [Col 3, lines 24-26]
Regarding Claim 5, Beale teaches “wherein, when the access request corresponds to a write request, the memory controller is further configured to: receive the normal data and the tag data corresponding to the normal data from the processor;” as “the IOP 1002 and intelligent processor module 108 share status and interrupt information via the shared known area descriptor segment 1005, which can be maintained, but periodically renamed to ensure security. This renaming operation (i.e., referencing the known area descriptor segment 1005 with a different area descriptor) will minimize the chance of malware writing to that area. It is noted that only writes to a changed status word would typically cause disruption of I/O operations.” [Col 19, lines 4-12]
“write the normal data to the data region corresponding to the first address; and write the tag data to the tag region corresponding to the second address.” as “This allows the intelligent processor module 108, or software stored thereon, to intelligently select to read/write data to specific areas of memory, for example to provide memory-speed runtime logging for audit purposes.” [Col 13, lines 20-23]
Regarding Claim 6, Beale teaches “wherein the memory controller is further configured to: read the tag data from the tag region after writing the tag data to the tag region corresponding to the second address;” as “ the IOP 1002 and intelligent processor module 108 share status and interrupt information via the shared known area descriptor segment 1005, which can be maintained, but periodically renamed to ensure security. This renaming operation (i.e., referencing the known area descriptor segment 1005 with a different area descriptor) will minimize the chance of malware writing to that area. It is noted that only writes to a changed status word would typically cause disruption of I/O operations.” [Col 19, lines 4-12]
“determine whether the tag data received from the processor matches the tag data read from the tag region corresponding to the second address to calculate a matching result; and transmit the matching result to the processor.” as “This allows the intelligent processor module 108, or software stored thereon, to intelligently select to read/write data to specific areas of memory, for example to provide memory-speed runtime logging for audit purposes.” [Col 13, lines 20-23]
Regarding Claim 7, Beale teaches “when the access request corresponds to a read request, the memory controller is further configured to: read the normal data from the data region corresponding to the first address;” as “ the IOP 1002 and intelligent processor module 108 share status and interrupt information via the shared known area descriptor segment 1005, which can be maintained, but periodically renamed to ensure security. This renaming operation (i.e., referencing the known area descriptor segment 1005 with a different area descriptor) will minimize the chance of malware writing to that area. It is noted that only writes to a changed status word would typically cause disruption of I/O operations.” [Col 19, lines 4-12]
“read the tag data from the tag region corresponding to the second address; and transmit the normal data and the tag data to the processor.” as “This allows the intelligent processor module 108, or software stored thereon, to intelligently select to read/write data to specific areas of memory, for example to provide memory-speed runtime logging for audit purposes.” [Col 13, lines 20-23]
Regarding Claim 9, Beale teaches “wherein the start position of the data region and the start position of the tag region are fixed in the memory device when the system-on-chip is booted.” as “ The BIOS 1418 includes a set of computer-executable instructions that, when executed by the processing system 1404, cause the computing device 1400 to boot up.” [Col 25, lines 52-55]
Claim 12 is anticipated by Beale under the same rationale of anticipation of claim 1.
Claim 13 is anticipated by Beale under the same rationale of anticipation of claim 2.
Claim 14 is anticipated by Beale under the same rationale of anticipation of claim 3.
Claim 15 is anticipated by Beale under the same rationale of anticipation of claim 4.
Regarding Claim 19, Beale teaches “An operating method of a processor communicating with a storage device, the operating method comprising:” as “embodiments of the present disclosure may be practiced in an electrical circuit comprising discrete electronic elements, packaged or integrated electronic chips containing logic gates, a circuit utilizing a microprocessor, or on a single chip containing electronic elements or microprocessors.” [Col 27, lines 29-34]
“allocating a tag region storing tag data and a data region storing normal data in the storage device when the processor is booted;” as “In this example, a separate memory area 502 and a tag area 504 are allocated in response to a request for a tagged area of 32K bytes in length.” [Col 14, lines 4-7]
“designating at least a part of one of the tag region and the data region as a memory region on which a memory operation on the normal data is to be performed; and” as “the area descriptor including a base address and a length of the memory area;” [Col 3, lines 24-25] and “ In this arrangement, I/O operations become simplified, because the tags are sequentially organized in an area of memory separate from the data, and therefore a common operation (setting tag values to zero) can be accomplished by an efficient operation, e.g., by a memset operation, available from the underlying commodity platform 102.” [Col 10, line 65-Col 11, line 4]
“transmitting a first address and an access request for the normal data to the storage device, the first address indicating the memory region on which the memory operation on the normal data is to be performed.” as “The operator returns an area descriptor (AD) token (included in the area descriptor collection 202) assigned, and an area descriptor 404 includes control bits (defining attributes of the memory area), a length, and data area virtual address indicating a location of the data.” [Col 13, lines 62-67]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10-11 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Beale et al. [US 9,823,851 B2] in view of STEINMACHER-BUROW [US 2019/0251029].
Claim 10 is rejected over Beale and STEINMACHER-BUROW.
Beale does not explicitly teach wherein the memory controller includes a tag cache storing tag data stored in at least a part of the tag region and the memory controller is further configured to invalidate a cache line of the cache corresponding to the first address based on the first address.
However, STEINMACHER-BUROW teaches “wherein the memory controller includes a tag cache storing tag data stored in at least a part of the tag region and the memory controller is further configured to invalidate a cache line of the cache corresponding to the first address based on the first address.” as “The predefined command may e.g. be a data cache block invalidate command dcbix(address tag, X) identifying a cache line assigned with the address tag to be invalidated as well as a second cache memory X that is likely to contain a valid copy of the cache line after invalidation of the copy in the first cache memory. ” [¶0043]
Beale and STEINMACHER-BUROW are analogous arts because they teach storage system management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Beale and STEINMACHER-BUROW before him/her, to modify the teachings of Beale to include the teachings of STEINMACHER-BUROW with the motivation of application software may be executed on one or more processor chips 901 and thus a given application may implicitly or explicitly exploit and benefit from similar or different processor chips 901. [STEINMACHER-BUROW, ¶0083]
Claim 11 is rejected over Beale and STEINMACHER-BUROW.
Beale does not explicitly teach when the processor transmits, to the memory controller, the first address indicating the tag region cached by the tag cache in the memory operation on the normal data, the memory controller is further configured to invalidate the cache line corresponding to the first address in the tag cache.
However, STEINMACHER-BUROW teaches “when the processor transmits, to the memory controller, the first address indicating the tag region cached by the tag cache in the memory operation on the normal data, the memory controller is further configured to invalidate the cache line corresponding to the first address in the tag cache.” as “The predefined command may e.g. be a data cache block invalidate command dcbix(address tag, X) identifying a cache line assigned with the address tag to be invalidated as well as a second cache memory X that is likely to contain a valid copy of the cache line after invalidation of the copy in the first cache memory. ” [¶0043]
Claim 16 is rejected over Beale and STEINMACHER-BUROW under the same rationale of rejection of claim 10.
Claim 17 is rejected over Beale and STEINMACHER-BUROW under the same rationale of rejection of claim 11.
Allowable Subject Matter
Claims 8, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/Primary Examiner, Art Unit 2132