Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 12 are rejected under 35 U.S.C. 103 as being unpatentable over SAEKI (DE 102005042334 A1) in view of Thanigasalam (US 2007/0177701 A1) in view of LEE (US 20230112285 A1).
With regards to claim 1, SAEKI teaches:
A method for the contactless transfer of serial signals (17) from a transmitter (2) to a receiver (3), (FIG. 12 and corresponding specification, Fig. 12 is a circuit diagram showing the structure of a preferred embodiment of the present invention. To facilitate the production of the drawings, shows 2 a transmitter / receiver circuit on a single channel and the circuit shared by all channels.) wherein the signals (17) from the transmitter (2) are received in the form of a first bit stream (12) with a first bit clock (10) and are evaluated by a control unit (6), (FIG. 10 and corresponding specification, with respect to the data on the N-th channel, parallel data "*, *, *, *, *, 0" on the rising edge of the frequency-divided clock signal (Nch 6div H0) is applied to the register array at time t1 122 and parallel data "2, 4, 6, 8, 10, *" are applied to the register array at the rising edge of the frequency-divided signal at time t2 122 transfer. In this example, the received serial data stream at channel N lags behind channel 1 by 4 clocks and advances 5 clocks from channel 2). and a delay time (14) is set and transmitted to a delay circuit (8) which scans all bits of the signals (17) in the first bit stream (12) and saves them, delayed by the delay time (14), characterized in that a search is made for a start bit (15) of a signal (17) within the first bit stream (12) (BACKGROUND THE INVENTION paragraph 2, a delay calculator calculates 215 the amount of delay between these two channels, and a delay difference pickup unit 217 eliminates the difference in delay between the two channels based on the result of the calculation. Whenever a sync signal detector detects a sync signal, a similar operation is performed until the differences in delay between all channels are finally eliminated and all channels are synchronized). and for reading out from the FIFO memory (9), pending bits are in each case sequentially read out synchronously with the second bit clock (11), (BACKGROUND THE INVENTION paragraph 2, a timing switching unit 218 so that the synchronization timing signal which has been generated is supplied to the synchronizing signal detector which has detected the synchronizing signal). wherein the second bit clock (11) is the bit clock of the inductive transmitting unit, and the control unit (6) detects a time offset between the first bit clock (10) and the second bit clock (11), and sets the delay time (14) (SUMMARY OF THE REVELATION paragraph 2, an internal clock signal supplied to the receiver circuit and for the bit Offset is set at a clock input terminal of the receiver circuit in each of the number of channels, thereby ensuring the synchronization between the number of channels). in such a way that it corresponds at least to the time interval between an ending edge of the start bit (15) and the next edge of the second bit clock (11), and at most corresponds to the time interval between a starting edge of the start bit (15) and the next edge of the second bit clock (11), but a middle range of each bit received in the first bit clock (10) is preferably synchronized with the second bit clock (11). (Embodiment 1 and corresponding specification, An edge detection alignment circuit (edge detection 6div alignment to CTS CLK) 120 uses the edge detection result edge [5,0] to align the phase of the divided by 6 clock of the recovery clock signal to the phase of the CTS clock signal (CTS CLK). For example, based on the information provided by the edge detector 118 has been detected, the edge detection alignment circuit 120 use the frequency-divided clock of the rising edge, which corresponds to the rising edge of the CTS clock signal, as the 6-divided clock (6div H0) for the serial-parallel conversion).
SAEKI fails to teach:
using the control unit (6), and the delay circuit (8) sequentially saves all bits of the signals (17) in a FIFO memory (9), in each case for a second bit clock (11);
However, Thanigasalam teaches:
using the control unit (6), and the delay circuit (8) sequentially saves all bits of the signals (17) in a FIFO memory (9), in each case for a second bit clock (11); (0039, Buffer control logic 116 manages the operation of the FIFO forming elastic buffer 112 and the insertion and removal of clock compensation symbols.).
It would have been obvious to one of ordinary skill in the art at the time the invention was
effectively filed to modify the system of a method for the contactless transfer of serial signals from a transmitter to a receiver of SAEKI with the teaching of Thanigasalam, which teaches FIFO memory logic and circuitry in order to manage communicating signals through the channels (0039, As data is written into the FIFO the write pointer is incremented and as data is read from the FIFO the read pointer is incremented).
SAEKI in view of Thanigasalam fails to teach:
and transferred as a second bit stream (13) via an air gap (7) by means of an inductive transmitting unit stream and transmitted to the receiver (3);
However, LEE teaches:
and transferred as a second bit stream (13) via an air gap (7) by means of an inductive transmitting unit stream and transmitted to the receiver (3); (0152, an air gap is formed in a portion of a region in which a signal line is disposed, thereby improving signal transmission efficiency, compared to a calibration substrate structure including a dielectric about a line (a signal line) for transferring a signal inside a transmission line);
It would have been obvious to one of ordinary skill in the art at the time the invention was
effectively filed to modify the system of a method for the contactless transfer of serial signals from a transmitter to a receiver of SAEKI with the teaching of Lee, which teaches transfer via air gap in order to communicating signals effectively through the channels (0152, an air gap is formed in a portion of a region in which a signal line is disposed, thereby improving signal transmission efficiency).
With regards to claim 2, SAEKI in view Thanigasalam in view of Lee teaches the method of claim 1. SAEKI teaches:
The method according to the method according to characterized in that the control unit (6) compares each signal (17) to a template, and supplements missing end bits (16) if necessary if they are not received within the signal (17). (BACKGROUND THE INVENTION paragraph 2, Whenever a sync signal detector detects a sync signal, a similar operation is performed until the differences in delay between all channels are finally eliminated and all channels are synchronized.)
With regards to claim 3, SAEKI in view Thanigasalam in view of Lee teaches the method of claim 1. SAEKI teaches:
The method according to claim 1, characterized in that the control unit (6) sets a separate delay time (14) for each signal (17). (BACKGROUND THE INVENTION paragraph 2, a delay calculator calculates 215 the amount of delay between these two channels, and a delay difference pickup unit 217 eliminates the difference in delay between the two channels based on the result of the calculation.)
With regards to claim 4, SAEKI in view Thanigasalam in view of Lee teaches the method of claim 1. SAEKI teaches:
The method according to claim 1, characterized in that the second bit clock (11) of the inductive transmitting unit has the same clock rate as the first bit clock (10), preferably corresponding to a highest possible first bit clock (10) of the transmitter (2) for a signal protocol that is used, or to an integer multiple thereof. (SUMMARY OF THE REVELATION paragraph 4, the phase of the internal clock signal and the phase of the frequency-divided clock signal in the receiver circuit the channel can be pushed and adjusted so that they are essentially the same;)
With regards to claim 5, SAEKI in view Thanigasalam in view of Lee teaches the method of claim 1. SAEKI fails to teach:
The method according to claim 1, characterized in that clock rates of 4.8 Kbit/s, 38.4 Kbit/s, or 230.4 Kbit/s are provided as the first bit clock (10).
However, Thanigasalam teaches:
The method according to claim 1, characterized in that clock rates of 4.8 Kbit/s, 38.4 Kbit/s, or 230.4 Kbit/s are provided as the first bit clock (10). (0059, Local clock generator 214 generates the local clock with a frequency value of 2.5 GHz.+-.300 ppm. Clock dividers may be used as needed to derive slower local clocks such as the local symbol clock).
It would have been obvious to one of ordinary skill in the art at the time the invention was
effectively filed to modify the system of a method for the contactless transfer of serial signals from a transmitter to a receiver of SAEKI with the teaching of Thanigasalam, which teaches FIFO memory logic and circuitry in order to manage communicating signals through the channels (0039, As data is written into the FIFO the write pointer is incremented and as data is read from the FIFO the read pointer is incremented).
With regards to claim 6, SAEKI in view Thanigasalam in view of Lee teaches the method of claim 1. SAEKI teaches:
The method according to claim 1, characterized in that the control unit (6) determines the clock rate of the first bit clock (10) and uses it for synchronization with the second bit clock (11). (Description paragraph 11, the receiver circuit detecting a frame pattern; which has been inserted into the received serial data and outputs a parallel data signal which is synchronized with the frame pattern;)
With regards to claim 7, SAEKI in view Thanigasalam in view of Lee teaches the method of claim 1. SAEKI teaches:
The method according to claim 1, characterized in that within a cycle of the second bit clock (11), multiple bits of a signal (17) or of multiple signals (17) of the transmitter (2) are simultaneously transferred to the receiver (3). (Description paragraph 42, the number of clock count steps (counter periods) in the frequency divider circuit becomes 13 in time terms varies so that the byte or word data, which is parallel to the series-parallel converter circuit 12 is output, coincides with the detection timing of the frame head. For example, if the number of counts is set to a prescribed number of cycles (x cycles) for one period in the frequency divider circuit 13 is reduced, the phase can be pushed forward by x cycles.)
With regards to claim 8, SAEKI in view Thanigasalam in view of Lee teaches the transfer device and corresponds to claim 1 as analyzed accordingly.
With regards to claim 9, SAEKI in view Thanigasalam in view of Lee teaches the transfer device of claim 8. SAEKI fails to teach:
The transfer device according to the transfer device according to characterized in that the control unit (6) has means for setting a clock rate of the first bit clock (10).
However, Thanigasalam teaches:
The transfer device according to the transfer device according to characterized in that the control unit (6) has means for setting a clock rate of the first bit clock (10). (0015, In accordance with an aspect of the present invention, there is provided a receiver for providing symbols at a second clock rate from an incoming stream of symbols clocked at a first clock rate, comprising a first buffer for storing symbols in the incoming stream at the first clock rate).
It would have been obvious to one of ordinary skill in the art at the time the invention was
effectively filed to modify the system of a method for the contactless transfer of serial signals from a transmitter to a receiver of SAEKI with the teaching of Thanigasalam, which teaches FIFO memory logic and circuitry in order to manage communicating signals through the channels (0039, As data is written into the FIFO the write pointer is incremented and as data is read from the FIFO the read pointer is incremented).
With regards to claim 10, SAEKI in view Thanigasalam in view of Lee teaches transfer device of claim 8. SAEKI teaches:
The transfer device according to claim 8, characterized in that the control unit (6) has a multiplexer for simultaneously transferring multiple signals via the inductive transmitting unit. (FIG. 12 and corresponding specification, this circuit corresponds to a transmission-side multiplexer 137 that outputs the 2-bit parallel signal 2 multiplexed into serial data and outputs the data to a serial transmission line.)
With regards to claim 11, SAEKI in view Thanigasalam in view of Lee teaches the transfer device of claim 8. SAEKI teaches:
The transfer device according to claim 8, characterized in that the transfer device is designed completely in software on a CPU, in programmable logic on an FPGA or a CPLD, in integrated logic on an IC or ASIC, or with hard-wired logic, or from a mixture of such components. (PREFERRED EMBODIMENTS THE INVENTION paragraph 1, Referring to 1, is a PLL (phase locked loop) circuit 20 a clock generating circuit which receives a system clock SCLK to generate a clock located inside the device.)
With regards to claim 12, SAEKI in view Thanigasalam in view of Lee teaches the transfer device of claim 8. SAEKI teaches:
The transfer device according to claim 8, characterized in that the inductive transmitting unit has a bidirectional design, i.e., either has combined inductive transmitting units and receiving units on both sides, or has an inductive transmitting unit (4) and an inductive receiving unit (5) on each side. (SUMMARY OF THE REVELATION paragraph 1, According to one Aspect of the present invention is a synchronization device created in each of the number of channels a receiver circuit has, with the receiver circuits enter received serial data on a number of channels, the received page data on the corresponding channels one Undergo serial-to-parallel conversion and output parallel data).
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
Su (US 2013/0170591 A1): A computing device quarantine action system includes a computing device having a plurality of computing device components and a Basic Input/Output System (BIOS) subsystem.
Conclusion
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/V.P./Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111