DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Preliminary Amendment
2. The Examiner acknowledges the amended claims filed on 09/16/2024. Claims 21-24 have been cancelled.
Priority
3. Receipt is acknowledged of certified copies of documents required by 37 CFR 1.55.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 09/16/2024 is in compliance with the provisions of 37 CFR 1.97 and was considered by the examiner.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Horikoshi (US-PGPUB 2022/0077215).
Regarding claim 1, Horikoshi discloses a stacked image sensor (see fig. 10A) comprising:
a first semiconductor chip (see fig. 10A; sections 1 and 3) including:
a first photoelectric conversion layer (First charge generation region 12a; see fig. 10A and paragraph 0104), a first floating diffusion region (First Charge Storage Region 15a; see fig. 10A and paragraph 0104), and a first transfer transistor electrically connecting the first photoelectric conversion layer to the first floating diffusion region (Transfer transistor 16 connects the photodiode 10 to the floating diffusion region 15; see figs. 2, 10A and paragraphs 0062, 0102); and
a second photoelectric conversion layer (Second charge generation region 12b; see fig. 10A and paragraph 0105), a second floating diffusion region (Second Charge Storage Region 15b; see fig. 10A and paragraph 0105), and a second transfer transistor electrically connecting the second photoelectric conversion layer to the second floating diffusion region (Transfer transistor 16 connects the photodiode 10 to the floating diffusion region 15; see figs. 2, 10A and paragraphs 0062, 0102); and
a second semiconductor chip (see fig. 10A, section 5) configured to output a pixel signal based on the first photoelectric conversion layer and the second photoelectric conversion layer (Substrate 5 integrates logic circuits having functions such as image processing and signal processing, and processes a pixel signal and outputs an image; see figs. 3A, 10A and paragraphs 0065, 0096),
wherein the second semiconductor chip includes at least one transistor (Substrate 5 is provided with semiconductor layer 51 which is provided with a logic circuit transistor 52 made up of a plurality of logic transistors; see fig. 10A and paragraphs 0078, 0096),
wherein the first semiconductor chip (see fig. 10A; sections 1 and 3) comprises:
a first contact electrically connected to the first transfer transistor and extending in a Z-axis direction (Structure 16a connected to vertical gate 17a; see fig. 10A and paragraph 0104);
a second contact electrically connected to the second transfer transistor and extending in the Z-axis direction (Structure 16b connected to vertical gate 17b; see fig. 10A and paragraph 0105);
a plurality of third contacts (Via plugs 21a and 21b; see fig. 10A and paragraphs 0104-0105) electrically connected to each of the first floating diffusion region (Via plug 21a connected to first charge storage region 15a; see fig. 10A and paragraph 0104) and the second floating diffusion region (Via plug 21b connected to second charge storage region 15b; see fig. 10A and paragraph 0104), the plurality of third contacts extending in the Z-axis direction (see Via plugs 21a and 21b in fig. 10A); and
a first metal region configured to electrically connect the plurality of third contacts to one another and extending in an X-axis direction (Wiring layer 38a connecting via plugs 21a and 21b; see fig. 10A and paragraphs 0076, 0104, 0105), and wherein the first contact (Structure 16a; see fig. 10A), the second contact (Structure 16b; see fig. 10A), and the first metal region (Wiring layer 38a; see fig. 10A) contact a first surface of a first interlayer insulation layer that defines the first contact, the second contact, and the first metal region (Structures 16a, 16b and wiring layer 38a contacting interlayer insulation layers 20, 35 and 37; see fig. 10A and paragraphs 0076, 0099).
Regarding claim 8, Horikoshi discloses a stacked image sensor (see fig. 10A) comprising:
a first semiconductor chip (see fig. 10A; sections 1 and 3) including:
a first photoelectric conversion layer (First charge generation region 12a; see fig. 10A and paragraph 0104), a first floating diffusion region (First Charge Storage Region 15a; see fig. 10A and paragraph 0104), and a first transfer transistor electrically connecting the first photoelectric conversion layer to the first floating diffusion region (Transfer transistor 16 connects the photodiode 10 to the floating diffusion region 15; see figs. 2, 10A and paragraphs 0062, 0102); and
a second photoelectric conversion layer (Second charge generation region 12b; see fig. 10A and paragraph 0105), a second floating diffusion region (Second Charge Storage Region 15b; see fig. 10A and paragraph 0105), and a second transfer transistor electrically connecting the second photoelectric conversion layer to the second floating diffusion region (Transfer transistor 16 connects the photodiode 10 to the floating diffusion region 15; see figs. 2, 10A and paragraphs 0062, 0102);
a second semiconductor chip (see fig. 10A, section 5) configured to output a pixel signal based on the first photoelectric conversion layer and the second photoelectric conversion layer (Substrate 5 integrates logic circuits having functions such as image processing and signal processing, and processes a pixel signal and outputs an image; see figs. 3A, 10A and paragraphs 0065, 0096),
the second semiconductor chip including at least one transistor (Substrate 5 is provided with semiconductor layer 51 which is provided with a logic circuit transistor 52 made up of a plurality of logic transistors; see fig. 10A and paragraphs 0078, 0096); and
a third semiconductor chip including a circuit configured to process the pixel signal (Four or more layers can be laminated including circuits with a DRAM, a non-volatile memory, a MEMS; see paragraph 0101);
wherein the first semiconductor chip (see fig. 10A; sections 1 and 3) comprises:
a first contact electrically connected to the first transfer transistor and extending in a Z-axis direction (Structure 16a connected to vertical gate 17a; see fig. 10A and paragraph 0104);
a second contact electrically connected to the second transfer transistor and extending in the Z-axis direction (Structure 16b connected to vertical gate 17b; see fig. 10A and paragraph 0105);
a plurality of third contacts (Via plugs 21a and 21b; see fig. 10A and paragraphs 0104-0105) electrically connected with each of the first floating diffusion region (Via plug 21a connected to first charge storage region 15a; see fig. 10A and paragraph 0104) and the second floating diffusion region (Via plug 21b connected to second charge storage region 15b; see fig. 10A and paragraph 0104) and extending in the Z-axis direction (see Via plugs 21a and 21b in fig. 10A); and
a first metal region configured to electrically connect the plurality of third contacts to one another and extending in an X-axis direction (Wiring layer 38a connecting via plugs 21a and 21b; see fig. 10A and paragraphs 0076, 0104, 0105), and
wherein the first contact (Structure 16a; see fig. 10A), the second contact (Structure 16b; see fig. 10A), and the first metal region (Wiring layer 38a; see fig. 10A) contact a first surface of a first interlayer insulation layer that defines the first contact, the second contact, and the first metal region (Structures 16a, 16b and wiring layer 38a contacting interlayer insulation layers 20, 35 and 37; see fig. 10A and paragraphs 0076, 0099).
Allowable Subject Matter – Part I
8. Claims 16-20 are allowed.
9. The following is an examiner’s statement of reasons for allowance:
Regarding claim 16, the prior art does not teach or fairly suggest “…a first contact and a second contact are electrically connected to the first transfer transistor and the second transfer transistor, respectively, and extend in a Z-axis direction, wherein a height of the first contact and a height of the second contact are equal to a height of a first metal region that electrically connects a plurality of third contacts electrically to one another, the plurality of third contacts being connected to each of the plurality of floating diffusion regions and extending in the Z-axis direction, and wherein the first metal region extends in an X-axis direction…” and used in combination with all of the other limitations of claim 16.
Claims 17-20 depend on allowable claim 16. Therefore, the dependent claims are also held allowable.
Allowable Subject Matter – Part II
10. Claims 2-7 and 9-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
Regarding claim 2, the specific limitation of “the first contact, the second contact, the first metal region, and the plurality of third contacts comprise a same conductive material” in the combination as claimed is neither anticipated nor made obvious over the prior art made of record.
Regarding claim 3, it is objected to for depending on claim 2.
Regarding claim 4, the specific limitation of “the first semiconductor chip further comprises a second interlayer insulation layer disposed on the first surface of the first interlayer insulation layer, and wherein the second interlayer insulation layer comprises: a first via and a second metal region respectively connected to the first contact and the second contact; and a second via and a third metal region each connected to the first metal region” in the combination as claimed is neither anticipated nor made obvious over the prior art made of record.
Regarding claims 5-6, they are objected to for depending on claim 4.
Regarding claim 7, the specific limitation of “the second semiconductor chip further comprises a source follower transistor connected to the first floating diffusion region and the second floating diffusion region” in the combination as claimed is neither anticipated nor made obvious over the prior art made of record.
Regarding claim 9, the specific limitation of “the first contact, the second contact, the first metal region, and the plurality of third contacts comprise a same conductive material” in the combination as claimed is neither anticipated nor made obvious over the prior art made of record.
Regarding claim 10, the specific limitation of “the first semiconductor chip comprises a second interlayer insulation layer disposed on the first surface of the first interlayer insulation layer, and wherein the second interlayer insulation layer comprises: a first via and a second metal region respectively connected to the first contact and the second contact; and a second via and a third metal region each connected to the first metal region” in the combination as claimed is neither anticipated nor made obvious over the prior art made of record.
Regarding claims 11-15, they are objected to for depending on claim 10.
Regarding claim 12, the specific limitation of “the second semiconductor chip further comprises a source follower transistor connected to the first floating diffusion region and the second floating diffusion region, and wherein the third semiconductor chip comprises a plurality of logic circuits configured to control the source follower transistor” in the combination as claimed is neither anticipated nor made obvious over the prior art made of record.
Regarding claim 13, it is objected to for depending on claim 12.
Regarding claim 14, the specific limitation of “the first contact, the second contact, the first metal region, and the plurality of third contacts comprise tungsten” in the combination as claimed is neither anticipated nor made obvious over the prior art made of record.
Citation of Pertinent Art
11. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Lim et al. (US-PGPUB 2025/0006770) discloses the contact 140 may be connected to the connecting portion C of the vertical transfer gate 120 and may be electrically connected to a bonding pad 180 through the interconnection line 145.
Jang et al. (US-PGPUB 2024/0014243) discloses a transfer gate (TG) 440 extending in the third direction D3 through a lower portion of the third substrate 400 to contact the light sensing element 430 and having a lower portion protruding from the second surface 409 of the third substrate 400 downwardly that may be covered by the fourth insulating interlayer 500.
Nakagawa (US-PGPUB 2023/0326938) discloses the gate electrode of the vertical transistor 45 reaches the n-type semiconductor region 44 from the front surface of the semiconductor substrate 50, and is connected to the IR pixel drive circuit 102B via a wiring lines 65 and 66 formed in an interlayer insulating film 56. The floating diffusion region FD2 is connected to the source of the reset transistor 22 and the gate of the amplification transistor 23 via wiring lines 67 and 68 formed in the interlayer insulating film 56.
Lin et al. (US-PGPUB 2020/0381465) discloses the first vertical transfer gate 116c is configured to selectively form a first conductive channel between the photodetector 104 and the storage node 106, such that charges accumulated in the photodetector 104 (e.g., via absorbing the incident radiation) may be transferred to the storage node 106. The second vertical transfer gate 116d is configured to selectively form a second conductive channel between the storage node 106 and the floating diffusion node 108.
Cho et al. (US Patent 12,336,315) discloses the deep contact capacitor is a capacitor including a deep contact area that extends in the vertical direction and electrically connects the floating diffusion area to the metal pad of the floating diffusion node.
Contact Information
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CYNTHIA CALDERON whose telephone number is (571)270-3580. The examiner can normally be reached M-F 9:00 AM-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TWYLER HASKINS can be reached at (571)272-7406. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CYNTHIA CALDERON/Primary Examiner, Art Unit 2639 04/22/2026
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