Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claim 1 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a response to the first request" in line 10. There is insufficient antecedent basis for this limitation in the claim.
Claim 2 recites the limitation “issuing a second request to the first device at an address " in line 4. A second request is already recited in claim 1 and another second request is used in a claim 1, which lacks clarity
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Device discoverer in 1,2 4 is equivalent to Baseboard management controller 102 in 0023
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-5 of U.S. Patent No. 114095044. Although the claims at issue are not identical, they are not patentably distinct from each other because claim limitation of the instant application is anticipated by the reference patent.
Instant application
Reference patent 114095044
1. A baseboard management controller (BMC) mounted to a motherboard of a computing device, comprising: a device discoverer that: performs, based on a configuration schema specifying a first device associated with the motherboard and coupled to the BMC by a communication bus, a first discovery sequence over the communication bus to verify the first device, the first discovery sequence comprising: issuing a second request to the first device at an address indicated for the first device in the configuration schema, and waiting for a response to the first request; responsive to the discovery sequence being unsuccessful with respect to the first device, issues an error; and responsive to issuing the error, receives an updated configuration schema.
1. A method implemented by a baseboard management controller mounted to a motherboard, comprising: receiving, via a communication interface of the baseboard management controller, a configuration schema that specifies a plurality of devices associated with the motherboard and coupled to the baseboard management controller by a communication bus; determining that a digital signature associated with the configuration schema is valid and that the configuration schema is formatted in accordance with a predetermined formatting scheme; responsive to a determination that the digital signature is valid and the configuration schema is formatted in accordance with the predetermined formatting scheme, for each device of the plurality of devices, performing a discovery sequence over the communication bus based on the configuration schema to verify that the device is communicatively coupled to the baseboard management controller and to determine a property of the device; and responsive to verifying that the devices are communicatively coupled to the baseboard management controller, monitoring operation of the devices.
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2. The method of claim 1, wherein the configuration schema further specifies, for each device of the plurality of devices, at least one of: an address at which the device is located; an address at which one or more configuration registers of the device is located; an expected value for each of the one or more configuration registers; a communication protocol utilized by the device; or a physical location at which the device is located.
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3. The method of claim 2, wherein said performing comprises: for each device of the plurality of devices: transmitting a request to the device; receiving a response from the device; responsive to receiving the response from the device, reading contents of one or more configuration registers associated with the device; determining whether the contents of each of the one or more configuration registers match the expected value specified for each of the one or more configuration registers by the configuration schema; in response to determining that the content match, determining that the device is coupled to the baseboard management controller; and in response to determining that the contents do not match, providing an error signal indicating that the contents do not match.
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4. The method of claim 3, wherein the contents of the one or more configuration registers of the device specify the property of the device.
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5. The method of claim 3, further comprising: storing the contents of the one or more configuration registers in a sensor data record of the baseboard management controller.
6
3
9
8+9+10
10
9
15
15+16+17
Additionally Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 3 of U.S. Patent No. 12135975. Although the claims at issue are not identical, they are not patentably distinct from each other because claim limitation of the instant application is anticipated by the reference patent. Also, 9 is anticipated by 8 and 15 by 15 of the 15 of the reference patents
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 9 , 11, is/are rejected under 35 U.S.C. 103 as being unpatentable over ALVAREZ JANA [20200076690], in view of Remis et al [20180081849].
As to claim 1,
ALVAREZ JANA [20200076690] teaches A baseboard management controller (BMC) mounted to a motherboard of a computing device [0070: “0070 “the BMC 113 compares the identifier received over the communication bus cable 123 to the predefined identifier associated with the communication bus cable 123.”], comprising: a device discoverer that:
performs, based on a configuration schema specifying a first device associated with the motherboard and coupled to the BMC by a communication bus [0029: “Communication between the various components of the computing environment 100 may be enabled by one or more internal and/or external buses 160 (e.g. a PCI bus, universal serial bus, IEEE 1394 “Firewire” bus, SCSI bus, Serial-ATA bus, ARINC bus, etc.), to which the various hardware components are electronically coupled. ”], a first discovery sequence over the communication bus to verify the first device the first discovery sequence comprising: [0010: “determining, based on the plurality of object schemas, a common schema corresponding to the plurality of target networking devices; determining, based on the common schema, whether the desired configuration is valid for the plurality of target networking devices; in response to a determination that the desired configuration is valid for the plurality of target networking devices ”- networking devices are connected with the bus. Checking validity is equivalent to verifying. and 0043: “A valid configuration may set configurable attributes of the networking device within the predetermined boundaries corresponding to the driver. The schema class may comprise various attributes, such as a name attribute and/or a location attribute.” And [0037: “The networking device database 310 may indicate, for each networking device, one or more names, locations, addresses, configurations, model number, model type, operating system, services provided, drivers, driver versions, and/or other information corresponding to each networking device. The networking device database 310 may comprise information about networking devices within one physical location, such as a data center, or within multiple physical locations, such as multiple data centers.” And 0030: “The specific physical layer and the data link layer may provide a base for a full network protocol stack, allowing communication among small groups of computers on the same local area network (LAN) and large-scale network communications through routable protocols, such as Internet Protocol (IP).”],
But, does not explicitly teach waiting for the request.
However, Remis et al [20180081849] teaches issuing a second request to the first device at an address indicated for the first device in the configuration schema, and waiting for a response to the first request [0077: “the identifier module 310 writes the installation location identifier for an install location of a peripheral device 114, e.g., the slot ID and bay ID, to a storage location associated with each bay 121 and/or slot 117. In one embodiment, the storage location includes a register, a cache, a nonvolatile memory device, a volatile memory device, or the like. For example, each drive bay 121 may have an associated register for storing data associated with the drive bay 121, such as a bay ID and/or a slot ID of the communication bus cable slot 117 for the communication bus cable 123 that should be communicatively coupled to the peripheral device 114 at the install location. The SEP 115 may read the bay ID and/or slot ID from the register when it is requested from the FPGA 204.”and 0058: “A processing unit 202 may send various commands, data, instructions, and/or the like to the peripheral devices 114 using the communication buses 123 and/or the data buses 216, 116. For example, a processing unit 202 may send a read request command, a write request command, or the like to an NVMe peripheral storage device located at slot ID 10 and bay ID 62 on the backplane 122.”];
responsive to the discovery sequence being unsuccessful with respect to the first device, issues an error; and responsive to issuing the error, receives [0077: “The method 500 compares 508 the identifier received over the communication bus cable 123 to a predefined identifier associated with the communication bus cable 123. The method 500 determines 510 whether the identifier that is received over the communication bus cable 123 matches the predefined identifier for the communication bus cable 123. If not, the method 500 sends 512 a notification that indicates that the communication bus cable 123 is communicatively coupled to an incorrect, erroneous, or not recommended peripheral device 114. ” and 0086]. ”- erroneous notification is received]. an updated configuration schema The SEP 115 may read the bay ID and/or slot ID from the register when it is requested from the FPGA 204.” And 0078: “The identifier module 310 may read the install location identifiers from the SEP 115, the FPGA 204, the BMC 113, or the like, and write the received install location identifiers to the registers, or other storage location, associated with each install location on the backplanes 122.”]
It would have been obvious to person of ordinary skill in the art before the effective filing date of the claimed invention to combine teaching of ALVAREZ JANA and Remis because both are directed toward configuration of the devices. ALverez teaches receiving the configuration via network, in addition to that Remis teaches requesting configurations. The teaching of receiving configuration can be combined in Alveris such that the system the ALveris can distribute configuration directly received configuration to coupled devices for updating valid devices with readily available configuration data.
As to claim 9,
Combination of ALVAREZ and Remis teach this claim according to the reasoning set forth in claim 1 supra.
As to claim 11,
Remis teaches said issuing the error comprises: issuing the error responsive to failure to receive the response after a predetermined period of time [0078: “The SEP 115 may read the bay ID and/or slot ID from the register when it is requested from the FPGA 204.” And 0078: “The identifier module 310 may read the install location identifiers from the SEP 115, the FPGA 204, the BMC 113, or the like, and write the received install location identifiers to the registers, or other storage location, associated with each install location on the backplanes 122.”]
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15, 16 is/are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Satyanarayana [10242176]
As to claim 15,
Sathyanarayana [10242176] teaches A system comprising: a baseboard management controller (BMC) mounted to a motherboard of a computing device[Fig. 1: BMC 120 ], the BMC: validates a digital signature associated with a configuration schema that specifies a first device associated with the motherboard and coupled to the BMC by a communication bus [Fig. 12: strep 1210] ; responsive to validation of the digital signature[Fig. 12, step 1230], issues a first request to the first device based on the configuration schema [Fig. 13: step 1310]; verifies the first device based on a response to the first request; and responsive to the verification of the first device[fig. 13, step 1230], monitors operation of the first device [Fig. 13: step 1350- when communication exchanged and data shared, monitoring happens , also fig.12: step 1260, device is owned and information is shared, monitoring happens ].
As to Claim 16,
Sathyanarayana teaches the BMC: determines the configuration schema is formatted in accordance with a predetermined formatting scheme [Fig.10, step 1040: mctp control commands]
Allowable Subject Matter
Claim 2-8, 10, 17-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KESHAB R PANDEY whose telephone number is (571)270-0176. The examiner can normally be reached Monday-Friday 9:00-5:00(ET).
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/KESHAB R PANDEY/Primary Examiner, Art Unit 2176
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