DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 1 (and by virtue of dependence claims 2-4) requires that the ground of a reference circuit is connected to the external ground terminal via a first individual transistor but is not connected to the internal ground line.
Applicant’s Specification teaches that:
“the ground side of the reference circuit 16 is not directly connected to the lower line SUB, but is connected to the input terminal 12b via the n-channel first individual transistor M7. The gate of the first individual transistor M7 is connected to the gate of the transistor M4, and the first individual transistor M7 is turned on/off similarly to the transistor M4, and bypasses the transistor M4 to connect the ground of the reference circuit 16 to the input terminal 12b” [25].
However, looking at Applicant’s Figures 1-2, since M4 and M7 are both depicted as NMOS and both receive the same signal at their gate terminals, it is understood that they will substantially conduct simultaneous to one another. When both M4 and M7 are on, the internal ground line (SUB) is connected to the external ground line (GND) and the ground of the reference circuit is connected to the external ground line through M7.
Thus, it is not understood how M4 is bypassed “to connect the ground of the reference circuit 16 to the input terminal 12b” as cited above or how Applicant’s Figures teach the claimed limitation “wherein the ground of the reference circuit is connected to the external ground terminal via a first individual transistor but is not connected to the internal ground line” since both the internal ground line and the ground of the reference circuit are connected to the external ground line when M4 and M7 are on.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2836