DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 2 is objected to because of the following informalities: “further having an ADC that performs an AD conversion” should be “further having an analog-to-digital converter (ADC) that performs an analog-to-digital conversion.” Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishii et al (US 2016/0187020) in view of Ramaraju et al (US 2011/0296211).
For claim 1, Ishii teaches:
an external power supply (2, 54, 63, 64, 65) supplying power (output of 65) to an internal block (67, [0029]);
an external ground terminal (bottom terminal of 67), to which the ground of the external power supply is connected (as understood by examination of Figure 2);
a rectifying element (63), which makes a current flow toward the external ground terminal (as understood by examination of Figure 2).
Ishii fails to teach an internal power supply line, internal ground line and the reference circuit as claimed.
It is noted that Ishii’s regulator 65 supplies a regulated DC supply voltage to a processor 67 ([0029]).
However, Ramaraju teaches a semiconductor integrated circuit (Figure 1 and [0017]), which has an internal power supply line (VDD line) that outputs an internal power supply voltage (VDD), and in which an internal block (18) is connected to the internal power supply line (as understood by examination of Figure 1), the semiconductor integrated circuit comprising:
an internal ground line (VVSS), which is the ground of the internal power supply line (as understood by examination of Figure 1);
an external ground terminal (VSS), to which the ground of the external power supply is connected;
a reference circuit (30), which generates a reference voltage (voltage supplied to the gate of 26);
wherein the ground of the reference circuit is connected to the external ground terminal via a first individual transistor (32).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to supply power to Ramaraju’s processor (VDD and VSS of Figure 1) using Ishii’s AC-to-DC converter with voltage regulation (2, 54, 63, 64, 65 of Figure 2) since they both relate to providing external power to a processor.
Furthermore, the particular known technique of using an AC-to-DC converter with voltage regulation to provide a DC supply voltage to a circuit was recognized as part of the ordinary capabilities of one skilled in the art, as evidenced by Ishii.
The combination of Ishii and Ramaraju teaches a semiconductor integrated circuit (Figure 1, Rararaju), which has an internal power supply line (VDD line) that outputs an internal power supply voltage generated based on an external power supply (input to Ishii’s 63), and in which an internal block (18) is connected to the internal power supply line (as understood by the combination of references), the semiconductor integrated circuit comprising:
an internal ground line, which is the ground of the internal power supply line (VVSS, Ramaraju);
an external ground terminal (VSS, Ramaraju), to which the ground of the external power supply is connected (as understood by the combination of references);
a rectifying element (63, Ishii), which is disposed between the internal ground line and the external ground terminal (as understood by the combination of references) and makes a current flow toward the external ground terminal (as understood by the combination of references); and
a reference circuit (30, Ramaraju), which generates a reference voltage (voltage supplied to the gate of 26);
wherein the ground of the reference circuit is connected to the external ground terminal via a first individual transistor (32, as understood by the combination of references).
For claim 3, combination of Ishii and Ramaraju as cited above teaches the limitations of claim 1 and Ramaraju further teaches:
a connection point between the ground line and the first individual transistor (node commonly coupled to the bottom terminals of 32 and 34) and the ground of the internal power supply line (VVSS) are connected by a bidirectional (via 34) circuit (34, 36), and when a power supply voltage is applied to the external ground terminal and the first individual transistor is off, the ground of the internal power supply line is connected to an external power supply terminal (as understood by examination of Figure 1 and by [0029]-[0030]).
For claim 4, combination of Ishii and Ramaraju as cited above teaches the limitations of claim 1 and Ishii further teaches:
the external power supply terminal (input to 63) and the internal power supply line are connected via a rectifying circuit (63, 64), and the rectifying element is included in the rectifying circuit (as understood by examination of Figure 2 and [0029]).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishii, Ramaraju and Dayel et al (US 2019/0324298).
For claim 2, the combination of Ishii and Ramaraju as cited above teaches the limitations of claim 1 but fails to teach an ADC as claimed.
However, Dayel teaches a processor (816, Figure 8) comprising an analog to digital converter (820).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement Ramaraju’s functional block 12 using an ADC since Ramaraju teaches that “functional block 12 can be any type of circuit” ([0027]) and Dayel teaches that processors are known to comprise ADCs.
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention.
The combination of Ishii, Ramaraju and Dayel as cited above teaches:
an ADC (12, Ramaraju) that performs an AD conversion with reference to the reference voltage (based on whether low power mode is active, [0030]), wherein the ground of the ADC is connected to the external ground terminal via a second individual transistor (via 28 during normal operation, [0029]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2849