Prosecution Insights
Last updated: August 06, 2026
Application No. 18/886,019

SEMICONDUCTOR INTEGRATED CIRCUIT

Final Rejection §112
Filed
Sep 16, 2024
Priority
May 24, 2024 — JP 2024-085165
Examiner
PUENTES, DANIEL CALRISSIAN
Art Unit
2849
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Will Semiconductor (Shanghai) Co. Ltd.
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
2m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
825 granted / 931 resolved
+20.6% vs TC avg
Minimal +3% lift
Without
With
+3.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
18 currently pending
Career history
952
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
41.7%
+1.7% vs TC avg
§102
32.8%
-7.2% vs TC avg
§112
18.4%
-21.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 931 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 1-4 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-4 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claim 1 (and by virtue of dependence claims 2-4) requires that the ground of a reference circuit is connected to the external ground terminal via a first individual transistor but is not connected to the internal ground line. Applicant’s Specification teaches that: “the ground side of the reference circuit 16 is not directly connected to the lower line SUB, but is connected to the input terminal 12b via the n-channel first individual transistor M7. The gate of the first individual transistor M7 is connected to the gate of the transistor M4, and the first individual transistor M7 is turned on/off similarly to the transistor M4, and bypasses the transistor M4 to connect the ground of the reference circuit 16 to the input terminal 12b” [25]. However, looking at Applicant’s Figures 1-2, since M4 and M7 are both depicted as NMOS and both receive the same signal at their gate terminals, it is understood that they will substantially conduct simultaneous to one another. When both M4 and M7 are on, the internal ground line (SUB) is connected to the external ground line (GND) and the ground of the reference circuit is connected to the external ground line through M7. Thus, it is not understood how M4 is bypassed “to connect the ground of the reference circuit 16 to the input terminal 12b” as cited above or how Applicant’s Figures teach the claimed limitation “wherein the ground of the reference circuit is connected to the external ground terminal via a first individual transistor but is not connected to the internal ground line” since both the internal ground line and the ground of the reference circuit are connected to the external ground line when M4 and M7 are on. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL C PUENTES/Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Sep 16, 2024
Application Filed
Jan 21, 2026
Non-Final Rejection mailed — §112
Apr 10, 2026
Response Filed
Jun 03, 2026
Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12699010
TEMPERATURE SENSOR AND CIRCUIT
2y 9m to grant Granted Aug 04, 2026
Patent 12700861
GATE DRIVER CIRCUIT CAPABLE OF PREVENTING SPIKES
2y 1m to grant Granted Aug 04, 2026
Patent 12695448
POWER SEMICONDUCTOR MODULE
2y 0m to grant Granted Jul 28, 2026
Patent 12695442
ISOLATED TYPE ACTIVE EMI FILTER HAVING NO ADDITIONAL ELEMENTS ON POWER LINE
1y 11m to grant Granted Jul 28, 2026
Patent 12683615
TUNABLE DIGITALLY CONTROLLED OSCILLATOR
2y 1m to grant Granted Jul 14, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
92%
With Interview (+3.1%)
2y 1m (~2m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 931 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month