DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 11-12, 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fukuzumi et al (US 2018/0374864).
Regarding Claim 1, Fukuzumi et al discloses a memory device (semiconductor memory device [0024] Fig 9), comprising:
a stack (stacked body [0033] Fig 9) including conductive layers (electrode layer WL [0033] Fig 9) and first dielectric layers (insulating layers 40 [0033] Fig 4 and Fig 9) alternately stacked in a first direction (vertical y direction Fig 9);
an insulating layer (insulating film 45 [0034] Fig 9) and a first semiconductor layer (layer that includes back gate BG which comprises silicon as a main component [0035] Fig 9) located on a first side of the stack (top side of the stack shown in Fig 9) in a first direction (vertical y direction Fig 9), and
the first semiconductor layer (layer that includes BG Fig 9) is between the insulating layer (45 Fig 9) and the stack (shown in Fig 9);
a second dielectric layer (interlayer insulating layer 69 [0065] Fig 9) adjacent to the stack (shown in Fig 9) in a second direction (horizontal x direction Fig 9) perpendicular to the first direction (vertical y direction Fig 9), wherein the first semiconductor layer (layer that includes BG Fig 9) is between the insulating layer (45 Fig 9) and second dielectric layer (69 Fig 9) in the first direction (vertical y direction Fig 9);
a recessed structure (structure that is in via 95 [0103] Fig 7 shown in Fig 9) extending through the insulating layer (45 Fig 9) and the first semiconductor layer (layer that includes BG Fig 9) in the first direction (vertical y direction Fig 9);
one or more contact pads (pad 70 [0081] Fig 7 and pad 122 [0121] Fig 9) disposed at a bottom of the recessed structure (structure that is in via 95 Fig 7 shown in Fig 9); and
one or more conductive contact structures (external connection electrode 121 [0122] Fig 9) surrounded by the second dielectric layer (69 Fig 9), wherein the one or more conductive contact structures (121 Fig 9) are connected to the one or more contact pads (70 Fig 7 and 122 Fig 9).
Regarding Claim 2, Fukuzumi et al discloses the limitations of claim 1 as explained above. Fukuzumi et al further discloses
wherein: a bottom and side walls of the one or more contact pads (70 Fig 7 and 122 Fig 9) are surrounded by a first dielectric layer (insulating layers 40 [0033] Fig 4 and Fig 9).
Regarding Claim 3, Fukuzumi et al discloses the limitations of claim 1 as explained above. Fukuzumi et al further discloses
wherein: the stack (shown in Fig 9) spaced apart from the one or more conductive contact structures (121 Fig 9) in the second direction (horizontal x direction Fig 9).
Regarding Claim 5, Fukuzumi et al discloses the limitations of claim 1 as explained above. Fukuzumi et al further discloses
wherein: the one or more conductive contact structures (121 Fig 9) extend along the first direction (vertical y direction Fig 9), and in the first direction (vertical y direction Fig 9),
a length of the one or more conductive contact structures (121 Fig 9) is greater than a length of the stack (shown in Fig 9) (it can be observed that the overall length of the contact structure 121 in the vertical y direction shown in Fig 9 is greater than the length of the WL stack in the vertical y direction shown in Fig 9).
Regarding Claim 11, Fukuzumi et al discloses the limitations of claim 1 as explained above. Fukuzumi et al further discloses
wherein: the one or more contact pads (pad 70 [0081] Fig 7 and pad 122 [0121] Fig 9) are disposed below a level of the insulating layer (insulating film 45 [0034] Fig 9).
Regarding Claim 12, Fukuzumi et al discloses the limitations of claim 1 as explained above. Fukuzumi et al further discloses
wherein: a bottom surface of the recessed structure (structure that is in via 95 [0103] Fig 7 shown in Fig 9) is at a level of the first semiconductor layer (layer that includes back gate BG which comprises silicon as a main component [0035] Fig 9) or below a level of the first semiconductor layer (layer that includes back gate BG which comprises silicon as a main component [0035] Fig 9).
Regarding Claim 15, Fukuzumi et al discloses the limitations of claim 1 as explained above. Fukuzumi et al further discloses
further comprising: one and more first connecting pads (interconnection layers 73 [0074] and pad 122 [0121] Fig 9) located at a second side opposite to the first side of the stack (shown in Fig 9), wherein a first end and a second end of the one or more conductive contact structures (121 Fig 9) are connected to the one or more contact pads (pad 70 [0081] Fig 7 and pad 122 [0121] Fig 9) and the one or more first connecting pads (73 and 122 Fig 9) respectively.
Regarding Claim 16, Fukuzumi et al discloses the limitations of claim 15 as explained above. Fukuzumi et al further discloses
further comprising: a peripheral circuit (circuit chip 200 [0073] Fig 9) and one or more second connecting pads (interconnection layers 76 [0076] Fig 9) located between the peripheral circuit (200 Fig 9) and the one or more first connecting pads (73 and 122 Fig 9), the one or more first connecting pads (73 and 122 Fig 9) being in contact with the one or more second connecting pads (73 and 122 Fig 9).
Regarding Claim 17, Fukuzumi et al discloses
a method for fabricating (method for manufacturing [0011]) a memory device (semiconductor memory device [0024] Fig 9), comprising:
providing an array device (an array chip [0024]) including a stack (shown in Fig 9), an insulating layer (insulating film 45 [0034] Fig 9), a first semiconductor layer (layer that includes back gate BG which comprises silicon as a main component [0035] Fig 9), and a second dielectric layer (interlayer insulating layer 69 [0065] Fig 9),
wherein the insulating layer (45 Fig 9) and the first semiconductor layer (layer that includes BG Fig 9) are located on a first side of the stack (top side of the stack shown in Fig 9) in a first direction (vertical y direction Fig 9), and
the second dielectric layer (interlayer insulating layer 69 [0065] Fig 9) is adjacent to the stack (shown in Fig 9) in a second direction (horizontal x direction Fig 9) perpendicular to the first direction (vertical y direction Fig 9);
forming a recessed structure (structure that is in via 95 [0103] Fig 7 shown in Fig 9) extending through the insulating layer (45 Fig 9) and the first semiconductor layer (layer that includes BG Fig 9) in the first direction (vertical y direction Fig 9);
forming one or more contact pads (pad 70 [0081] Fig 7 and pad 122 [0121] Fig 9) disposed at a bottom of the recessed structure (structure that is in via 95 Fig 7 shown in Fig 9); and
forming one or more conductive contact structures (external connection electrode 121 [0122] Fig 9) surrounded by the second dielectric layer (69 Fig 9) in the second direction (horizontal x direction Fig 9) are connected to the one or more contact pads (pad 70 Fig 7 and 122 Fig 9).
Regarding Claim 18, Fukuzumi et al discloses the limitations of claim 17 as explained above. Fukuzumi et al further discloses
further comprising: forming one and more first connecting pads (interconnection layers 73 [0074] and pad 122 [0121] Fig 9) located at a second side opposite to the first side of the stack (shown in Fig 9), and
a first end and a second end of the one or more conductive contact structures (external connection electrode 121 [0122] Fig 9) are connected to the one or more contact pads (pad 70 [0081] Fig 7 and pad 122 [0121] Fig 9) and the one or more first connecting pads (73 and 122 Fig 9) respectively.
Regarding Claim 19, Fukuzumi et al discloses the limitations of claim 18 as explained above. Fukuzumi et al further discloses
further comprising: bonding the one or more of first connecting pads (73 and 122 Fig 9) with one or more second connecting pads (interconnection layers 76 [0075] Fig 9) of a peripheral structure (200 Fig 9).
Regarding Claim 20, Fukuzumi et al discloses the limitations of claim 19 as explained above. Fukuzumi et al further discloses
wherein: bonding (it can be observed in the combination of Fig 7 and Fig 9 that pads are bonded before the conductive contact structure 121 Fig 9 is formed) the one or more of first connecting pads (73 and 122 Fig 9) with one or more second connecting pads (76 Fig 9) of a peripheral structure (200 Fig 9) before forming a recessed structure (structure that is in via 95 [0103] Fig 7 shown in Fig 9) extending through the insulating layer (45 Fig 9) and the first semiconductor layer (layer that includes back gate BG which comprises silicon as a main component [0035] Fig 9) in the first direction (vertical y direction Fig 9).
Allowable Subject Matter
Claims 4, 6-10, and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4:
Regarding Claim 4, Fukuzumi et al discloses the limitations of claim 1 as explained above.
The reason for the indication of allowability of Claim 4 is the inclusion of
wherein: the one or more contact pads are between the recessed structure and the one or more conductive contact structures in the first direction; and the recessed structure overlaps with at least two conductive structures in the first direction.
Specifically, based on the interpretation used in Claim 1, the recess structure (structure that is in via 95 [0103] Fig 7 shown in Fig 9) of Fukuzumi et al occupies the same space as the one or more conductive contact structures (121 Fig 9), and would make it unreasonable to meet this claim limitation. Further, should another reference be found that includes this limitation, it would not be obvious to a person of ordinary skill in the art to combine the references and modify Fukuzumi et al to include this feature.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 6:
Regarding Claim 6, Fukuzumi et al discloses the limitations of claim 1 as explained above.
The reason for the indication of allowability of Claim 6 is the inclusion of
further comprising: a second semiconductor layer located between the stack and the first semiconductor layer.
Specifically, although Fig 8 of Fukuzumi et al discloses a metal silicide layer (110 [0117]) above the first semiconductor layer (layer that comprises BG Fig 9), the metal silicide layer 110 is not in the required location, and it is absent in the embodiment of Fig 9. Additionally, a person of ordinary skill in the art would not be motivated to modify Fukuzumi et al to include this limitation. Further, should another prior art reference be found that includes this feature, it would not be obvious to a person of ordinary skill in the art to combine the references and modify Fukuzumi et al to include this feature.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claims 7-10 would be allowable based on their dependency on Claim 6.
Claim 13:
Regarding Claim 13, Fukuzumi et al discloses the limitations of claim 1 as explained above.
The reason for the indication of allowability of Claim 13 is the inclusion of
wherein: the insulating layer includes a first portion and a second portion arranged in a third direction parallel to the second direction, and the recessed structure is located between the first portion and the second portion.
Specifically, Fukuzumi et al does not disclose these claim limitations and should a secondary reference be found that does disclose these features, it would not be obvious to a person of ordinary skill in the art to combine the references and modify Fukuzumi et al to includes these features.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 14 would be allowable based on its dependency on Claim 13.
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al (US 2019/0221557) which discloses a 3D NAND stacked memory device [0003], and Baek et al (US 2019/0304992) which discloses a 3D NAND device [0020].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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