DETAILED ACTION
This is a first office action in response to application 18/886,109 originally filed 09/16/2024. The response filed 07/21/2026, in which claims 1, 2, 4, 19, 20 are amended, claims 5-8, 18 are cancelled, and claims 21-25 is hereby acknowledged. The Office notes that the claims are subject to the restriction set forth on 05/12/2025 in which Applicant as elected Species A in the reply filed 07/07/2025. Originally, claims 3 and 5 were withdrawn.
Currently claims 1-4 and 9-25 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Amended and newly submitted claims 2, 4, 21-25, are directed to a non-elected species that is independent or distinct from the invention originally claimed for the following reasons: The amendments to the claims suggest, alternatively that the bias module is multiplexed from at least one of a reset module, a data-writing module, or an initialization module of the pixel circuit, additional bias stages and circuit connection configurations. The scope of the claims looks as an attempt to cover alternative embodiments that were not elected in the original requirement. The Office notes that only Species A was elected and that alternatives (e.g. fifth interval stage, double gate transistor, bias module being multiplexed with the data writing module Fig. 10-12 [0106-0107] etc.) are expressly discussed in the disclosure as being directed to a non-elected embodiment. Applicant is requested to cancel all claims not directed to the elected species and amend Claims consistent only with the elected species A.
Accordingly, claims 2-4 and 22-25 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
Currently claims 1 and 9-20 are pending.
Response to Arguments
Applicant's arguments filed 07/21/2026 have been fully considered but they are not persuasive.
Applicant asserts the amendments to the claims overcomes the prior art however The Office respectfully disagrees. Applicant appears to readily admit that the “Lin discloses a gate voltage setting transistor Tgd coupled in a diode-connected configuration between the gate and drain terminals of Tdrive”, however further asserts that the transistor Tgd is not a compensation transistor. The Office respectfully disagrees with these assertions. In the example of FIG. 5B, the Vth sampling and data programming phase of t3-t4 provides this functionality. Applicant’s independent claims simply suggest that these elements exist without expressly stating how they function assuming the function would be different.
Applicant further asserts that Lin nor Sang teach an NMOS drive or compensation transistor. Given that Lin teaches the exact same transistor configuration and circuit elements connected between each other as seen in Applicants’ elected embodiment, it’s clear that Lin in Figure 5A (see below) teaches NMOS transistor for both the equated driving transistor and compensation transistor.
Applicants remaining arguments assert that the teachings of Sang “The voltage transition in Sang is in the opposite direction (low to high) relative to the claimed invention (high to low), and the transistor polarity is opposite (PMOS versus NMOS),” however The Office respectfully disagrees. As was noted in the prior action, and acknowledged by Applicant, the driving transistor used in Sang is pmos (while an nmos is expressly taught in Lin and not acknowledged by Applicant). To provide the same functionality as that which is claimed (i.e. “the driving transistor is reversely biased”), Sang provides a high voltage named V1_H, (not low as expressly shown in Figure 3I in both drawings), to the drain of the driving transistor. Given the connection and specifically the type of applied voltage, this creates the reverse biasing of the driving transistor using a high voltage instead of low voltage. In short, while the direction of the current maybe different, the effect is the same. Applicants have claimed to perform the same function, just in the opposite way (as was acknowledged in the prior action). In addition, the equated compensation transistor T1 in Sang, is not turned on during the equated periods. Notably, there is not a need to expressly call one or more of the horizontal periods in Sang a specific name or give it a specific label. The transitioning of the periods as shown performs the claimed function. This is clearly evident by the timing diagram associated with Figure 3I and a marked up version providing the portions equated to the these period is reproduced below for convenience.
In regards to new claims 21-25, The Office notes again that claim 21-25 recite language and/or are dependent from a non-elected base claim and find support within the paragraphs of a non-elected species specifically with respect to Figures 10-12. Applicant is remined the claims are subject to the restriction set forth on 05/12/2025 in which Applicant as elected Species A in the reply filed 07/07/2025. For these reasons, the claims must be withdrawn as being directed to a non-elected species.
Therefore, after review, Applicants arguments are not found persuasive and the rejections will be currently maintained.
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Lin Sang
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1 and 9-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. U.S. Patent Application Publication No. 2023/0035245 A1 as applied to claim 1 above, and further in view of Sang et al. U.S. Patent Application Publication No. 2022/0059036 A1 hereinafter Sang.
Consider Claim 1:
Lin discloses a display panel, comprising: (Lin, See Abstract.)
a pixel circuit and a light emitting element, (Lin, [0034], “FIG. 2 is a diagram of an illustrative display such as an organic light-emitting diode display 14 having an array of organic light-emitting diode display pixels 22. As shown in FIG. 2, display 14 may have one or more layers such as substrate 24. Layers such as substrate 24 may be formed from planar rectangular layers of material such as planar glass layers. Display 14 may have an array of display pixels 22 for displaying images for a user. The array of display pixels 22 may be formed from rows and columns of display pixel structures on substrate 24. These structures may include thin-film transistors such as polysilicon thin-film transistors, semiconducting-oxide thin-film transistors, etc. There may be any suitable number of rows and columns in the array of display pixels 22 (e.g., ten or more, one hundred or more, or one thousand or more).”)
wherein: the pixel circuit comprises a driving module, a data writing module, a compensation module, and a first light emitting control module; the driving module comprises a driving transistor, wherein the driving transistor is an NMOS transistor; the data writing module is connected between a data signal input end and a first electrode of the driving transistor and is used for providing a data signal for the driving transistor; and the first light emitting control module is connected between a first power supply signal end and a second electrode of the driving transistor and is used for providing a first power supply signal for the driving transistor, (Lin, [0069], “FIG. 5A is a circuit diagram showing yet another suitable implementation of display pixel 22 having at least two initialization transistors. As shown in FIG. 5A, pixel 22 may include transistor Tem1, transistor Tdrive, transistor Tem2, and diode 304 coupled in series between power supply terminals 300 and 302. Storage capacitor Cst1 may be coupled between Node2 and the anode terminal of diode 304. Transistor Tgd that is controlled by signal SCAN1(n) on scan line 314-1 may be coupled across Node1 and Node2. Transistor Tdata that is controlled by signal SCAN2(n) on scan line 314-2 may be coupled to Node3. Pixel 22 may include a first initialization transistor Tini1 coupled to the anode terminal of diode 304. In the example of FIG. 5A, transistors Tgd, Tdrive, and Tini1 may all be implemented as semiconducting-oxide transistors (see transistors surrounded by circles) while all remaining transistors are implemented as p-type silicon transistors. This configuration is, however, merely illustrative. In general, any portion of pixel 22 of FIG. 5A may be implemented as semiconducting-oxide transistors and/or n-type/p-type silicon transistors.”)
wherein an operation of the pixel circuit comprises at least one bias stage, and during a bias stage of the at least one bias stage, the driving transistor receives a bias signal. (Lin, [0073], [0070], “Second initialization transistor Tini2 may be a p-type silicon transistor like the rest of the silicon transistors within the pixel and may be controlled by signal SCAN2(n−1) routed from an immediately preceding pixel row via routing path 314-2′. Signal SCAN2(n−1) can be pulsed low during the non-emission phase to help set Node1 to VDDEL during the initialization/anode reset phase. One such way of operating pixel 22 of FIG. 5A is illustrated in the timing diagram of FIG. 5B.”)
the compensation module is turned off during the bias stage, and (Lin, [0072], “At time t3, signal SCAN2(n) is pulsed low, which turns on transistor Tdata to load in a desired data value D(n) onto Node3. Since signal SCAN1(n) remains high during this time, the drive transistor remains in the diode-connected configuration, so both data signal Vdata and the drive transistor threshold voltage Vth will be sampled onto the storage capacitor Cst1.”)
Lin however does not appear to further specify wherein the operation of the pixel circuit further comprises a non-bias stage, during the non-bias stage, the bias signal provides a first bias signal, and during the bias stage, the bias signal provides a second bias signal, wherein a voltage of the second bias signal is lower than a voltage of the first bias signal.
Sang however teaches that it was a known technique in the art to use different bias voltages in different periods for biasing the driving transistor and therefore teaches a data writing module, a compensation module, and a first light emitting control module; the driving module comprises a driving transistor, wherein the driving transistor is an NMOS transistor; (Sang, [0056] Each of the transistors DT and T1 to T6 may be a PMOS transistor or an NMOS transistor.” See also at least Figure 3I items T1, DT V1_H)
the driving transistor receives a bias signal, and the compensation module is turned off during the bias stage, (Sang, [0096], “In FIG. 3I, as the fifth transistor T5 is turned on, the voltage of the first electrode of the driving transistor DT connected to the second node N2 increases to the voltage V1_H. Here, the voltage Vgs between the gate and the source of the driving transistor DT is Vgs=V.sub.DATA(n)−|Vth|−V1_H. That is, the driving transistor DT maintains a stronger saturation. Also, as the sixth transistor T6 is turned on, the pixel electrode (or anode electrode) of the electroluminescent device ELD is initialized to the second bias voltage V2. The voltage of the gate electrode of the driving transistor DT connected to the first node N1 maintains V.sub.DATA(n)−|Vth|.”)
wherein the operation of the pixel circuit further comprises a non-bias stage, during the non-bias stage, the bias signal provides a first bias signal, and during the bias stage, the bias signal provides a second bias signal, wherein a voltage of the second bias signal is lower than a voltage of the first bias signal, (Sang, [0056], [0081-0100], [0103-0106], [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown. The light emission signal EM represents a high voltage, and the third and fourth transistors T3 and T4 are turned off. The first voltage is represented as V1_L, and the second voltage is represented as V1_H. The V1_H is higher than the V1_L, and it is preferable that the V1_H is higher than the data voltage V.sub.DATA. The first scan signal SC1(n) is a low voltage and the first transistor T1 is turned off. The second and third scan signals SC2(n) and SC3(n) are high voltages, and the second, fifth, and sixth transistors T2, T5, and T6 are turned off. The voltage of the gate electrode of the driving transistor DT connected to the first node N1 is V.sub.DATA(n−1)−|Vth|, that is, a difference between the data voltage V.sub.DATA(n−1) of the previous frame n−1 and the threshold voltage Vth of the driving transistor DT.”)
so that the driving transistor is reversely biased, and wherein before the bias stage, the bias signal is converted from the first bias signal to the second bias signal, and (Sang, [0081-0102], See Figures 3A-C and 3H-J. [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown.”)
after a first interval stage provided to deal with a delay of a rising edge or a falling edge of the bias signal, the bias stage begins, wherein during the first interval stage, the bias signal provides the second bias signal but the driving transistor does not receive the second bias signal until the first interval stage ends. (Sang, [0081-0100], [0083], “In FIG. 3B, the low second scan signal SC2(n) is input, and the fifth and sixth transistors T5 and T6 are turned on. As the fifth transistor T5 is turned on, the first bias voltage V1 (V1_H) is applied to the first electrode of the driving transistor DT connected to the second node N2. The voltage of the first electrode of the driving transistor DT connected to the second node N2 increases to the voltage V1_H. The driving transistor DT may be a PMOS transistor, and in this case, the first electrode may be a source electrode.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide a first and second bias signal to the driving transistor over different periods as taught in Sang as this was a known technique in view as taught by Sang and would have been used for the purpose of so that the hysteresis of the driving transistor can be reduced. (Sang, [0084])
Consider Claim 9:
Lin in view of Sang disclose the display panel according to claim 8, wherein at the end of the bias stage, the bias signal remains the second bias signal, which, after a second interval stage, is converted into the first bias signal. (Sang, [0103-0106], [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown. The light emission signal EM represents a high voltage, and the third and fourth transistors T3 and T4 are turned off. The first voltage is represented as V1_L, and the second voltage is represented as V1_H. The V1_H is higher than the V1_L, and it is preferable that the V1_H is higher than the data voltage V.sub.DATA. The first scan signal SC1(n) is a low voltage and the first transistor T1 is turned off. The second and third scan signals SC2(n) and SC3(n) are high voltages, and the second, fifth, and sixth transistors T2, T5, and T6 are turned off. The voltage of the gate electrode of the driving transistor DT connected to the first node N1 is V.sub.DATA(n−1)−|Vth|, that is, a difference between the data voltage V.sub.DATA(n−1) of the previous frame n−1 and the threshold voltage Vth of the driving transistor DT.”)
Consider Claim 10:
Lin in view of Sang disclose the display panel according to claim 8, wherein a duration of the first interval stage is shorter than a duration of the bias stage; or a duration the second interval stage is shorter than a duration of the bias stage. (Sang, [0103-0106], [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown. The light emission signal EM represents a high voltage, and the third and fourth transistors T3 and T4 are turned off. The first voltage is represented as V1_L, and the second voltage is represented as V1_H. The V1_H is higher than the V1_L, and it is preferable that the V1_H is higher than the data voltage V.sub.DATA. The first scan signal SC1(n) is a low voltage and the first transistor T1 is turned off. The second and third scan signals SC2(n) and SC3(n) are high voltages, and the second, fifth, and sixth transistors T2, T5, and T6 are turned off. The voltage of the gate electrode of the driving transistor DT connected to the first node N1 is V.sub.DATA(n−1)−|Vth|, that is, a difference between the data voltage V.sub.DATA(n−1) of the previous frame n−1 and the threshold voltage Vth of the driving transistor DT.”)
Consider Claim 11:
Lin in view of Sang discloses the display panel according to claim 1, wherein the operation of the pixel circuit comprises at least one data write frame and at least one retention frame. (Lin, [0072], “At time t3, signal SCAN2(n) is pulsed low, which turns on transistor Tdata to load in a desired data value D(n) onto Node3. Since signal SCAN1(n) remains high during this time, the drive transistor remains in the diode-connected configuration, so both data signal Vdata and the drive transistor threshold voltage Vth will be sampled onto the storage capacitor Cst1. At time t4, signal SCAN1(n) is driven low to turn off transistor Tgd while signal SCAN2(n) is driven high to turn off transistor Tdata, thereby ending the Vth sampling and data programming phase. At time t5, signals EM(n) is driven low to start the emission phase.”)
Consider Claim 12:
Lin in view of Sang discloses the display panel according to claim 11, wherein the data write frame comprises at least one bias stage; or the retention frame comprises at least one bias stage. (Lin, [0070], “Second initialization transistor Tini2 may be a p-type silicon transistor like the rest of the silicon transistors within the pixel and may be controlled by signal SCAN2(n−1) routed from an immediately preceding pixel row via routing path 314-2′. Signal SCAN2(n−1) can be pulsed low during the non-emission phase to help set Node1 to VDDEL during the initialization/anode reset phase. One such way of operating pixel 22 of FIG. 5A is illustrated in the timing diagram of FIG. 5B.”)
Consider Claim 13:
Lin in view of Sang discloses the display panel according to claim 1, wherein the pixel circuit comprises: a second light emitting control module connected between the light emitting element and the first electrode of the driving transistor; a reset module connected to a gate or the second electrode of the driving transistor; and a storage capacitor connected between a control terminal of the driving transistor and the light emitting element. (Lin, [0069], “FIG. 5A is a circuit diagram showing yet another suitable implementation of display pixel 22 having at least two initialization transistors. As shown in FIG. 5A, pixel 22 may include transistor Tem1, transistor Tdrive, transistor Tem2, and diode 304 coupled in series between power supply terminals 300 and 302. Storage capacitor Cst1 may be coupled between Node2 and the anode terminal of diode 304. Transistor Tgd that is controlled by signal SCAN1(n) on scan line 314-1 may be coupled across Node1 and Node2. Transistor Tdata that is controlled by signal SCAN2(n) on scan line 314-2 may be coupled to Node3. Pixel 22 may include a first initialization transistor Tini1 coupled to the anode terminal of diode 304. In the example of FIG. 5A, transistors Tgd, Tdrive, and Tini1 may all be implemented as semiconducting-oxide transistors (see transistors surrounded by circles) while all remaining transistors are implemented as p-type silicon transistors. This configuration is, however, merely illustrative. In general, any portion of pixel 22 of FIG. 5A may be implemented as semiconducting-oxide transistors and/or n-type/p-type silicon transistors.”)
Consider Claim 14:
Lin in view of Sang discloses the display panel according to claim 1, wherein the operation of the pixel circuit further comprises at least one non-bias stage; in the bias stage, a voltage of a gate of the driving transistor is Vg1, a voltage of the first electrode of the driving transistor is Vs1, and a voltage of the second electrode of the driving transistor is Vd1; and in the non-bias stage, the voltage of the gate of the driving transistor is Vg2, the voltage of the first electrode of the driving transistor is Vs2, and the voltage of the second electrode of the driving transistor is Vd2, wherein (Vg1 - Vd1) × (Vg2 - Vd2) < 0, or (Vg1 - Vs1) × (Vg2 - Vs2) < 0. (Lin, [0070], “Second initialization transistor Tini2 may be a p-type silicon transistor like the rest of the silicon transistors within the pixel and may be controlled by signal SCAN2(n−1) routed from an immediately preceding pixel row via routing path 314-2′. Signal SCAN2(n−1) can be pulsed low during the non-emission phase to help set Node1 to VDDEL during the initialization/anode reset phase. One such way of operating pixel 22 of FIG. 5A is illustrated in the timing diagram of FIG. 5B.”)
Consider Claim 15:
Lin in view of Sang discloses the display panel according to claim 14, wherein a duration of the bias stage is t1, and a duration of the non-bias stage is t2, wherein ( ∣ Vg1 - Vs1 ∣ - ∣ Vg2 - Vs2 ∣ ) × (t1 - t2) < 0, or ( ∣ Vg1 - Vd1 ∣﹣∣ Vg2 - Vd2 ∣ ) × (t1 - t2) < 0. (Lin, [0070], “Second initialization transistor Tini2 may be a p-type silicon transistor like the rest of the silicon transistors within the pixel and may be controlled by signal SCAN2(n−1) routed from an immediately preceding pixel row via routing path 314-2′. Signal SCAN2(n−1) can be pulsed low during the non-emission phase to help set Node1 to VDDEL during the initialization/anode reset phase. One such way of operating pixel 22 of FIG. 5A is illustrated in the timing diagram of FIG. 5B.”)
Consider Claim 16:
Lin in view of Sang discloses the display panel according to claim 14, wherein the non-bias phase is a light emitting stage of the pixel circuit. (Lin, [0073], “In the example of FIG. 5B, the Vth sampling and data programming phase immediately follows the initialization phase. This is merely illustrative and is not intended to limit the scope of the present embodiments. If desired, one or more OBS phases may be inserted between the initialization phase and the data programming phase, and/or one or more OBS phases may be inserted between the data programming phase and the emission phase.”)
Consider Claim 17:
Lin in view of Sang discloses the display panel according to claim 14, wherein in the bias stage, the voltage at the second electrode of the driving transistor is lower than the voltage at the gate of the driving transistor; or the operation of the pixel circuit comprises at least one data write stage, wherein the at least one data write stage is performed before at least one bias stage. (Lin, [0046], [0065], [0070-0073], [0071], “Prior to time t0, emission signal EM(n) is low, thereby turning on both emission transistors Tem1 and Tem2, so pixel 22 is in the emission phase. At time t0, signal EM(n) is driven high to temporarily halt emission. At time t1, signal SCAN1(n) is driven high to turn on transistor Tgd while signal SCAN2(n−1) is pulsed low to temporarily activate second initialization transistor Tini2. Turning on both transistors Tgd and Tini2 in this way initializes pixel 22 by setting Node1 to positive power supply voltage VDDEL. During this time, signal EM(n) is also high, which enables first initialization transistor Tini1 to load initialization voltage Vini onto the anode terminal of diode 304 (i.e., the anode terminal is set to Vini). The period from time t1 to t2 is therefore sometimes referred to as the “initialization” or “anode reset” phase.”)
Consider Claim 18:
Lin in view of Sang discloses the display panel according to claim 14, wherein the driving transistor is an N-type transistor. (Lin, See Fig. 5A item Tdrive.)
Consider Claim 19:
Lin discloses a driving method of a display panel that includes (Lin, See Abstract.)
a pixel circuit and a light emitting element, (Lin, [0034], “FIG. 2 is a diagram of an illustrative display such as an organic light-emitting diode display 14 having an array of organic light-emitting diode display pixels 22. As shown in FIG. 2, display 14 may have one or more layers such as substrate 24. Layers such as substrate 24 may be formed from planar rectangular layers of material such as planar glass layers. Display 14 may have an array of display pixels 22 for displaying images for a user. The array of display pixels 22 may be formed from rows and columns of display pixel structures on substrate 24. These structures may include thin-film transistors such as polysilicon thin-film transistors, semiconducting-oxide thin-film transistors, etc. There may be any suitable number of rows and columns in the array of display pixels 22 (e.g., ten or more, one hundred or more, or one thousand or more).”)
wherein the pixel circuit comprises a driving module, a data writing module, a compensation module, and a first light emitting control module; the driving module comprises a driving transistor, wherein the driving transistor is an NMOS transistor; the data writing module is connected between a data signal input end and a first electrode of the driving transistor and is used for providing a data signal for the driving transistor; and the first light emitting control module is connected between a first power supply signal end and a second electrode of the driving transistor and is used for providing a first power supply signal for the driving transistor, (Lin, [0069], “FIG. 5A is a circuit diagram showing yet another suitable implementation of display pixel 22 having at least two initialization transistors. As shown in FIG. 5A, pixel 22 may include transistor Tem1, transistor Tdrive, transistor Tem2, and diode 304 coupled in series between power supply terminals 300 and 302. Storage capacitor Cst1 may be coupled between Node2 and the anode terminal of diode 304. Transistor Tgd that is controlled by signal SCAN1(n) on scan line 314-1 may be coupled across Node1 and Node2. Transistor Tdata that is controlled by signal SCAN2(n) on scan line 314-2 may be coupled to Node3. Pixel 22 may include a first initialization transistor Tini1 coupled to the anode terminal of diode 304. In the example of FIG. 5A, transistors Tgd, Tdrive, and Tini1 may all be implemented as semiconducting-oxide transistors (see transistors surrounded by circles) while all remaining transistors are implemented as p-type silicon transistors. This configuration is, however, merely illustrative. In general, any portion of pixel 22 of FIG. 5A may be implemented as semiconducting-oxide transistors and/or n-type/p-type silicon transistors.”)
the driving method of the display panel comprising: receiving, by the driving transistor, a bias signal during a bias stage of at least one bias stage, wherein the compensation module is turned off during the bias stage. (Lin, [0073], [0070], “Second initialization transistor Tini2 may be a p-type silicon transistor like the rest of the silicon transistors within the pixel and may be controlled by signal SCAN2(n−1) routed from an immediately preceding pixel row via routing path 314-2′. Signal SCAN2(n−1) can be pulsed low during the non-emission phase to help set Node1 to VDDEL during the initialization/anode reset phase. One such way of operating pixel 22 of FIG. 5A is illustrated in the timing diagram of FIG. 5B.”)
wherein the compensation module is turned off during the bias stage. (Lin, [0072], “At time t3, signal SCAN2(n) is pulsed low, which turns on transistor Tdata to load in a desired data value D(n) onto Node3. Since signal SCAN1(n) remains high during this time, the drive transistor remains in the diode-connected configuration, so both data signal Vdata and the drive transistor threshold voltage Vth will be sampled onto the storage capacitor Cst1.”)
Lin however does not appear to further specify receiving, by the driving transistor, a second bias signal during a bias stage of at least one bias stage: and voltage of the second bias signal is lower than a voltage of the first bias signal during the non-bias stage.
Sang however teaches that it was a known technique in the art to use different bias voltages in different periods for biasing the driving transistor and therefore teaches receiving, by the driving transistor, a second bias signal during a bias stage of at least one bias stage: and voltage of the second bias signal is lower than a voltage of the first bias signal during the non-bias stage. (Sang, [0056], [0103-0106], [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown. The light emission signal EM represents a high voltage, and the third and fourth transistors T3 and T4 are turned off. The first voltage is represented as V1_L, and the second voltage is represented as V1_H. The V1_H is higher than the V1_L, and it is preferable that the V1_H is higher than the data voltage V.sub.DATA. The first scan signal SC1(n) is a low voltage and the first transistor T1 is turned off. The second and third scan signals SC2(n) and SC3(n) are high voltages, and the second, fifth, and sixth transistors T2, T5, and T6 are turned off. The voltage of the gate electrode of the driving transistor DT connected to the first node N1 is V.sub.DATA(n−1)−|Vth|, that is, a difference between the data voltage V.sub.DATA(n−1) of the previous frame n−1 and the threshold voltage Vth of the driving transistor DT.”)
so that the driving transistor is reversely biased; and before the bias stage, converting the bias signal from the first bias signal to the second bias signal, and (Sang, [0081-0086], [0093-0102], See Figures 3A-C and 3H-J. [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown.”)
after a first interval stage provided to deal with a delay of a rising edge or a falling edge of the bias signal, beginning the bias stage, wherein during the first interval stage. the bias signal provides the second bias signal but the driving transistor does not receive the second bias signal until the first interval stage ends. (Sang, [0083], “In FIG. 3B, the low second scan signal SC2(n) is input, and the fifth and sixth transistors T5 and T6 are turned on. As the fifth transistor T5 is turned on, the first bias voltage V1 (V1_H) is applied to the first electrode of the driving transistor DT connected to the second node N2. The voltage of the first electrode of the driving transistor DT connected to the second node N2 increases to the voltage V1_H. The driving transistor DT may be a PMOS transistor, and in this case, the first electrode may be a source electrode.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide a first and second bias signal to the driving transistor over different periods as taught in Sang as this was a known technique in view as taught by Sang and would have been used for the purpose of so that the hysteresis of the driving transistor can be reduced. (Sang, [0084])
Consider Claim 20:
Lin discloses a display device comprising: (Lin, See Abstract.)
a display panel, comprising: a pixel circuit and a light emitting element, wherein: (Lin, [0034], “FIG. 2 is a diagram of an illustrative display such as an organic light-emitting diode display 14 having an array of organic light-emitting diode display pixels 22. As shown in FIG. 2, display 14 may have one or more layers such as substrate 24. Layers such as substrate 24 may be formed from planar rectangular layers of material such as planar glass layers. Display 14 may have an array of display pixels 22 for displaying images for a user. The array of display pixels 22 may be formed from rows and columns of display pixel structures on substrate 24. These structures may include thin-film transistors such as polysilicon thin-film transistors, semiconducting-oxide thin-film transistors, etc. There may be any suitable number of rows and columns in the array of display pixels 22 (e.g., ten or more, one hundred or more, or one thousand or more).”)
the pixel circuit comprises a driving module, a data writing module, a compensation module, and a first light emitting control module; the driving module comprises a driving transistor, wherein the driving transistor is an NMOS transistor; the data writing module is connected between a data signal input end and a first electrode of the driving transistor and is used for providing a data signal for the driving transistor; and the first light emitting control module is connected between a first power supply signal end and a second electrode of the driving transistor and is used for providing a first power supply signal for the driving transistor, (Lin, [0069], “FIG. 5A is a circuit diagram showing yet another suitable implementation of display pixel 22 having at least two initialization transistors. As shown in FIG. 5A, pixel 22 may include transistor Tem1, transistor Tdrive, transistor Tem2, and diode 304 coupled in series between power supply terminals 300 and 302. Storage capacitor Cst1 may be coupled between Node2 and the anode terminal of diode 304. Transistor Tgd that is controlled by signal SCAN1(n) on scan line 314-1 may be coupled across Node1 and Node2. Transistor Tdata that is controlled by signal SCAN2(n) on scan line 314-2 may be coupled to Node3. Pixel 22 may include a first initialization transistor Tini1 coupled to the anode terminal of diode 304. In the example of FIG. 5A, transistors Tgd, Tdrive, and Tini1 may all be implemented as semiconducting-oxide transistors (see transistors surrounded by circles) while all remaining transistors are implemented as p-type silicon transistors. This configuration is, however, merely illustrative. In general, any portion of pixel 22 of FIG. 5A may be implemented as semiconducting-oxide transistors and/or n-type/p-type silicon transistors.”)
wherein an operation of the pixel circuit comprises at least one bias stage, and during a bias stage of the at least one bias stage, the driving transistor receives a bias signal, (Lin, [0073], [0070], “Second initialization transistor Tini2 may be a p-type silicon transistor like the rest of the silicon transistors within the pixel and may be controlled by signal SCAN2(n−1) routed from an immediately preceding pixel row via routing path 314-2′. Signal SCAN2(n−1) can be pulsed low during the non-emission phase to help set Node1 to VDDEL during the initialization/anode reset phase. One such way of operating pixel 22 of FIG. 5A is illustrated in the timing diagram of FIG. 5B.”)
the compensation module is turned off during the bias stage. (Lin, [0072], “At time t3, signal SCAN2(n) is pulsed low, which turns on transistor Tdata to load in a desired data value D(n) onto Node3. Since signal SCAN1(n) remains high during this time, the drive transistor remains in the diode-connected configuration, so both data signal Vdata and the drive transistor threshold voltage Vth will be sampled onto the storage capacitor Cst1.”)
Lin however does not appear to further specify wherein the operation of the pixel circuit further comprises a non-bias stage, during the non-bias stage, the bias signal provides a first bias signal, and during the bias stage, the bias signal provides a second bias signal, wherein a voltage of the second bias signal is lower than a voltage of the first bias signal.
Sang however teaches that it was a known technique in the art to use different bias voltages in different periods for biasing the driving transistor and therefore teaches wherein the operation of the pixel circuit further comprises a non-bias stage, during the non-bias stage, the bias signal provides a first bias signal, and during the bias stage, the bias signal provides a second bias signal, wherein a voltage of the second bias signal is lower than a voltage of the first bias signal. (Sang, [0056], [0103-0106], [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown. The light emission signal EM represents a high voltage, and the third and fourth transistors T3 and T4 are turned off. The first voltage is represented as V1_L, and the second voltage is represented as V1_H. The V1_H is higher than the V1_L, and it is preferable that the V1_H is higher than the data voltage V.sub.DATA. The first scan signal SC1(n) is a low voltage and the first transistor T1 is turned off. The second and third scan signals SC2(n) and SC3(n) are high voltages, and the second, fifth, and sixth transistors T2, T5, and T6 are turned off. The voltage of the gate electrode of the driving transistor DT connected to the first node N1 is V.sub.DATA(n−1)−|Vth|, that is, a difference between the data voltage V.sub.DATA(n−1) of the previous frame n−1 and the threshold voltage Vth of the driving transistor DT.”)
so that the driving transistor is reversely biased, and wherein before the bias stage, the bias signal is converted from the first bias signal to the second bias signal, and (Sang, [0081-0086], [0093-0102], See Figures 3A-C and 3H-J. [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown.”)
after a first interval stage provided to deal with a delay of a rising edge or a falling edge of the bias signal, the bias stage begins, wherein during the first interval stage, the bias signal provides the second bias signal but the driving transistor does not receive the second bias signal until the first interval stage ends. (Sang, [0083], “In FIG. 3B, the low second scan signal SC2(n) is input, and the fifth and sixth transistors T5 and T6 are turned on. As the fifth transistor T5 is turned on, the first bias voltage V1 (V1_H) is applied to the first electrode of the driving transistor DT connected to the second node N2. The voltage of the first electrode of the driving transistor DT connected to the second node N2 increases to the voltage V1_H. The driving transistor DT may be a PMOS transistor, and in this case, the first electrode may be a source electrode.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide a first and second bias signal to the driving transistor over different periods as taught in Sang as this was a known technique in view as taught by Sang and would have been used for the purpose of so that the hysteresis of the driving transistor can be reduced. (Sang, [0084])
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
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/Michael J Jansen II/ Primary Examiner, Art Unit 2626
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