DETAILED ACTION
This communication is in response to Application No. 18/886,109 originally filed 09/16/2024. The Request for Continued Examination and Amendment presented on 01/30/2026 which provides amendments to claims 1, 9, 10, 19, and 20 and claims 6-8 are cancelled is hereby acknowledged. The claims are subject to the restriction set forth on 05/12/2025 in which Applicant as elected Species A in the reply filed 07/07/2025. Claims 3 and 5 were withdrawn.
Currently claims 1-2, 4, and 9-20 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/30/2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 1-2, 4, and 9-20 have been fully considered but they are not persuasive.
Regarding Sang, the prior art reference teaches applying a change to the bias signal prior to the actual gate signal SC2(n) which applies the signal to the gate of T5. This is shown in Figures 3A-C and 3H-J. Provided below is marked up in figure 3I as an example. These periods are considered the first and second interval stages. Furthermore, the figures shows the application of the applied voltage. In addition, as the driving transistor is a pmos transistor, application of the higher voltage in this direction creates a reverse bias condition on DT as is indicated by the arrow. This appears similar to Applicants arrow in Figure 4 which shows the reverse bias of the driving transistor.
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In response to applicant's argument that the references fail to show certain features of the invention, although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Therefore, after review, the arguments are not found persuasive and the rejection will be maintained.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-2, 4, and 9-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. U.S. Patent Application Publication No. 2023/0035245 A1 as applied to claim 1 above, and further in view of Sang et al. U.S. Patent Application Publication No. 2022/0059036 A1 hereinafter Sang.
Consider Claim 1:
Lin discloses a display panel, comprising: (Lin, See Abstract.)
a pixel circuit and a light emitting element, (Lin, [0034], “FIG. 2 is a diagram of an illustrative display such as an organic light-emitting diode display 14 having an array of organic light-emitting diode display pixels 22. As shown in FIG. 2, display 14 may have one or more layers such as substrate 24. Layers such as substrate 24 may be formed from planar rectangular layers of material such as planar glass layers. Display 14 may have an array of display pixels 22 for displaying images for a user. The array of display pixels 22 may be formed from rows and columns of display pixel structures on substrate 24. These structures may include thin-film transistors such as polysilicon thin-film transistors, semiconducting-oxide thin-film transistors, etc. There may be any suitable number of rows and columns in the array of display pixels 22 (e.g., ten or more, one hundred or more, or one thousand or more).”)
wherein: the pixel circuit comprises a driving module, a data writing module, and a first light emitting control module; the driving module comprises a driving transistor; the data writing module is connected between a data signal input end and a first electrode of the driving transistor and is used for providing a data signal for the driving transistor; and the first light emitting control module is connected between a first power supply signal end and a second electrode of the driving transistor and is used for providing a first power supply signal for the driving transistor, (Lin, [0069], “FIG. 5A is a circuit diagram showing yet another suitable implementation of display pixel 22 having at least two initialization transistors. As shown in FIG. 5A, pixel 22 may include transistor Tem1, transistor Tdrive, transistor Tem2, and diode 304 coupled in series between power supply terminals 300 and 302. Storage capacitor Cst1 may be coupled between Node2 and the anode terminal of diode 304. Transistor Tgd that is controlled by signal SCAN1(n) on scan line 314-1 may be coupled across Node1 and Node2. Transistor Tdata that is controlled by signal SCAN2(n) on scan line 314-2 may be coupled to Node3. Pixel 22 may include a first initialization transistor Tini1 coupled to the anode terminal of diode 304. In the example of FIG. 5A, transistors Tgd, Tdrive, and Tini1 may all be implemented as semiconducting-oxide transistors (see transistors surrounded by circles) while all remaining transistors are implemented as p-type silicon transistors. This configuration is, however, merely illustrative. In general, any portion of pixel 22 of FIG. 5A may be implemented as semiconducting-oxide transistors and/or n-type/p-type silicon transistors.”)
wherein an operation of the pixel circuit comprises at least one bias stage, and during a bias stage of the at least one bias stage, the driving transistor receives a bias signal. (Lin, [0073], [0070], “Second initialization transistor Tini2 may be a p-type silicon transistor like the rest of the silicon transistors within the pixel and may be controlled by signal SCAN2(n−1) routed from an immediately preceding pixel row via routing path 314-2′. Signal SCAN2(n−1) can be pulsed low during the non-emission phase to help set Node1 to VDDEL during the initialization/anode reset phase. One such way of operating pixel 22 of FIG. 5A is illustrated in the timing diagram of FIG. 5B.”)
Lin however does not appear to further specify wherein the operation of the pixel circuit further comprises a non-bias stage, during the non-bias stage, the bias signal provides a first bias signal, and during the bias stage, the bias signal provides a second bias signal, wherein a voltage of the second bias signal is lower than a voltage of the first bias signal.
Sang however teaches that it was a known technique in the art to use different bias voltages in different periods for biasing the driving transistor and therefore teaches wherein the operation of the pixel circuit further comprises a non-bias stage, during the non-bias stage, the bias signal provides a first bias signal, and during the bias stage, the bias signal provides a second bias signal, wherein a voltage of the second bias signal is lower than a voltage of the first bias signal, (Sang, [0056], [0103-0106], [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown. The light emission signal EM represents a high voltage, and the third and fourth transistors T3 and T4 are turned off. The first voltage is represented as V1_L, and the second voltage is represented as V1_H. The V1_H is higher than the V1_L, and it is preferable that the V1_H is higher than the data voltage V.sub.DATA. The first scan signal SC1(n) is a low voltage and the first transistor T1 is turned off. The second and third scan signals SC2(n) and SC3(n) are high voltages, and the second, fifth, and sixth transistors T2, T5, and T6 are turned off. The voltage of the gate electrode of the driving transistor DT connected to the first node N1 is V.sub.DATA(n−1)−|Vth|, that is, a difference between the data voltage V.sub.DATA(n−1) of the previous frame n−1 and the threshold voltage Vth of the driving transistor DT.”)
so that the driving transistor is reversely biased, and wherein before the bias stage, the bias signal is converted from the first bias signal to the second bias signal, and (Sang, [0081-0086], [0093-0102], See Figures 3A-C and 3H-J. [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown.”)
after a first interval stage provided to deal with a delay of a rising edge or a falling edge of the bias signal, the bias stage begins, wherein during the first interval stage, the bias signal provides the second bias signal but the driving transistor does not receive the second bias signal until the first interval stage ends. (Sang, [0083], “In FIG. 3B, the low second scan signal SC2(n) is input, and the fifth and sixth transistors T5 and T6 are turned on. As the fifth transistor T5 is turned on, the first bias voltage V1 (V1_H) is applied to the first electrode of the driving transistor DT connected to the second node N2. The voltage of the first electrode of the driving transistor DT connected to the second node N2 increases to the voltage V1_H. The driving transistor DT may be a PMOS transistor, and in this case, the first electrode may be a source electrode.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide a first and second bias signal to the driving transistor over different periods as taught in Sang as this was a known technique in view as taught by Sang and would have been used for the purpose of so that the hysteresis of the driving transistor can be reduced. (Sang, [0084])
Consider Claim 2:
Lin in view of Sang discloses the display panel according to claim 1, wherein the pixel circuit comprises a bias module, and during the bias stage, the bias module is on and provides the bias signal for the driving transistor. (Lin, [0070], “Second initialization transistor Tini2 may be a p-type silicon transistor like the rest of the silicon transistors within the pixel and may be controlled by signal SCAN2(n−1) routed from an immediately preceding pixel row via routing path 314-2′. Signal SCAN2(n−1) can be pulsed low during the non-emission phase to help set Node1 to VDDEL during the initialization/anode reset phase. One such way of operating pixel 22 of FIG. 5A is illustrated in the timing diagram of FIG. 5B.”)
Consider Claim 4:
Lin in view of Sang discloses the display panel according to claim 2, wherein the pixel circuit comprises a compensation module which is connected between a gate of the driving transistor and the second electrode of the driving transistor. (Lin, See Fig. 5A)
Consider Claim 9:
Lin in view of Sang disclose the display panel according to claim 8, wherein at the end of the bias stage, the bias signal remains the second bias signal, which, after a second interval stage, is converted into the first bias signal. (Sang, [0103-0106], [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown. The light emission signal EM represents a high voltage, and the third and fourth transistors T3 and T4 are turned off. The first voltage is represented as V1_L, and the second voltage is represented as V1_H. The V1_H is higher than the V1_L, and it is preferable that the V1_H is higher than the data voltage V.sub.DATA. The first scan signal SC1(n) is a low voltage and the first transistor T1 is turned off. The second and third scan signals SC2(n) and SC3(n) are high voltages, and the second, fifth, and sixth transistors T2, T5, and T6 are turned off. The voltage of the gate electrode of the driving transistor DT connected to the first node N1 is V.sub.DATA(n−1)−|Vth|, that is, a difference between the data voltage V.sub.DATA(n−1) of the previous frame n−1 and the threshold voltage Vth of the driving transistor DT.”)
Consider Claim 10:
Lin in view of Sang disclose the display panel according to claim 8, wherein a duration of the first interval stage is shorter than a duration of the bias stage; or a duration the second interval stage is shorter than a duration of the bias stage. (Sang, [0103-0106], [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown. The light emission signal EM represents a high voltage, and the third and fourth transistors T3 and T4 are turned off. The first voltage is represented as V1_L, and the second voltage is represented as V1_H. The V1_H is higher than the V1_L, and it is preferable that the V1_H is higher than the data voltage V.sub.DATA. The first scan signal SC1(n) is a low voltage and the first transistor T1 is turned off. The second and third scan signals SC2(n) and SC3(n) are high voltages, and the second, fifth, and sixth transistors T2, T5, and T6 are turned off. The voltage of the gate electrode of the driving transistor DT connected to the first node N1 is V.sub.DATA(n−1)−|Vth|, that is, a difference between the data voltage V.sub.DATA(n−1) of the previous frame n−1 and the threshold voltage Vth of the driving transistor DT.”)
Consider Claim 11:
Lin in view of Sang discloses the display panel according to claim 1, wherein the operation of the pixel circuit comprises at least one data write frame and at least one retention frame. (Lin, [0072], “At time t3, signal SCAN2(n) is pulsed low, which turns on transistor Tdata to load in a desired data value D(n) onto Node3. Since signal SCAN1(n) remains high during this time, the drive transistor remains in the diode-connected configuration, so both data signal Vdata and the drive transistor threshold voltage Vth will be sampled onto the storage capacitor Cst1. At time t4, signal SCAN1(n) is driven low to turn off transistor Tgd while signal SCAN2(n) is driven high to turn off transistor Tdata, thereby ending the Vth sampling and data programming phase. At time t5, signals EM(n) is driven low to start the emission phase.”)
Consider Claim 12:
Lin in view of Sang discloses the display panel according to claim 11, wherein the data write frame comprises at least one bias stage; or the retention frame comprises at least one bias stage. (Lin, [0070], “Second initialization transistor Tini2 may be a p-type silicon transistor like the rest of the silicon transistors within the pixel and may be controlled by signal SCAN2(n−1) routed from an immediately preceding pixel row via routing path 314-2′. Signal SCAN2(n−1) can be pulsed low during the non-emission phase to help set Node1 to VDDEL during the initialization/anode reset phase. One such way of operating pixel 22 of FIG. 5A is illustrated in the timing diagram of FIG. 5B.”)
Consider Claim 13:
Lin in view of Sang discloses the display panel according to claim 1, wherein the pixel circuit comprises: a second light emitting control module connected between the light emitting element and the first electrode of the driving transistor; a reset module connected to a gate or the second electrode of the driving transistor; and a storage capacitor connected between a control terminal of the driving transistor and the light emitting element. (Lin, [0069], “FIG. 5A is a circuit diagram showing yet another suitable implementation of display pixel 22 having at least two initialization transistors. As shown in FIG. 5A, pixel 22 may include transistor Tem1, transistor Tdrive, transistor Tem2, and diode 304 coupled in series between power supply terminals 300 and 302. Storage capacitor Cst1 may be coupled between Node2 and the anode terminal of diode 304. Transistor Tgd that is controlled by signal SCAN1(n) on scan line 314-1 may be coupled across Node1 and Node2. Transistor Tdata that is controlled by signal SCAN2(n) on scan line 314-2 may be coupled to Node3. Pixel 22 may include a first initialization transistor Tini1 coupled to the anode terminal of diode 304. In the example of FIG. 5A, transistors Tgd, Tdrive, and Tini1 may all be implemented as semiconducting-oxide transistors (see transistors surrounded by circles) while all remaining transistors are implemented as p-type silicon transistors. This configuration is, however, merely illustrative. In general, any portion of pixel 22 of FIG. 5A may be implemented as semiconducting-oxide transistors and/or n-type/p-type silicon transistors.”)
Consider Claim 14:
Lin in view of Sang discloses the display panel according to claim 1, wherein the operation of the pixel circuit further comprises at least one non-bias stage; in the bias stage, a voltage of a gate of the driving transistor is Vg1, a voltage of the first electrode of the driving transistor is Vs1, and a voltage of the second electrode of the driving transistor is Vd1; and in the non-bias stage, the voltage of the gate of the driving transistor is Vg2, the voltage of the first electrode of the driving transistor is Vs2, and the voltage of the second electrode of the driving transistor is Vd2, wherein (Vg1 - Vd1) × (Vg2 - Vd2) < 0, or (Vg1 - Vs1) × (Vg2 - Vs2) < 0. (Lin, [0070], “Second initialization transistor Tini2 may be a p-type silicon transistor like the rest of the silicon transistors within the pixel and may be controlled by signal SCAN2(n−1) routed from an immediately preceding pixel row via routing path 314-2′. Signal SCAN2(n−1) can be pulsed low during the non-emission phase to help set Node1 to VDDEL during the initialization/anode reset phase. One such way of operating pixel 22 of FIG. 5A is illustrated in the timing diagram of FIG. 5B.”)
Consider Claim 15:
Lin in view of Sang discloses the display panel according to claim 14, wherein a duration of the bias stage is t1, and a duration of the non-bias stage is t2, wherein ( ∣ Vg1 - Vs1 ∣ - ∣ Vg2 - Vs2 ∣ ) × (t1 - t2) < 0, or ( ∣ Vg1 - Vd1 ∣﹣∣ Vg2 - Vd2 ∣ ) × (t1 - t2) < 0. (Lin, [0070], “Second initialization transistor Tini2 may be a p-type silicon transistor like the rest of the silicon transistors within the pixel and may be controlled by signal SCAN2(n−1) routed from an immediately preceding pixel row via routing path 314-2′. Signal SCAN2(n−1) can be pulsed low during the non-emission phase to help set Node1 to VDDEL during the initialization/anode reset phase. One such way of operating pixel 22 of FIG. 5A is illustrated in the timing diagram of FIG. 5B.”)
Consider Claim 16:
Lin in view of Sang discloses the display panel according to claim 14, wherein the non-bias phase is a light emitting stage of the pixel circuit. (Lin, [0073], “In the example of FIG. 5B, the Vth sampling and data programming phase immediately follows the initialization phase. This is merely illustrative and is not intended to limit the scope of the present embodiments. If desired, one or more OBS phases may be inserted between the initialization phase and the data programming phase, and/or one or more OBS phases may be inserted between the data programming phase and the emission phase.”)
Consider Claim 17:
Lin in view of Sang discloses the display panel according to claim 14, wherein in the bias stage, the voltage at the second electrode of the driving transistor is lower than the voltage at the gate of the driving transistor; or the operation of the pixel circuit comprises at least one data write stage, wherein the at least one data write stage is performed before at least one bias stage. (Lin, [0046], [0065], [0070-0073], [0071], “Prior to time t0, emission signal EM(n) is low, thereby turning on both emission transistors Tem1 and Tem2, so pixel 22 is in the emission phase. At time t0, signal EM(n) is driven high to temporarily halt emission. At time t1, signal SCAN1(n) is driven high to turn on transistor Tgd while signal SCAN2(n−1) is pulsed low to temporarily activate second initialization transistor Tini2. Turning on both transistors Tgd and Tini2 in this way initializes pixel 22 by setting Node1 to positive power supply voltage VDDEL. During this time, signal EM(n) is also high, which enables first initialization transistor Tini1 to load initialization voltage Vini onto the anode terminal of diode 304 (i.e., the anode terminal is set to Vini). The period from time t1 to t2 is therefore sometimes referred to as the “initialization” or “anode reset” phase.”)
Consider Claim 18:
Lin in view of Sang discloses the display panel according to claim 14, wherein the driving transistor is an N-type transistor. (Lin, See Fig. 5A item Tdrive.)
Consider Claim 19:
Lin discloses a driving method of a display panel that includes (Lin, See Abstract.)
a pixel circuit and a light emitting element, (Lin, [0034], “FIG. 2 is a diagram of an illustrative display such as an organic light-emitting diode display 14 having an array of organic light-emitting diode display pixels 22. As shown in FIG. 2, display 14 may have one or more layers such as substrate 24. Layers such as substrate 24 may be formed from planar rectangular layers of material such as planar glass layers. Display 14 may have an array of display pixels 22 for displaying images for a user. The array of display pixels 22 may be formed from rows and columns of display pixel structures on substrate 24. These structures may include thin-film transistors such as polysilicon thin-film transistors, semiconducting-oxide thin-film transistors, etc. There may be any suitable number of rows and columns in the array of display pixels 22 (e.g., ten or more, one hundred or more, or one thousand or more).”)
wherein the pixel circuit comprises a driving module, a data writing module, and a first light emitting control module; the driving module comprises a driving transistor; the data writing module is connected between a data signal input end and a first electrode of the driving transistor and is used for providing a data signal for the driving transistor; and the first light emitting control module is connected between a first power supply signal end and a second electrode of the driving transistor and is used for providing a first power supply signal for the driving transistor, (Lin, [0069], “FIG. 5A is a circuit diagram showing yet another suitable implementation of display pixel 22 having at least two initialization transistors. As shown in FIG. 5A, pixel 22 may include transistor Tem1, transistor Tdrive, transistor Tem2, and diode 304 coupled in series between power supply terminals 300 and 302. Storage capacitor Cst1 may be coupled between Node2 and the anode terminal of diode 304. Transistor Tgd that is controlled by signal SCAN1(n) on scan line 314-1 may be coupled across Node1 and Node2. Transistor Tdata that is controlled by signal SCAN2(n) on scan line 314-2 may be coupled to Node3. Pixel 22 may include a first initialization transistor Tini1 coupled to the anode terminal of diode 304. In the example of FIG. 5A, transistors Tgd, Tdrive, and Tini1 may all be implemented as semiconducting-oxide transistors (see transistors surrounded by circles) while all remaining transistors are implemented as p-type silicon transistors. This configuration is, however, merely illustrative. In general, any portion of pixel 22 of FIG. 5A may be implemented as semiconducting-oxide transistors and/or n-type/p-type silicon transistors.”)
the driving method of the display panel comprising: receiving, by the driving transistor, a bias signal during a bias stage of at least one bias stage. (Lin, [0073], [0070], “Second initialization transistor Tini2 may be a p-type silicon transistor like the rest of the silicon transistors within the pixel and may be controlled by signal SCAN2(n−1) routed from an immediately preceding pixel row via routing path 314-2′. Signal SCAN2(n−1) can be pulsed low during the non-emission phase to help set Node1 to VDDEL during the initialization/anode reset phase. One such way of operating pixel 22 of FIG. 5A is illustrated in the timing diagram of FIG. 5B.”)
Lin however does not appear to further specify receiving, by the driving transistor, a second bias signal during a bias stage of at least one bias stage: and voltage of the second bias signal is lower than a voltage of the first bias signal during the non-bias stage.
Sang however teaches that it was a known technique in the art to use different bias voltages in different periods for biasing the driving transistor and therefore teaches receiving, by the driving transistor, a second bias signal during a bias stage of at least one bias stage: and voltage of the second bias signal is lower than a voltage of the first bias signal during the non-bias stage. (Sang, [0056], [0103-0106], [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown. The light emission signal EM represents a high voltage, and the third and fourth transistors T3 and T4 are turned off. The first voltage is represented as V1_L, and the second voltage is represented as V1_H. The V1_H is higher than the V1_L, and it is preferable that the V1_H is higher than the data voltage V.sub.DATA. The first scan signal SC1(n) is a low voltage and the first transistor T1 is turned off. The second and third scan signals SC2(n) and SC3(n) are high voltages, and the second, fifth, and sixth transistors T2, T5, and T6 are turned off. The voltage of the gate electrode of the driving transistor DT connected to the first node N1 is V.sub.DATA(n−1)−|Vth|, that is, a difference between the data voltage V.sub.DATA(n−1) of the previous frame n−1 and the threshold voltage Vth of the driving transistor DT.”)
so that the driving transistor is reversely biased; and before the bias stage, converting the bias signal from the first bias signal to the second bias signal, and (Sang, [0081-0086], [0093-0102], See Figures 3A-C and 3H-J. [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown.”)
after a first interval stage provided to deal with a delay of a rising edge or a falling edge of the bias signal, beginning the bias stage, wherein during the first interval stage. the bias signal provides the second bias signal but the driving transistor does not receive the second bias signal until the first interval stage ends. (Sang, [0083], “In FIG. 3B, the low second scan signal SC2(n) is input, and the fifth and sixth transistors T5 and T6 are turned on. As the fifth transistor T5 is turned on, the first bias voltage V1 (V1_H) is applied to the first electrode of the driving transistor DT connected to the second node N2. The voltage of the first electrode of the driving transistor DT connected to the second node N2 increases to the voltage V1_H. The driving transistor DT may be a PMOS transistor, and in this case, the first electrode may be a source electrode.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide a first and second bias signal to the driving transistor over different periods as taught in Sang as this was a known technique in view as taught by Sang and would have been used for the purpose of so that the hysteresis of the driving transistor can be reduced. (Sang, [0084])
Consider Claim 20:
Lin discloses a display device comprising: (Lin, See Abstract.)
a display panel, comprising: a pixel circuit and a light emitting element, wherein: (Lin, [0034], “FIG. 2 is a diagram of an illustrative display such as an organic light-emitting diode display 14 having an array of organic light-emitting diode display pixels 22. As shown in FIG. 2, display 14 may have one or more layers such as substrate 24. Layers such as substrate 24 may be formed from planar rectangular layers of material such as planar glass layers. Display 14 may have an array of display pixels 22 for displaying images for a user. The array of display pixels 22 may be formed from rows and columns of display pixel structures on substrate 24. These structures may include thin-film transistors such as polysilicon thin-film transistors, semiconducting-oxide thin-film transistors, etc. There may be any suitable number of rows and columns in the array of display pixels 22 (e.g., ten or more, one hundred or more, or one thousand or more).”)
the pixel circuit comprises a driving module, a data writing module, and a first light emitting control module; the driving module comprises a driving transistor; the data writing module is connected between a data signal input end and a first electrode of the driving transistor and is used for providing a data signal for the driving transistor; and the first light emitting control module is connected between a first power supply signal end and a second electrode of the driving transistor and is used for providing a first power supply signal for the driving transistor, (Lin, [0069], “FIG. 5A is a circuit diagram showing yet another suitable implementation of display pixel 22 having at least two initialization transistors. As shown in FIG. 5A, pixel 22 may include transistor Tem1, transistor Tdrive, transistor Tem2, and diode 304 coupled in series between power supply terminals 300 and 302. Storage capacitor Cst1 may be coupled between Node2 and the anode terminal of diode 304. Transistor Tgd that is controlled by signal SCAN1(n) on scan line 314-1 may be coupled across Node1 and Node2. Transistor Tdata that is controlled by signal SCAN2(n) on scan line 314-2 may be coupled to Node3. Pixel 22 may include a first initialization transistor Tini1 coupled to the anode terminal of diode 304. In the example of FIG. 5A, transistors Tgd, Tdrive, and Tini1 may all be implemented as semiconducting-oxide transistors (see transistors surrounded by circles) while all remaining transistors are implemented as p-type silicon transistors. This configuration is, however, merely illustrative. In general, any portion of pixel 22 of FIG. 5A may be implemented as semiconducting-oxide transistors and/or n-type/p-type silicon transistors.”)
wherein an operation of the pixel circuit comprises at least one bias stage, and during a bias stage of the at least one bias stage, the driving transistor receives a bias signal. (Lin, [0073], [0070], “Second initialization transistor Tini2 may be a p-type silicon transistor like the rest of the silicon transistors within the pixel and may be controlled by signal SCAN2(n−1) routed from an immediately preceding pixel row via routing path 314-2′. Signal SCAN2(n−1) can be pulsed low during the non-emission phase to help set Node1 to VDDEL during the initialization/anode reset phase. One such way of operating pixel 22 of FIG. 5A is illustrated in the timing diagram of FIG. 5B.”)
Lin however does not appear to further specify wherein the operation of the pixel circuit further comprises a non-bias stage, during the non-bias stage, the bias signal provides a first bias signal, and during the bias stage, the bias signal provides a second bias signal, wherein a voltage of the second bias signal is lower than a voltage of the first bias signal.
Sang however teaches that it was a known technique in the art to use different bias voltages in different periods for biasing the driving transistor and therefore teaches wherein the operation of the pixel circuit further comprises a non-bias stage, during the non-bias stage, the bias signal provides a first bias signal, and during the bias stage, the bias signal provides a second bias signal, wherein a voltage of the second bias signal is lower than a voltage of the first bias signal. (Sang, [0056], [0103-0106], [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown. The light emission signal EM represents a high voltage, and the third and fourth transistors T3 and T4 are turned off. The first voltage is represented as V1_L, and the second voltage is represented as V1_H. The V1_H is higher than the V1_L, and it is preferable that the V1_H is higher than the data voltage V.sub.DATA. The first scan signal SC1(n) is a low voltage and the first transistor T1 is turned off. The second and third scan signals SC2(n) and SC3(n) are high voltages, and the second, fifth, and sixth transistors T2, T5, and T6 are turned off. The voltage of the gate electrode of the driving transistor DT connected to the first node N1 is V.sub.DATA(n−1)−|Vth|, that is, a difference between the data voltage V.sub.DATA(n−1) of the previous frame n−1 and the threshold voltage Vth of the driving transistor DT.”)
so that the driving transistor is reversely biased, and wherein before the bias stage, the bias signal is converted from the first bias signal to the second bias signal, and (Sang, [0081-0086], [0093-0102], See Figures 3A-C and 3H-J. [0082], “In FIG. 3A, a section in which the first bias voltage V1 is changed from a first voltage to a second voltage is shown.”)
after a first interval stage provided to deal with a delay of a rising edge or a falling edge of the bias signal, the bias stage begins, wherein during the first interval stage, the bias signal provides the second bias signal but the driving transistor does not receive the second bias signal until the first interval stage ends. (Sang, [0083], “In FIG. 3B, the low second scan signal SC2(n) is input, and the fifth and sixth transistors T5 and T6 are turned on. As the fifth transistor T5 is turned on, the first bias voltage V1 (V1_H) is applied to the first electrode of the driving transistor DT connected to the second node N2. The voltage of the first electrode of the driving transistor DT connected to the second node N2 increases to the voltage V1_H. The driving transistor DT may be a PMOS transistor, and in this case, the first electrode may be a source electrode.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide a first and second bias signal to the driving transistor over different periods as taught in Sang as this was a known technique in view as taught by Sang and would have been used for the purpose of so that the hysteresis of the driving transistor can be reduced. (Sang, [0084])
Conclusion
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
Applicant Representatives are reminded of CFR 1.4(d)(2)(ii) which states “A patent practitioner (§ 1.32(a)(1) ), signing pursuant to §§ 1.33(b)(1) or 1.33(b)(2), must supply his/her registration number either as part of the S-signature, or immediately below or adjacent to the S-signature. The number (#) character may be used only as part of the S-signature when appearing before a practitioner’s registration number; otherwise the number character may not be used in an S-signature.” When an unsigned or improperly signed amendment is received the amendment will be listed in the contents of the application file, but not entered. The examiner will notify applicant of the status of the application, advising him or her to furnish a duplicate amendment properly signed or to ratify the amendment already filed. In an application not under final rejection, applicant should be given a two month time period in which to ratify the previously filed amendment (37 CFR 1.135(c) ).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J JANSEN II whose telephone number is (571)272-5604. The examiner can normally be reached Normally Available Monday-Friday 9am-4pm EST.
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/Michael J Jansen II/ Primary Examiner, Art Unit 2626
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