Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
FINAL OFFICE ACTION
This Office Action addresses U.S. Patent Application No. 18/886,194, entitled “NON-VOLATILE MEMORY DEVICE INCLUDING CURRENT MIRROR READ CIRCUIT”, filed September 16, 2024, as a continuation of PCT/JP2023/008037, filed 03/03/2023, and claims priority from JP2022-042611, filed 03/17/2022, filed March 17, 2022.
Claims 1-8 are pending.
DRAWING OBJECTIONS
The drawings are objected to under 37 CFR 1.83(a) because:
Figure 2 is not in accordance with 37 CFR 1.84(l), which states, “Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined.”
In the original Figure 2, all of the lines were sufficiently dense and dark, with the exception of “[A]” and “[V]”, which appeared faded, as shown below:
PNG
media_image1.png
320
510
media_image1.png
Greyscale
However, in the drawing correction submitted August 5, 2026, the “[A]” and “[V]” in Figure 2 are now solid and clear, while the rest of the figure is fuzzy, as show below:
PNG
media_image2.png
521
592
media_image2.png
Greyscale
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
SPECIFICATION
The previous objections to the abstract, title and specification are withdrawn due to the amendments filed August 5, 2026.
If any further errors in translation / English idiom come to light, these should be corrected in the same manner.
CLAIM OBJECTIONS
The previous objection to the claims is withdrawn due to the amendment filed August 5, 2026.
CLAIM INTERPRETATION
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
An application may include one or more claim limitations that use the words “means for” and also limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) use(s) a generic placeholder.
Three Prong Analysis
To invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, a claimed phrase must meet the three prong analysis as set forth in MPEP § 2181, subsection I.
(A) Regarding Prong (A), the MPEP states:
the claim limitation uses the term "means" or "step" or a term used as a substitute for "means" that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function....
The claim limitations listed below do not use the language "means" or "step". However, each of these may be found to be a generic placeholder.
current mirror
reference transistor
data transistor
reference current transistor
storage circuit
voltage adder
driving transistor
differential amplifier
switch
Thus, these limitations meet Prong (A) of the analysis.
(B) Regarding Prong (B), the MPEP states:
the term "means" or "step" or the generic placeholder is modified by
functional language, typically, but not always linked by the transition word "for" (e.g., "means for") or another linking word or phrase, such as "configured to" or "so that"...
The claim limitations listed below may be modified by functional language, as shown.
current mirror (not modified by functional language)
reference element (“configured as”)
data element (“configured as”)
reference current generator (“configured to”)
storage circuit (“operable to”)
voltage adder (“that adds”)
driving transistor (not modified by functional language)
differential amplifier (not modified by functional language)
switch (not modified by functional language)
Any limitations which have been marked “not modified by functional language” do not meet Prong (B) and will not be further considered in this analysis. All other limitations meet Prong (B) of the analysis and must be considered in the following step.
(C) Regarding Prong (C), the MPEP states:
the term "means" or "step" or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
With regard to where the limitations may be found in the disclosure:
reference transistor (“The data elements Md1 and Md2 and the reference elements Mr1 and Mr2 are both configured as memory elements and are configured, more specifically, as NMOS transistors (N-channel MOSFET (metal-oxide-semiconductor field-effect transistors))” ¶ [0015]; “A memory element is an element for which a program operation can be performed by changing the characteristics of a transistor by hot carrier injection and is also called an OTP (one-time programmable) element” ¶ [0015]; however, because of the lack of clarity, the disclosure fails to adequately explain how the structure of a transistor performs the function of “for which a program operation can be performed”)
data transistor (“The data elements Md1 and Md2 and the reference elements Mr1 and Mr2 are both configured as memory elements and are configured, more specifically, as NMOS transistors (N-channel MOSFET (metal-oxide-semiconductor field-effect transistors))” ¶ [0015]; “A memory element is an element for which a program operation can be performed by changing the characteristics of a transistor by hot carrier injection and is also called an OTP (one-time programmable) element” ¶ [0015]; however, because of the lack of clarity, the disclosure fails to adequately explain how the structure of a transistor performs the function of “for being a target of the program operation”)
reference current generator (“the output-side transistor 61 is one example of a reference current generator” ¶ [0055]; there is no further explanation of how the reference current generator performing the function of “generate a reference current”)
storage circuit (see below with regard to circuitry)
voltage adder (“The resistive element R2 is one example of a voltage adder that adds up voltages. The voltage adder is not limited to a resistive element and can be configured with, for example, a MOS transistor” ¶ [0053]; “the first current mirror (8) may have a voltage adder (R2) that adds a voltage to the gate-source voltage of the reference element (81). (A third configuration.) In the third configuration described above, the voltage adder may be a first resistor (R2) connected to the source of the reference element” ¶¶ [0081]-[0082]; this language does not explain how the “resistive element” structure performs the claimed function of “adds a voltage”).
Note: With regard to the limitation(s) directed to a “circuit”, the circuitry as claimed, combined with a description of the function of the circuits in the claim itself, provides sufficient structure to one of ordinary skill in the art. See Mass. Inst. of Tech., 462 F.3d at 1355-1356, 80 USPQ2d at 1332 (“circuitry” is generally determined to have sufficient structure).
Thus, the limitations “storage circuit” listed above do not meet Prong (C) of the analysis and thus do not invoke 35 U.S.C. § 112, 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph.
However, the reference transistor, the data transistor, the reference current transistor and the voltage adder do meet Prong (C) of the analysis and do invoke 35 U.S.C. § 112, 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph.
CLAIM REJECTIONS - 35 USC § 112, 1st PARAGRAPH
The previous rejections under 35 U.S.C. 112(a) are withdrawn due to the amendments filed August 5, 2026. However, new rejections are necessitated by the amendments.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
(1) In claim 1, regarding the claimed “reference transistor”, because of the lack of clarity, the disclosure fails to adequately explain how the structure of a transistor performs the function of “for which a program operation can be performed”.
(2) In claim 1, regarding the claimed “data transistor”, because of the lack of clarity, the disclosure fails to adequately explain how the structure of a transistor performs the function of “for being a target of the program operation”.
(3) In claim 1, regarding the claimed “reference current transistor”, there is not an adequate explanation of how the reference current transistor is performing the function of “generate a reference current”. This is not enabled, because transistors are not current generators.
(4) In claims 3 and 4, regarding the claimed “voltage adder”, the disclosure states, “The resistive element R2 is one example of a voltage adder that adds up voltages. The voltage adder is not limited to a resistive element and can be configured with, for example, a MOS transistor” ¶ [0053] and “the voltage adder may be a first resistor (R2) connected to the source of the reference element” ¶[0082]. However, as shown in the circuit diagram of Figure 4, R2 is simply a resistor:
PNG
media_image3.png
690
964
media_image3.png
Greyscale
This is not enabled, because a resistor cannot add voltages.
CLAIM REJECTIONS - 35 USC § 112, 2nd PARAGRAPH
The previous rejections under 35 U.S.C. 112(a) are withdrawn due to the amendments filed August 5, 2026. However, new rejections are necessitated by the amendments.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude
with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) In claim 1, with regard to the claimed “reference transistor” and the claimed “data transistor”, it is confusing that one is “for which a program operation can be performed” and the other “for being a target of the program operation”, as these seem to mean almost the same thing in the context of the claim.
(2) In claim 1, the “reference element” is a memory element “for which a program operation can be performed” (emphasis added) but a data element is “a target of the program operation” (emphasis added). This is confusing since if the program operation is for the reference element, then it would stand to reason that the reference element is the target.
(3) In claim 1, there is “a first current mirror having” a reference transistor and a data transistor, but there is also “a storage circuit having the data transistor”. Which is it?
(4) In claim 4, it is unclear how a voltage adder can be a resistor. A summing amplifier including resistors would make sense, but applicant has not explained how the single resistor is meant to be used as a voltage adder (cf. “The resistive element R2 is one example of a voltage adder that adds up voltages” ¶ [0053]).
PRIOR ART
WO 2021005956 A1, by the same inventor and assigned to the same assignee, was not cited in an information disclosure statement, but appears to be particularly relevant to the present invention. Any future rejection based on prior art in the prosecution of this application would likely include this reference.
For at least the reasons explained above, the claims are indefinite to the extent that they preclude any reasonable search and consideration on the merits of the claimed subject matter.
Consequently, any rejections based on prior art (e.g., nonstatutory double patenting, 35 U.S.C. §102 or 35 U.S.C. §103) will be held in abeyance until the claims are rewritten to remove the indefinite language and ambiguous descriptions of the intended subject matter of the invention.
RESPONSE TO AMENDMENT
In response to the amendments filed August 5, 2026, most of the objections and rejections made in the previous Office action have now been withdrawn.
For the reasons explained above, some objections or rejections have been modified or newly added in response to the amendments.
CONCLUSION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to B. James Peikari at telephone number (571) 272-4185. The examiner can normally be reached M-F 8:30am - 5:30pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Kosowski can be reached at (571) 272-3744. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users.
To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format.
For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B. James Peikari/
Primary Examiner, Art Unit 3992
Prosecution Insights