Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. -An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a
specified function without the recital of structure, material, or acts in support thereof, and such claim
shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain
meaning of the claim language in light of the specification as it would be understood by one of ordinary
skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as
a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35
U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong
test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term "means" or "step" or a term used as a substitute for "means"
that is a generic placeholder (also called a nonce term or a non-structural term having no
specific structural meaning) for performing the claimed function;
(B) the term "means" or "step" or the generic placeholder is modified by functional language,
typically, but not always linked by the transition word "for" (e.g., "means for") or another linking
word or phrase, such as "configured to" or "so that"; and
(C) the term "means" or "step" or the generic placeholder is not modified by sufficient structure,
material, or acts for performing the claimed function.
Use of the word "means" (or "step") in a claim with functional language creates a rebuttable
presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35
U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C.
112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient
structure, material, or acts to entirely perform the recited function.
Absence of the word "means" (or "step") in a claim creates a rebuttable presumption that the
claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth
paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-
AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without
reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word "means" (or "step") are being interpreted
under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an
Office action. Conversely, claim limitations in this application that do not use the word "means" (or
"step") are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph,
except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word "means," but
are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph,
because the claim limitation(s) uses a generic placeholder that is coupled with functional language
without reciting sufficient structure to perform the recited function and the generic placeholder is not
preceded by a structural modifier.
Such claim limitation(s) is/are:
"the load counting hardware structure (…) configured to" in claims 1 and 10 ;
“configuration unit (…) configured to”, “the trigger unit (…) configured to ” in claim 2;
"calculation unit (…) configured to" in claims 2, 6 and 8;
"memory read/write unit (…) configured to" in claims 2 and 3;
“the first trigger information (…) configured to " and “the second trigger information (…) configured to” in claim 4;
“the dynamic voltage and frequency scaling controller (…) configured to” in claim 9 and 15
“the counting module (…) configured to” in claims 17, 19, and 20
“the updating module (…) configured to” in claim 18
“the counting submodule (…) configured to” in claims 19
“the acquisition unit (…) configured to ” in claim 20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA
35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure
described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or
pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them
being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting
sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim
limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being
interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
For clarity of the record, the Examiner would like to point to the claims of those limitations mentioned above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or
composition of matter, or any new and useful improvement thereof, may obtain a patent
therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an
abstract idea without significantly more.
1. An electronic device, comprising:
one or more processors, a load counting hardware structure, and a system memory, wherein: the one or more processors are connected to the load counting hardware structure; the one or more processors and the load counting hardware structure are respectively connected to the system memory; and the load counting hardware structure is configured to
respond to first trigger information to count a first load corresponding to each processor and a second load corresponding to each task in a window period,
and update each of the first load and the second load to the system memory.
Claim 1 Step 1:
Claim 1 is directed to a load counting method, the method comprising: a series of steps, and is therefore directed to a process, which is one of the four statutory categories.
Claim 1 Step 2A, Prong One:
Limitation(s) 1 b can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and is/are therefore reciting a mental process.
Accordingly, claim 1 recites a judicial exception (i.e., an abstract idea).
Claim 1 Step 2A, Prong Two:
Limitation(s) 1 a provide(s) mere instructions to implement the limitations which can be performed in the human mind, i.e., the judicial exception, on a computer, which is not indicative of integration into a practical application. See MPEP 2106.04(d) and 2106.0S(f).
Limitation(s) 1 c amount(s) to insignificant extra-solution activity of necessary data gathering/outputting, as it is merely outputting the result of the judicial exception, which is not indicative of integration into a
practical application. See MPEP 2106.04(d) and 2106.0S(g).
Claim 1Step 2B:
The combination of these elements amount to a method comprising steps which can
be performed mentally on a computer and comprising a step of insignificant extra-solution and well-understood, routine and conventional activity. Therefore, these elements, when considered individually and in combination, fail to add an inventive concept to the claim. Consequently, claim 1 as a whole does not amount to significantly more than the recited judicial exceptions and the claim is not eligible.
The following claim inherits from claim 1 and therefore inherits its rejection.
2. The electronic device according to claim 1,
wherein the load counting hardware structure includes a trigger unit, a configuration unit, a memory read/write unit, and a calculation unit, wherein: the configuration unit is an interface for interaction between the processor and the load counting hardware structure, and is configured to
obtain the first trigger information from the processor;
the trigger unit is configured to receive the first trigger information sent by the configuration unit and
generate a trigger instruction corresponding to the first trigger information;
the calculation unit is configured to respond to the trigger instruction, count each of the first load and the second load in the window period,
and store each of the first load and the second load in the memory read/write unit;
and the memory read/write unit is configured to update each of the first load and the second load to the system memory using the window period as an update period.
Limitation(s) 2 e can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and is/are therefore reciting a mental process.
Limitation(s) 2 a provide(s) mere instructions to implement the limitations which can be performed in the human mind, i.e., the judicial exception, on a computer, which is not indicative of integration into a practical application.
Limitation(s) 2 b,c,d,f,g amount(s) to insignificant extra-solution activity of necessary data gathering/outputting, as it is merely outputting the result of the judicial exception, which is not indicative of integration into a practical application.
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
The following claim inherits from claim 2 and therefore inherits its rejection.
3. The electronic device according to claim 2, wherein:
the memory read/write unit is configured to
respond to the first trigger information or second trigger information to store each of the first load and the second load in a last window period into the system memory,
and clear the memory read/write unit, wherein the second trigger information is configured to trigger a counting end of the window period.
Limitation(s) 3 a provide(s) mere instructions to implement the limitations which can be performed in the human mind, i.e., the judicial exception, on a computer, which is not indicative of integration into a practical application.
Limitation(s) 3 b,c amount(s) to insignificant extra-solution activity of necessary data gathering/outputting, as it is merely outputting the result of the judicial exception, which is not indicative of integration into a practical application.
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
The following claim inherits from claim 3 and therefore inherits its rejection.
4. The electronic device according to claim 3, wherein: the
second trigger information and the first trigger information occur at different time points, wherein the first trigger information is configured to trigger a start of counting in the window period, and the second trigger information is configured to trigger an end of counting in the window period.
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
The following claim inherits from claim 3 and therefore inherits its rejection.
5. The electronic device according to claim 3, wherein: the second trigger information and the first trigger information occur at a same time point, wherein a start time of a next window period is an end time of a last window period.
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
The following claim inherits from claim 3 and therefore inherits its rejection.
6. The electronic device according to claim 3, wherein:
in the window period, in response to task switching information, the calculation unit is configured to trigger a task load counting, to respectively count the second load corresponding to each task that is switched;
and in response to the second trigger information, the calculation unit is configured to accumulate the second load corresponding to each processor to obtain each first load.
Limitation(s) 6 a,b e can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and is/are therefore reciting a mental process.
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
The following claim inherits from claim 6 and therefore inherits its rejection.
7. The electronic device according to claim 6, wherein: the task is allocated to a matching CPU core of the processor according to a value of the second load corresponding to the task.
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
The following claim inherits from claim 6 and therefore inherits its rejection.
8. The electronic device according to claim 6,
wherein the calculation unit is configured to
count a target second load in the window period, wherein the target second load is a load corresponding to a target task,
the calculation unit is further configured to obtain a computing power factor of a processor that executes the target task, wherein the computing power factor is related to a frequency and computing power of the processor;
and count the target second load at least based on the computing power factor, a length of the window period, and a start time and an end time of the target task in the window period.
Limitation(s) 8 b,d e can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and is/are therefore reciting a mental process.
Limitation(s) 8 a provide(s) mere instructions to implement the limitations which can be performed in the human mind, i.e., the judicial exception, on a computer, which is not indicative of integration into a practical application.
Limitation(s) 8 c amount(s) to insignificant extra-solution activity of necessary data gathering/outputting, as it is merely outputting the result of the judicial exception, which is not indicative of integration into a practical application.
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
The following claim inherits from claim 1 and therefore inherits its rejection.
9. The electronic device according to claim 1, further comprising
a dynamic voltage and frequency scaling controller, wherein: the dynamic voltage and frequency scaling controller is connected to the load counting hardware structure;
and the dynamic voltage and frequency scaling controller is configured to dynamically adjust an operating frequency and a voltage of the processor.
Limitation(s) 9 a provide(s) mere instructions to implement the limitations which can be performed in the human mind, i.e., the judicial exception, on a computer, which is not indicative of integration into a practical application.
Limitation(s) 9 b provide(s) mere instructions to implement to apply the abstract idea, which is not indicative of integration into a practical application. See MPEP 2106.05(f)).
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
Claim 10 corresponds to claim 1 and therefore inherits the same rejection.
10. A load counting method,
applicable to an electronic device at least including one or more processors, a load counting hardware structure and a system memory, wherein: the load counting hardware structure is configured to execute a load counting method; and the load counting method includes:
in response to first trigger information, counting a first load corresponding to each processor and a second load corresponding to each task in a window period;
and updating each of the first load and the second load to the system memory.
Claim 11 corresponds to claim 3 and therefore inherits its rejections.
11. The method according to claim 10, wherein updating each of the first load and the second load to the system memory includes:
in response to the first trigger information or second trigger information, storing each of the first load and the second load in a last window period of the window period into the system memory,
and clearing a memory read/write unit of the load counting hardware structure, wherein the second trigger information is configured to trigger an end of counting in the window period.
Claim 12 corresponds to claim 6 and therefore inherits the same rejection.
12. The method according to claim 11, wherein counting each of the first load and the second load in the window period includes:
in response to task switching information, triggering task load counting to respectively count the second load corresponding to each task that is switched;
and in response to the second trigger information, accumulating each second load corresponding to each processor to obtain each first load.
Claim 13 corresponds to claim 8 and therefore inherits the same rejection.
13. The method according to claim 12, further comprising:
counting a target second load corresponding to a target task in the window period,
by performing: obtaining a computing power factor of a processor that executes the target task, wherein the computing power factor is related to a frequency and computing power of the processor;
and counting the target second load at least based on the computing power factor, a length of the window period, and a start time and an end time of the target task in the window period.
14. A frequency modulation method, applicable to an electronic device,
wherein the electronic device at least includes one or more processors, a load counting hardware structure, a system memory, and a dynamic voltage and frequency scaling controller, wherein the dynamic voltage and frequency scaling controller is connected to the load counting hardware structure, the frequency modulation method comprising:
performing load counting by the load counting hardware structure, including:
in response to first trigger information, counting a first load corresponding to each processor and a second load corresponding to each task in a window period; and when the first load of a target processor of the one or more processors is determined to be greater than a load threshold,
the load counting hardware structure sending a trigger signal to the dynamic voltage and frequency scaling controller,
triggering the dynamic voltage and frequency scaling controller to read the first load of the target processor for adjusting a frequency of the target processor.
Limitation(s) 14 b can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and is/are therefore reciting a mental process.
Limitation(s) 14 a provide(s) mere instructions to implement the limitations which can be performed in the human mind, i.e., the judicial exception, on a computer, which is not indicative of integration into a practical application.
Limitation(s) 14 c,d amount(s) to insignificant extra-solution activity of necessary data gathering/outputting, as it is merely outputting the result of the judicial exception, which is not indicative of integration into a practical application.
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
The following claim inherits from claim 14 and therefore inherits its rejection.
15. The method according to claim 14, wherein:
the dynamic voltage and frequency scaling controller is configured to adjust an operating frequency and a voltage of the processor, according to a computing power requirement of the task operating on the processor.
Limitation(s) 15 a provide(s) mere instructions to implement to apply the abstract idea, which is not indicative of integration into a practical application.
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
The following claim inherits from claim 16 and therefore inherits its rejection.
16. The method according to claim 14, wherein:
the load counting hardware structure is implemented by a logic circuit.
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
The following claim inherits from claim 14 and therefore inherits its rejection.
17. The method according to claim 14, wherein the load counting hardware structure includes
a counting module and an updating module, wherein: the counting module is configured to
respond to the first trigger information and calculate a first load corresponding to each processor and a second load corresponding to each task in the window period;
and the updating module is configured to update each of the first load and the second load to the system memory.
Limitation(s) 17 b can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and is/are therefore reciting a mental process.
Limitation(s) 17 a provide(s) mere instructions to implement the limitations which can be performed in the human mind, i.e., the judicial exception, on a computer, which is not indicative of integration into a practical application.
Limitation(s) 17 c amount(s) to insignificant extra-solution activity of necessary data gathering/outputting, as it is merely outputting the result of the judicial exception, which is not indicative of integration into a practical application.
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
The following claim inherits from claim 17 and therefore inherits its rejection.
18. The method according to claim 17, wherein:
the updating module is further configured to,
in response to the first trigger information or second trigger information, store each of the first load and the second load of a last window period into the system memory,
and clear the memory read/write unit of the load counting hardware structure, wherein the second trigger information is configured to trigger an end of counting in the window period.
Limitation(s) 18 a can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and is/are therefore reciting a mental process.
Limitation(s) 18 b,c amount(s) to insignificant extra-solution activity of necessary data gathering/outputting, as it is merely outputting the result of the judicial exception, which is not indicative of integration into a practical application.
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
The following claim inherits from claim 18 and therefore inherits its rejection.
19. The method according to claim 18,
wherein the updating module includes a counting submodule and an accumulation submodule, wherein:
the counting submodule is configured to trigger task load counting in response to task switching information, to respectively count the second load corresponding to each task that is switched;
and the accumulation submodule is configured to, in response to the second trigger information, accumulate each second load corresponding to each processor to obtain each first load.
Limitation(s) 19 b,c can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and is/are therefore reciting a mental process.
Limitation(s) 19 a provide(s) mere instructions to implement the limitations which can be performed in the human mind, i.e., the judicial exception, on a computer, which is not indicative of integration into a practical application.
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
The following claim inherits from claim 19 and therefore inherits its rejection.
20. The method according to claim 19,
wherein the counting submodule includes an acquisition unit and a counting unit, wherein:
the acquisition unit is configured to acquire a computing power factor of the processor executing a target task, wherein the computing power factor is related to a frequency and computing power of the processor;
and the counting unit is configured to count a target second load at least based on the computing power factor, a duration of the window period, and a start time and an end time of the target task in the window period.
Limitation(s) 20 c can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and is/are therefore reciting a mental process.
Limitation(s) 20 a provide(s) mere instructions to implement the limitations which can be performed in the human mind, i.e., the judicial exception, on a computer, which is not indicative of integration into a practical application.
Limitation(s) 20 b amount(s) to insignificant extra-solution activity of necessary data gathering/outputting, as it is merely outputting the result of the judicial exception, which is not indicative of integration into a practical application.
An integration into a practical application is not substantiated from the above. Thus, the claim is
not eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,2,10,17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0379953 A1, Heyrman, 2013-06-24 in view of KR 20230057084 A, Kwun, 2023-04-28.
Heyrman teaches the following.
1. An electronic device, comprising:
one or more processors, a load counting hardware structure, and a system memory, wherein: the one or more processors are connected to the load counting hardware structure; the one or more processors and the load counting hardware structure are respectively connected to the system memory;
[0006] The present invention is generally directed to a method and system for accumulating hardware counts by maintaining a current count value for a counted event of a hardware component of an electronic system in a hardware counter unit, and sending the current count value to a memory controller which controls access to a system memory device of the electronic system. The memory controller responsively updates an accumulated count value stored in the system memory device of the electronic system using the current count value.
[0036] Computer system 10 has a plurality of hardware counter units (HCUs) 50 embedded in different components of the system. In the depicted embodiment, HCUs are provided in each of the host processors 12a, 12b, and in the interconnection fabric
to count a first load corresponding to each processor
[0004] In addition to counting events between a start and a stop event, it is often desirable to see if the number of counted events exceeds a given threshold, or to measure how frequently the number of counted events exceeds the threshold. In order to provide this additional functionality, the hardware can support a threshold register which contains the value against which the total number of counted events is to be compared. Values in hardware counter registers may be swapped out with previously stored values as part of a context switch which changes the state of the processor
This total number of events corresponds to a total amount of work, or load.
and a second load corresponding to each task in a window period,
[0006] The present invention is generally directed to a method and system for accumulating hardware counts by maintaining a current count value for a counted event of a hardware component of an electronic system in a hardware counter unit
[0005] Due to the complexity of today's processors, there is a large number of different types of events that can be counted, as well as a large number of different possible start and stop events that need to be specified. The typical numbers of counted events between start and stop events for a complex computer system can vary over a huge range. For example, some pairs of start and stop events may be separated by only a few counted events, whereas other pairs of events may be separated by a million or more counted events.
Here an event corresponds to a task and the window interval between start and stop events corresponds to a window period.
and update each of the first load and the second load to the system memory.
[0006] The present invention is generally directed to a method and system for accumulating hardware counts by maintaining a current count value for a counted event of a hardware component of an electronic system in a hardware counter unit, and sending the current count value to a memory controller which controls access to a system memory device of the electronic system. The memory controller responsively updates an accumulated count value stored in the system memory device of the electronic system using the current count value.
Heyrman does not teach the following.
and (…) configured to respond to first trigger information
Kwun does however.
Page 8, Paragraph 4: Here, the optimization performance trigger unit may initiate execution of blockchain resource optimization in response to an input from a manager.
Kwun provides a response initiated by a trigger. It would have been obvious to one skilled in the art to modify Heyrman’s design with this element as this would confer a reliable sequence in which the counter could be anticipated to initiate.
The following claim inherits from claim 1 and therefore inherits its rejections.
2. The electronic device according to claim 1, wherein the load counting hardware structure includes
Heyrman teaches the following.
a configuration unit,
[0026] In this embodiment, PCI link 20c connects MC/HB 16 to a service processor interface 30 to allow communications between I/O device 24a and a service processor 32. Service processor 32 is connected to processors 12a, 12b via a JTAG interface 34, and uses an attention line 36 which interrupts the operation of processors 12a, 12b. Service processor 32 may have its own local memory 38, and is connected to read-only memory (ROM) 40 which stores various program instructions for system startup. Service processor 32 may also have access to a hardware operator panel 42 to provide system status and diagnostic information.
a memory read/write unit,
[0036] Data from an HCU is periodically sampled by a sending unit. The function of the sending unit is to combine addressing and data into a record set and then initiate posting those record sets to large memory tables in system memory 18.
and a calculation unit,
[0036] Computer system 10 has a plurality of hardware counter units (HCUs) 50 embedded in different components of the system. In the depicted embodiment, HCUs are provided in each of the host processors 12a, 12b, and in the interconnection fabric 28. The HCUs count performance events local to the source component without loss.
wherein: the configuration unit is an interface for interaction between the processor and the load counting hardware structure, and is configured to obtain (…) from the processor;
[0026] In this embodiment, PCI link 20c connects MC/HB 16 to a service processor interface 30 to allow communications between I/O device 24a and a service processor 32. Service processor 32 is connected to processors 12a, 12b via a JTAG interface 34, and uses an attention line 36 which interrupts the operation of processors 12a, 12b. Service processor 32 may have its own local memory 38, and is connected to read-only memory (ROM) 40 which stores various program instructions for system startup. Service processor 32 may also have access to a hardware operator panel 42 to provide system status and diagnostic information.
the calculation unit is configured to (…), count each of the first load and the second load in the window period, and store each of the first load and the second load in the memory read/write unit;
[0036] Computer system 10 has a plurality of hardware counter units (HCUs) 50 embedded in different components of the system. In the depicted embodiment, HCUs are provided in each of the host processors 12a, 12b, and in the interconnection fabric 28. The HCUs count performance events local to the source component without loss.
and the memory read/write unit is configured to update each of the first load and the second load to the system memory using the window period as an update period.
[0036] Data from an HCU is periodically sampled by a sending unit. The function of the sending unit is to combine addressing and data into a record set and then initiate posting those record sets to large memory tables in system memory 18.
[0038] Sending unit 52 forms an address offset based on a function of time, monitored event data, and the source domain. Each update set may consist of multiple records.
Heyrman does not teach the following.
includes a trigger unit,
Kwun does however.
Page 8, Paragraph 4: Here, the optimization performance trigger unit may initiate execution of blockchain resource optimization in response to an input from a manager.
Heyrman does not teach the following.
the trigger unit is configured to receive the first trigger information sent by the configuration unit and generate a trigger instruction corresponding to the first trigger information;
Kwun does however.
Page 8, Paragraph 4: Here, the optimization performance trigger unit may initiate execution of blockchain resource optimization in response to an input from a manager.
Kwun provides a trigger unit. It would have been obvious to one skilled in the art to modify Heyrman’s design with this element as this would confer a reliable sequence in which the counter could be anticipated to initiate.
The following claim corresponds to claim 1 and therefore inherits its rejections.
10. A load counting method, applicable to an electronic device at least including one or more processors, a load counting hardware structure and a system memory, wherein: the load counting hardware structure is configured to execute a load counting method; and the load counting method includes: in response to first trigger information, counting a first load corresponding to each processor and a second load corresponding to each task in a window period; and updating each of the first load and the second load to the system memory.
The following claim corresponds to claim 1 and therefore inherits its rejections.
17. The method according to claim 14, wherein the load counting hardware structure includes a counting module and an updating module, wherein: the counting module is configured to respond to the first trigger information and calculate a first load corresponding to each processor and a second load corresponding to each task in the window period; and the updating module is configured to update each of the first load and the second load to the system memory.
Claim(s) 3,4,11,18, is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0379953 A1, Heyrman, 2013-06-24 in view of KR 20230057084 A, Kwun, 2023-04-28, as well as in further view of US 20110080611 A1, Komatsu, 2010-04-20 and US 9846449 B1, Schumacher, 2014-07-02.
The following claim inherits from claim 2 and therefore inherits its rejections.
3. The electronic device according to claim 2, wherein: the memory read/write unit is configured to respond to the first trigger information or second trigger information
to store each of the first load and the second load (…) into the system memory, (…) wherein the second trigger information is configured to trigger (…) of the window period.
Heyrman in view of Kwun teaches the following.
in a last window period
[0005] Due to the complexity of today's processors, there is a large number of different types of events that can be counted, as well as a large number of different possible start and stop events that need to be specified. The typical numbers of counted events between start and stop events for a complex computer system can vary over a huge range. For example, some pairs of start and stop events may be separated by only a few counted events, whereas other pairs of events may be separated by a million or more counted events.
It is implicit from there being a plurality of start and stop pairs (these corresponding to window periods) that the final pair would correspond to a last window period.
Heyrman in view of Kwun does not teach the following.
and clear the (…) memory unit,
Komatsu does however.
[0045] Next, the loading unit 43 clears the memory unit 431 and erases the program file P that is temporarily stored in the memory unit 431 (ACT S409).
Heyrman in view of Kwun does not teach the following.
trigger a counting end
Schumacher does however.
(10) The first detector circuit further includes: a first counter circuit coupled to an output of the latency circuit and calculating a total latency; a second counter circuit coupled to an output of at least one of the start trigger circuit and counting start events, or the end trigger circuit and counting end events; and a third counter circuit coupled to an output of the data trigger circuit and counting a total amount of data transferred.
Komatsu provides clearing a memory unit. Schumaker provides ending a counting process. It would have been obvious to one skilled in the art to modify Heyrman’s design in view of Kwun with these elements as these operations would allow subsequent iterations of counting.
The following claim inherits from claim 3 and therefore inherits its rejections.
4. The electronic device according to claim 3, wherein:
Heyrman in view of Kwun and Komatsu does not teach the following.
the second trigger information and the first trigger information occur at different time points, wherein the first trigger information is configured to trigger a start of counting in the window period, and the second trigger information is configured to trigger an end of counting in the window period.
Schumacher does however.
(10) An integrated circuit (IC) includes a universal monitor system having a first detector circuit. The first detector circuit includes a start trigger circuit receiving first signals of an interconnect, wherein the start trigger circuit detects a start event for a transaction from the first signals, an end trigger circuit receiving second signals of the interconnect, wherein the end trigger circuit detects an end event for the transaction from the second signals. The first detector circuit further includes a latency circuit coupled to an output of the start trigger circuit and an output of the end trigger circuit. The first detector circuit also includes a data trigger circuit receiving third signals of the interconnect and detecting transferred data from the third signals. The first detector circuit further includes: a first counter circuit coupled to an output of the latency circuit and calculating a total latency; a second counter circuit coupled to an output of at least one of the start trigger circuit and counting start events, or the end trigger circuit and counting end events; and a third counter circuit coupled to an output of the data trigger circuit and counting a total amount of data transferred.
Schumacher provides triggers occurring at start and end events. It would have been obvious to one skilled in the art to modify Heyrman’s design in view of Kwun and Komatsu with this element as these operations would allow subsequent iterations of counting.
The following claim corresponds to claim 3 and therefore inherits its rejections.
11. The method according to claim 10, wherein updating each of the first load and the second load to the system memory includes: in response to the first trigger information or second trigger information, storing each of the first load and the second load in a last window period of the window period into the system memory, and clearing a memory read/write unit of the load counting hardware structure, wherein the second trigger information is configured to trigger an end of counting in the window period.
The following claim corresponds to claim 3 and therefore inherits its rejections.
18. The method according to claim 17, wherein: the updating module is further configured to, in response to the first trigger information or second trigger information, store each of the first load and the second load of a last window period into the system memory, and clear the memory read/write unit of the load counting hardware structure, wherein the second trigger information is configured to trigger an end of counting in the window period.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0379953 A1, Heyrman, 2013-06-24 in view of KR 20230057084 A, Kwun, 2023-04-28, as well as in further view of US 20110080611 A1, Komatsu, 2010-04-20, US 9846449 B1, Schumacher, 2014-07-02 and US 9390043 B2, Grafton, 2012-12-17.
The following claim inherits from claim 3 and therefore inherits its rejections.
5. The electronic device according to claim 3, wherein:
Heyrman in view of Kwun and Komatsu, and Schumacher does not teach the following.
the second trigger information and the first trigger information occur at a same time point, wherein a start time of a next window period is an end time of a last window period.
Grafton does however.
(6) In one aspect, a system for controlling a sequence of events includes a plurality of programmable registers, each associated with one of a plurality of slave modules. Selection circuitry associates, based on the contents of one of the registers, one of the slave modules with one of the master modules. An input port receives, from the master module associated with the slave module, a trigger signal indicating completion of a first event at the master module. An output port sends, to the slave module associated with the master module, the trigger signal to thereby trigger a second event at the slave module.
Grafton provides the starting and ending of distinct events taking place simultaneously. It would have been obvious to one skilled in the art to modify Heyrman’s design in view of Kwun, Komatsu, and Schumacher with this element would allow subsequent iterations of counting to take place without delay.
Claim(s) 6,7,12,19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0379953 A1, Heyrman, 2013-06-24 in view of KR 20230057084 A, Kwun, 2023-04-28, as well as in further view of US 20110080611 A1, Komatsu, 2010-04-20, US 9846449 B1, Schumacher, 2014-07-02, US 9390043 B2, Grafton, 2012-12-17, and US 20160224375 A1, Chiao, 2015-06-26.
The following claim inherits from claim 3 and therefore inherits its rejections.
6. The electronic device according to claim 3, wherein:
in the window period, (…) and in response to the second trigger information, the calculation unit is configured to accumulate the second load corresponding to each processor to obtain each first load
Heyrman in view of Kwun, Komatsu, Schumacher does not teach the following.
in response to task switching information, the calculation unit is configured to trigger a task load counting, to respectively count the second load corresponding to each task that is switched;
Chiao does however.
[0008] In a third aspect of the invention, a method for performance monitoring of tasks executed by a computer system comprising a processing unit and a storage unit is provided, wherein the processing unit further includes a performance monitoring unit (PMU) for performance monitoring on the tasks and the tasks are switchable by the processing unit. The method comprises the steps of: providing, by the processing unit, a callback function at a location at which a task switch is being performed; resetting, by the processing unit, a counter for external access counting of the PMU when a first task switch which is to switch execution of tasks to a first task occurs; reading, by the processing unit, a counted value from the counter for external access counting of the PMU and recording the read value into a log of a storage unit as a record of the first task when a second task switch which is to switch the execution of the tasks from the first task to a second task occurs; and resetting, by the processing unit, the counter for external access counting of the PMU for the second task after the log is generated; wherein the records of the first task in the log within a predetermined time period are summed to analyze the performance of the first task within the predetermined time period so as to determine the performance of external access of the first task for a specific event.
Chiao provides counting in response to tasks being switched. It would have been obvious to one skilled in the art to modify Heyrman’s design in view of Kwun, Komatsu, Schumacher with this element as it would allow the system to accommodate task rerouting.
Heyrman view of Kwun, Komatsu, Schumacher teaches the following.
7. The electronic device according to claim 6, wherein: (…) according to a value of the second load corresponding to the task.
Heyrman in view of Kwun, Komatsu, Schumacher does not teach the following.
the task is allocated to a matching CPU core of the processor
Chiao does however.
[0029] In some embodiments, the processing unit 110 may further include two or more processing cores or CPUs and the processing unit may further be configured to reset the counter for external access counting of the PMU 112 when a fourth task switch which is to switch the execution of tasks to the first task at each processing core or CPU occurs,
Chiao provides allocating a task to core of the processor. It would have been obvious to one skilled in the art to modify Heyrman’s design in view of Kwun, Komatsu, Schumacher with this element as limiting a task to a single core can reduce the chance of interruption by other processes.
The following claim corresponds to claim 6 and therefore inherits its rejections.
12. The method according to claim 11, wherein counting each of the first load and the second load in the window period includes: in response to task switching information, triggering task load counting to respectively count the second load corresponding to each task that is switched; and in response to the second trigger information, accumulating each second load corresponding to each processor to obtain each first load.
The following claim corresponds to claim 6 and therefore inherits its rejections.
19. The method according to claim 18, wherein the updating module includes a counting submodule and an accumulation submodule, wherein: the counting submodule is configured to trigger task load counting in response to task switching information, to respectively count the second load corresponding to each task that is switched; and the accumulation submodule is configured to, in response to the second trigger information, accumulate each second load corresponding to each processor to obtain each first load.
Claim(s) 8,13,20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0379953 A1, Heyrman, 2013-06-24 in view of KR 20230057084 A, Kwun, 2023-04-28, as well as in further view of US 20110080611 A1, Komatsu, 2010-04-20, US 9846449 B1, Schumacher, 2014-07-02, US 9390043 B2, Grafton, 2012-12-17, and US 20160224375 A1, Chiao, 2015-06-26.
Claim 8 inherits from claim 6 and therefore inherits its rejections.
8. The electronic device according to claim 6,
wherein the calculation unit is configured to count a target second load in the window period, wherein the target second load is a load corresponding to a target task, the calculation unit is further configured to (…) and count the target second load at least based on the computing power factor, a length of the window period, and a start time and an end time of the target task in the window period.
Heyrman in view of Kwun, Komatsu, Schumacher does not teach the following.
obtain a computing power factor of a processor that executes the target task, wherein the computing power factor is related to a frequency and computing power of the processor; (…)
Girard does however.
4. PRESENTATION OF THE INVENTION In a particular embodiment of the invention, there is provided a method for managing the execution by a processor of a software architecture included in a radiocommunication circuit, said software architecture comprising a radio communication software stack and at least one client application. This method comprises the following steps, for a given frequency of said processor: a) obtaining a first computing power associated with said stack; b) and count the target second load at least based on the computing power factor,
Girard provides obtaining the power of a processor related to its frequency. It would have been obvious to one skilled in the art to modify Heyrman’s design in view of Kwun, Komatsu, Schumacher with this element as considering hardware limitations would provide a more comprehensive picture of system performance.
The following claim corresponds to claim 8 and therefore inherits its rejections.
13. The method according to claim 12, further comprising: counting a target second load corresponding to a target task in the window period, by performing: obtaining a computing power factor of a processor that executes the target task, wherein the computing power factor is related to a frequency and computing power of the processor; and counting the target second load at least based on the computing power factor, a length of the window period, and a start time and an end time of the target task in the window period.
The following claim corresponds to claim 8 and therefore inherits its rejections.
20. The method according to claim 19, wherein the counting submodule includes an acquisition unit and a counting unit, wherein: the acquisition unit is configured to acquire a computing power factor of the processor executing a target task, wherein the computing power factor is related to a frequency and computing power of the processor; and the counting unit is configured to count a target second load at least based on the computing power factor, a duration of the window period, and a start time and an end time of the target task in the window period.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0379953 A1, Heyrman, 2013-06-24 in view of KR 20230057084 A, Kwun, 2023-04-28 as well as in further view of CN 107430423 A LI, 2017-12-01.
The following claim inherits from claim 1 and therefore inherits its rejections.
9. The electronic device according to claim 1, further comprising
Heyrman does not teach the following.
a dynamic voltage and frequency scaling controller, wherein: the dynamic voltage and frequency scaling controller is connected to the load counting hardware structure; and the dynamic voltage and frequency scaling controller is configured to dynamically adjust an operating frequency and a voltage of the processor.
Li does however.
Page 2, Paragraph 9: According to another embodiment of the invention, a system comprises a plurality of hardware modules and dynamic voltage frequency adjusting controller. dynamic voltage frequency adjusting controller coupled to the plurality of hardware modules
Page 2, Paragraph 3: dynamic voltage and frequency adjustment (Dynamic voltage and frequency scaling (DVFS) is a power management technique effective for situation according to adjusting the clock frequency and supply voltage of the working load. can increase clock frequency and supply voltage to let the processor operation and has better performance at a higher speed, and also can reduce the clock frequency and supply voltage to save power.
Li provides a dynamic voltage and frequency controller. It would have been obvious to one skilled in the art to modify Heyrman’s design in view of Kwun with this element as considering hardware limitations would allow for balancing the hardware resources of the system.
Claim 14 in part corresponds to claim 9 and therefore inherits its rejections.
14. A frequency modulation method, applicable to an electronic device, wherein the electronic device at least includes one or more processors, a load counting hardware structure, a system memory, and a dynamic voltage and frequency scaling controller, wherein the dynamic voltage and frequency scaling controller is connected to the load counting hardware structure, the frequency modulation method comprising: performing load counting by the load counting hardware structure, including: in response to first trigger information, counting a first load corresponding to each processor and a second load corresponding to each task in a window period;
Heyrman teaches the following.
and when the first load of a target processor of the one or more processors is determined to be greater than a load threshold,
[0004] In order to provide this additional functionality, the hardware can support a threshold register which contains the value against which the total number of counted events is to be compared.
Heyrman in view of Kwun does not teach the following.
the load counting hardware structure sending a trigger signal to the dynamic voltage and frequency scaling controller, triggering the dynamic voltage and frequency scaling controller to read the first load of the target processor for adjusting a frequency of the target processor.
Li does however.
Page 4, Paragraph 2: In this embodiment, the DVFS controller set 110 is a hardware DVFS controller, which can process a fast DVFS operation. concentration of DVFS controller 110 can receive software information from dynamic energy management 152, the receiving CPU 130-1, GPU130-2, MM 130, 3, MD 130, 4 and MC 130 to 5 active. integrated DVFS controller 110 for providing a voltage control signal to the PMIC140, based on activity of the hardware module respectively controlling/adjusting the CPU 130-1,
Li provides a dynamic voltage and frequency controller adjusting a processor in response to a trigger signal. It would have been obvious to one skilled in the art to modify Heyrman’s design in view of Kwun with this element as this would allow for balancing the hardware resources of the system.
The following claim corresponds to claim 9 and therefore inherits its rejections.
15. The method according to claim 14, wherein: the dynamic voltage and frequency scaling controller is configured to adjust an operating frequency and a voltage of the processor, according to a computing power requirement of the task operating on the processor.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0379953 A1, Heyrman, 2013-06-24 in view of KR 20230057084 A, Kwun, 2023-04-28 as well as in further view of CN 107430423 A LI, 2017-12-01 and US 20160224375 A1, Chiao, 2015-06-26
The following claim inherits from claim 14 and therefore inherits its rejection.
16. The method according to claim 14, wherein: the load counting hardware structure is
Heyrman in view of Kwun, Li does not teach the following.
implemented by a logic circuit.
Chiao does however.
[0035] The embodiments of methods for performance monitoring of tasks that have been described, or certain aspects or portions thereof, may be practiced in logic circuits,
Chiao provides task monitoring (hardware counting) implemented via logic circuits. It would have been obvious to one skilled in the art to modify Heyrman’s design in view of Kwun and Li with this element as this is a conventional means of processing signals and making decisions within the art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Luke Absher whose telephone number is (571) 270-1057. The examiner can normally be reached M-F: 8:00 am - 4:00 pm. Examiner interviews are available via telephone, in person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the US PTO Automated Interview Request (AIR) at http:/ /www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Kevin Young can be reached at 571-270-3180.
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/LUCAS DONALD ABSHER/
Examiner, Art Unit 2194
/KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194
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