333331331DETAILED ACTION
Claims 1-20 are presented for examination.
The present application is being examined under the AIA (America Invents Act) First Inventor to File.
This Office Action is Non-Final.
Claims 1, 11 and 20 are independent claims. Claims 2-10,12-19 are dependent claims.
This action is responsive to the following communication: corresponding claims filed on 10-25-2024.
Continuation Application
This application discloses and claims only subject matter disclosed in prior Application No. 17/682,917 and names an inventor or inventors named in the prior application. Accordingly, this application constitutes a continuation claiming benefit of the filing date of November 30, 2021 which is acknowledged.
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. under 35 U.S.C. 120 (continuation) is acknowledged. Applicant has complied with one or more conditions for receiving the benefit of an earlier filing date:
i) The later filed Application is filed prior to the patent issued of the earlier application. (co-pendency; MPEP 211.01(b) (I))
ii) At least one common inventor (MPEP 201.07)
iii) The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10-25-2024 in compliance with the provisions of 37 CFR 1.97
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
For faster processing of Terminal Disclaimer the USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/ patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/ eTD-info-I.jsp.
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Claim Analysis
Claims 1-20 of the instant application are rejected under the judicially created doctrine of nonstatutory double patenting over claims 1-20 of U.S. Patent No. 12,093,101 since the claims, if allowed, would improperly extend the "right to exclude" already granted in the patent.
Although the claims at issue are not identical, they are not patentably distinct from each other because as illustrated by the table below, each feature claimed is directly mapped and taught by the cited prior art that is commonly owned. Thus, a later application claim is not patentably distinct from an earlier patent claim if the later claim is anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus).” ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claims 11 and 20 are directed to similar features recited in claim 1, thus are rejected for the same rational already presented for claim 1.
Instant Application 18/886,572
Patent No. 12,093,101
Claim 1
A method comprising:
determining, by one or more control circuitries of a device, according to a condition for the device, one or more performance characteristics
for a first device processing unit of a first type and a second device processing unit of a second type different from the first type,
distributing, by the one or more control circuitries, a first number of power credits to the first device processing unit and a second number of power credits to the second device processing units, according to the determined performance characteristics, to manage a respective peak power for the first device processing unit and the second device processing unit.
the one or more performance characteristics indicating an impact of a respective device processing unit to quality of service (QoS) for the device; and
Claim 1
A method comprising
identifying, by one or more control circuitries of a device, a condition for the device; applying, by the one or more control circuitries, the condition for the device to one or more models maintained for a plurality of device processing units of the device to determine one or more performance characteristics
for the plurality of device processing units,
each device processing unit having a respective peak power which is a portion of an aggregate peak power of the device, the plurality of device processing units including a first device processing unit comprising one of a central processing unit (CPU), a graphics processing unit (GPU), a display interface, a sensing unit, a compression unit, a camera unit, an input/output (I/O) unit, a decoder, or an encoder, and a second device processing unit comprising a different one of the CPU, the GPU, the display interface, the sensing unit, the compression unit, the camera unit, the I/O unit, the decoder, or the encoder; and distributing, by the one or more control circuitries,
power credits to the plurality of device processing units of the device, including a first number of power credits to the first device processing unit and a second number of power credits to the second device processing unit, according to the determined performance characteristics for the plurality of device processing units, to manage the respective peak power for each respective device processing unit according to a number of the power credits distributed to the respective device processing unit,
wherein the one or more control circuitries distributes the power credits to the plurality of device processing units, according to an impact of quality of service (QoS) levels for a respective device processing unit to a device QoS for the device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-13, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2014/0143558 (hereinafter, “Kuesel”) in view of U.S Publication No. 2021/0349512 (hreinafter, “Guim Bernat”).
As per claim(s) 1, 11, 20, 1 Kuesel discloses a method comprising:
determining, by one or more control circuitries (power management block; Fig 11A) of a device, according to a condition for the device, (the system may allocate power consumption at a component level of a processor based on the “priority, availability, and/or power consumption target” [abstract] or “system demands”, for example, type of “processing instructions” ¶ [0111],¶ [0078] ) one or more performance characteristics (¶ [0078] states “power management block may monitor and adjust power token allocation for the interconnected IP blocks based on data and/or characteristics associated with the interconnected IP blocks”) for a first device processing unit of a first type and a second device processing unit of a second type different from the first type, (abstract discloses that the system may predict “power consumption at a component level of a processor” , where Kuesel by way of example, discloses these components as at least being a NOC Coprocessor, processor 12, NOC video adapter (i.e, Graphics Display), ASIC CHIP, FPGAs and ...ect; ¶s [003]-[005], Fig 1. Indeed, ¶ [0032] states “a power consumption target may be set for a processor and/or particular components of a processor”)
the one or more performance characteristics indicating an impact of a respective device processing unit to quality of service (QoS) for the device; and (inter alia: ¶ [0113] states “the power management block may control high/low priority IP blocks with more power tokens for some IP blocks cores and less for lower priority service IP blocks”. It is therefore seen that the Office’s interpretation is consistent with Applicant’s Specification description of “implementing power credit management, hierarchical management, and/or allocation of power” by which WOS is broadly defined. )
distributing, by the one or more control circuitries, a first number of power credits to the first device processing unit and a second number of power credits to the second device processing units, according to the determined performance characteristics, to manage a respective peak power for the first device processing unit and the second device processing unit. (¶ [0102] states “the power management block may analyze one or more of the interconnected IP blocks to determine a power token allocation of each of the one or more of the IP blocks” and ¶ [0112] discloses a centralized power management block that may facilitate chip level management where “power tokens may be injected into one or more groups of interconnected IP blocks based on input from board level hardware, ”
Kuesel does not distinctly discloses where the claimed term quality of service (QOS) is more narrowly interpreted as a service contract.
However, Guim Bernat discloses that. In particular, Guim Bernat discloses the following:
determining, by one or more control circuitries (software stack; ¶ [0015] ) of a device, according to a condition for the device, (power credited needed; ¶[0015] one or more performance characteristics, (Application is running a bit stream; ¶ [0015] ) for a first device processing unit of a first type and a second device processing unit of a second type different from the first type, ( ¶ [0015] states “an application or software stack can perform device-to-device power crediting at a fine-grained level, e.g., to implement advanced quality of services policies. As one example, assume an Application X is running a bit-stream on an accelerator (e.g., a field programmable gate array (FPGA)) and the application is in execution on a central processing unit (CPU). Assume Application X is at a phase where the bit-stream requires more power. With an embodiment, power credits can be transferred from the CPU (e.g., cores that are mapped into the application) to the accelerator where the bit-stream is executed.” )
the one or more performance characteristics indicating an impact of a respective device processing unit to quality of service (QoS) for the device; and (¶ [0015] states “an application or software stack can perform device-to-device power crediting at a fine-grained level, e.g., to implement advanced quality of services policies.” )
distributing, by the one or more control circuitries, a first number of power credits to the first device processing unit and a second number of power credits to the second device processing units, according to the determined performance characteristics, to manage a respective peak power for the first device processing unit and the second device processing unit. (¶ [0015] discloses power credits can be transferred to the “accelerator where the bit-stream is executed.” In other words, power credits may be allocated to one or more processing units having particular IDs as further illustrated by Fig 2 )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Kuesel and Guim Bernat because both references are in the same field of endeavor. Guim Bernat’s teaching of service contract policy would enhance Kuesel's system by achieving a certain quality agreements, thus improving contract fulfillments between servicers and consumers.
As per claim(s) 2, Kuesel as modified discloses a method further comprising: determining, by the one or more control circuitries, the condition for the device. (Kuesel: (the system may allocate power consumption at a component level of a processor based on the “priority, availability, and/or power consumption target” [abstract] or “system demands”, for example, type of “processing instructions” ¶ [0111],¶ [0078] )
As per claim(s) 3, 12, Kuesel as modified discloses a method wherein the first device processing unit comprises one of a central processing unit (CPU), a graphics processing unit (GPU), a display interface, a sensing unit, a compression unit, a camera unit, an input/output (I/O) unit, a decoder, or an encoder, and a second device processing unit comprising a different one of the CPU, the GPU, the displayinterface, the sensing unit, the compression unit, the camera unit, the I/O unit, the decoder, or the encoder. (Kuesel: NOC video adapter 26, NOC coprocessor 28, bus adapter 18, ASIC chip designs or FPGA logic; Fig. 1, ¶ [004]) & (Guim Bernat: Accelerator 130, which may be an artificial intelligence (Al) accelerator, may include acceleration circuitry 134; pooled memories 140, 160 may include corresponding dual inline memory modules (DIMMs) 144.sub.0-N and 164.sub.0-N. In turn, GPU 150 includes a GPU circuit 154; ¶ [0025] and FPGA/CPU ¶ [0015] )
As per claim(s) 4, 13, Kuesel as modified discloses a method wherein a respective device processing unit manages peak power by managing a data throughput according to the number of the power credits distributed to the respective device processing unit. (Kuesel: the first IP block may execute only the number of instructions indicated by allocated power tokens for a given time period, or the first IP block may run for only the indicated run time for a given time period.; ¶ [0082])
As per claim(s) 6, 15, Kuesel as modified discloses a method wherein the one or more performance characteristics comprise at least one of a predicted peak power consumption, a predicted execution completion deadline, or a predicted slack time. (Kuesel: The IP block may predict a requirement for additional power and analyzing a run time associated with operations to be performed by the IP block ¶ [0093]. Also, The IP block may predict a requirement for additional power by monitoring an instruction queue associated with the IP block, monitoring memory transaction operations queued to be performed by the IP block, and/or analyzing a run time associated with operations to be performed by the IP block ¶[0030]) & (Guim Bernat: overall fixed power budget can be dynamically shared, even among device) .
As per claim(s) 7, 16, Kuesel as modified discloses a method further comprising receiving, by the one or more control circuitries, a request for additional power credits from the first device processing unit. (Kuesel: additional power is required by an IP block [Abstract])
As per claim(s) 8, 17, Kuesel as modified discloses a method further comprising allocating, by the one or more control circuitries, one or more additional power credits to the first device processing unit from at least one of the following: a remaining number of available credits; or from a different device processing unit, according to a first QoS level for the first device processing unit relative to the device QoS, and a second QoS level for the different device processing unit relative to the device QoS. (Kuesel: inter alia: determine available allocated power tokens (block 246); ¶ [0090] or The dynamic reallocation of power tokens between interconnected IP blocks allows reallocation of power consumption within the power consumption target for interconnected IP blocks ¶ [0026] ) & ((Guim Bernat: allocating power credits from CPU to FPGA accelerator based on stream execution; ¶ [0015]) .
As per claim(s) 9, 18, Kuesel as modified discloses a method wherein the one or more control circuitries allocate the one or more additional power credits to the first device processing unit from the different device processing unit, by recalling the one or more additional power credits from the different device processing unit and granting the one or more additional power credits to the first device processing unit. (Kuesel” he one or more interconnected IP blocks may each receive the request and determine whether any allocated power tokens are available to reallocate to the requesting IP block ¶ [0028] and he one or more interconnected IP blocks may each receive the request and determine whether any allocated power tokens are available to reallocate to the requesting IP block ¶ [0009]) & (Guim Bernat: With an embodiment, power credits can be transferred from the CPU (e.g., cores that are mapped into the application) to the accelerator where the bit-stream is executed. ¶[0015] )
As per claim(s) 10, 19, Kuesel as modified discloses a method further comprising:receiving, by the one or more control circuitries, from the first device processing unit, a request to recall a power credit allocated to the first device processing unit;recalling, by the one or more control circuitries, the power credit from the first device processing unit. (Kuesel” he one or more interconnected IP blocks may each receive the request and determine whether any allocated power tokens are available to reallocate to the requesting IP block ¶ [0028] and he one or more interconnected IP blocks may each receive the request and determine whether any allocated power tokens are available to reallocate to the requesting IP block ¶ [0009]) & (Guim Bernat: With an embodiment, power credits can be transferred from the CPU (e.g., cores that are mapped into the application) to the accelerator where the bit-stream is executed. ¶[0015] )
Claim(s) 5, 14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2014/0143558 (hereinafter, “Kuesel”) in view of U.S Publication No. 2021/0349512 (hreinafter, “Guim Bernat”) and further view of U.S. Publication No. 2021/0200481 (hereinafter, “Buxton”).
As per claim(s) 5, 14, Kuesel as modified discloses a method wherein a respective device processing unit manages peak power execution of one or more processes to be performed by the device processing unit, according to the power credits allocated to the device processing unit. (Kuesel: may allocate power tokens to IP blocks for a given time period such that total power consumption is divided between the IP blocks. ¶ [0026] and a maximum quantity of allocated power tokens may be associated with such IP blocks such that the power consumption may be controlled and limited ¶ [0032] )
Kuesel as modified does not distinctly discloses delaying execution.
However, Buxton discloses delaying execution. (¶ [0042] )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Kuesel as modified and Buxton because all references are in the same field of endeavor. Buxton’s teaching of delaying execution would enhance Kuesel's as modified system by preventing system from failure due to lack of sufficient power, thus enhancing power management.
Conclusion
With respect to any newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See MPEP §714.02 and § 2163.06. For example, when responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov
1 As per independent claim(s) 11 and 20, these claims are substantially equivalent to method claim 1, because the additional feature(s) are present on any off the shelf general-purpose computer. Therefore, for at least this reason, claims 11 and 20 also stand rejected. Indeed, at least Fig. 1 illustrates data processing system 10 having at least one memory, for example, RAM 14, that is capable to store “instructions to execute, a quantity of memory transactions to perform, and/or other such types of power consumption metrics”.