Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This is in response to the preliminary amendment filed on 9/16/24. Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 15 recites a “device” in the preamble only, the body of the claim merely contains programming steps. Therefore, the claim is a program per se and is not tangibly embodied and therefore not a “device”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-9 and 11-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lloyd et al., US. No.20100299401.
As to claim 1, Lloyd discloses a method for assigning an address to an electronic device , the method comprising:
starting a test system (master device 102 fig.1b) for performing a test of a circuit arrangement comprising the electronic device (106A or 106B of fig.1B, implementing a communication protocol between the circuit arrangement and the test system, reading out a predetermined unique identifier (UID) of the electronic device by using the test system (broadcasting packet/configuration request message that is sent from the slave device 106A, 106B to the master device 102 includes a global unique identifier, see fig.1B, [0023]);
assigning the UID to at least one property of the electronic device within a lookup table , wherein the property is determined by using the test system and assigning an address to the electronic device by using the lookup table (the master device 102 to create a lookup table relating the GUID to an assigned network address unique among the devices, see [0023]).
As to claim 2, Lloyd discloses wherein the property of the electronic device comprises a position of the electronic device in the circuit arrangement (see [0024]).
As to claim 3, Lloyd discloses wherein the circuit arrangement comprises a plurality of electronic devices , wherein the method comprises assigning an individual address to each of the plurality of electronic devices (106A, 106B fig.1B of the circuit arrangement (assigning addresses for devices, see [0023] to [0024]).
As to claim 4, Lloyd discloses wherein at least two of the plurality of electronic devices are of the same type, wherein the at least two electronic devices of the same type are assigned different addresses (a device type identifier may also be provided by the slave device 106A, 106B in the broadcast packet for assistance in ID assignment, see [0023]).
As to claim 6, Lloyd discloses the electronic device is a part of a network and wherein the address is a network address (constructing an address table of all connected devices on the network medium 104 based on the received broadcast messages and assigned network addresses, see [0024] to [0025]).
As to claim 7, Lloyd discloses the communication protocol determines at least a set of addresses, wherein the set of addresses comprises at least a set of available addresses, wherein assigning the address step comprises assigning at least one of the UID and the property of the electronic device determined by using the test system to an available address (constructing an address table of all connected devices on the network medium 104 based on the received broadcast messages and assigned network addresses, see [0024]).
As to claim 8, Lloyd discloses the communication protocol determines at least a set of commands for communication between the circuit arrangement and the test system, wherein the set of commands comprises at least one general command sent out to all electronic devices comprised by the circuit arrangement (issuing a command over the network medium using the selected network address, directly addressed to the selected network address, see [0026] to [0027]).
As to claim 9, Lloyd discloses wherein the readout of the UID in step is triggered by detecting a predetermined logical state of the electronic device with the test system, wherein the logical state is determined in the communication protocol (The slave devices are operative in a slave mode/master mode, see [0035]}.
As to claim 11, Lloyd discloses wherein at least one of step d) and step e) assigning the UID to at least one property of the electronic device within a lookup table and assigning an address to the electronic device by using the lookup table is at least partially performed by using the test system (providing a look-up mechanism to translate the name or GUID into the appropriate network address, see [0024] to [0025]).
As to claim 12, Lloyd discloses at least one of step d) and step assigning the UID to at least one property of the electronic device within a lookup table and assigning an address to the electronic device by using the lookup table is at least partially performed by using a controller (providing a look-up mechanism to translate the name or GUID into the appropriate network address, see [0024]).
As to claim 13, Lloyd discloses wherein at least one of step d) and step e) assigning the UID to at least one property of the electronic device within a lookup table and assigning an address to the electronic device by using the lookup table is performed at an initial power-on of the circuit arrangement ( configured to be in the pseudo-master mode automatically upon applying power to the slave device, see [0043]).
Claims 15-16 are rejected for the same reasons set forth in claims 1, 1 respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 10, 14, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lloyd as in above and in view of Spica et al. US Pub. No.20200191869.
As to claim 5 Lloyd does not specifically disclose at least one printed circuit board (PCB), wherein the test of the circuit arrangement is an in-circuit testing (ICT), wherein the test system is an ICT system. However, Spica discloses at least one printed circuit board (PCB), wherein the test of the circuit arrangement is an in-circuit testing (ICT), wherein the test system is an ICT system (path placement on the printed circuit board (PCB) to provide access to the ICT device to facilitate testing on devices, see [0012], [0028]). It would have been obvious to one of the ordinary in the art before the effective filing date of the invention was made to implement Spica’s teachings into the computer system of Lloyd to test devices because it would have reduced potential redundant efforts made in developing test coverage via firmware implementation with system constraints (see Spica’s [0013]).
As to claims 10 and 14, Lloyd discloses the predetermined logical state comprises a predetermined voltage applied to at least one pin of the electronic device and starting the test system comprises connecting the test system with an interface of the circuit arrangement y using an adapter of the test system, wherein step starting the test system further comprises contacting a pin of the electronic device by using the adapter. However, Spica discloses the predetermined logical state comprises a predetermined voltage applied to at least one pin of the electronic device and starting the test system comprises connecting the test system with an interface of the circuit arrangement y using an adapter of the test system, wherein step starting the test system further comprises contacting a pin of the electronic device by using the adapter (using test pin for testing devices, see [0022] to [0026]). It would have been obvious to one of the ordinary in the art before the effective filing date of the invention was made to implement Spica’s teachings into the computer system of Lloyd to test devices because it would have reduced potential redundant efforts made in developing test coverage via firmware implementation with system constraints (see Spica’s [0013]).
As to claim 17, Spica further discloses the interface (116) is a serial interface (universal serial bus (USB) interface, see [0015]). It would have been obvious to one of the ordinary in the art before the effective filing date of the invention was made to implement Spica’s teachings into the computer system of Lloyd to test devices because it would have reduced potential redundant efforts made in developing test coverage via firmware implementation with system constraints (see Spica’s [0013]).
Claim 18 rejected for the same reasons set forth in claim 5.
As to claim 19, Lloyd discloses least one circuit arrangement , wherein the circuit arrangement (110) comprises at least one electronic device and at least one interface, wherein the test system is further configured for reading out a predetermined unique identifier (UID) of the electronic device, wherein the test system is further configured for determining at least one property of the electronic device (providing a look-up mechanism to translate the name or GUID into the appropriate network address, see [0024] to [0025]).
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lloyd as in above and in view of Spero, US Pub. No.20160195856.
As to claim 20, Lloyd does not specifically the method is performed in an automotive application. However, in a similar network environment, Spiro discloses the method is performed in an automotive application (automotive application, see [0170]). It would have been obvious to one of the ordinary in the art before the effective filing date of the invention was made to implement Spero’s teachings into the computer system of Lloyd to process data information because it would have provided different individuals with a localized environment of energy and mass flows to maintain them in thermal comfort (see Spero’s [0176]).
Conclusion
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/KHANH Q DINH/Primary Examiner, Art Unit 2458