DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to claims filed on 09/17/2024.
Claims 1-20 are pending.
Drawings
Figure 2 is objected to because of the following informalities: The labels “Network circuity 207” and “Network circuity 217” should read “Network circuitry 207” and “Network circuitry 217”. Appropriate correction is required.
Figures 1-2, 6-8, and 13 are objected to because they fail to comply with 37 CFR 1.84(p)(1) and 37 CFR 1.84(p)(3). 37 CFR 1.84(p)(1) requires that reference characters (numerals are preferred), sheet numbers, and view numbers must be plain and legible, and must not be used in association with brackets or inverted commas, or enclosed within outlines, e.g., encircled. They must be oriented in the same direction as the view so as to avoid having to rotate the sheet. Reference characters should be arranged to follow the profile of the object depicted. 37 CFR 1.84(p)(3) requires that numbers, letters, and reference characters must measure at least .32 cm. (1/8 inch) in height. They should not be placed in the drawing so as to interfere with its comprehension. Therefore, they should not cross or mingle with the lines. They should not be placed upon hatched or shaded surfaces. When necessary, such as indicating a surface or cross section, a reference character may be underlined and a blank space may be left in the hatching or shading where the character occurs so that it appears distinct. In the instant application, in Fig. 1-2, 6-8, and 13, labels of CPU 111, Memory 112, NIU 113, CPU 115, Cached 156, NIU 157, Cache 251, CPU 211, Cache 261, Network circuity 217, CPU 651, L1 653, CPU 652, L1 654, Memory Controller 660, Resource 1, 10%, Resource 2, Memory 90%, and L3 Cache are written over hatching; Examiner notes that there is no need that this text is depicted within the hatched area but insofar as Applicant believes it must be placed within the hatching, it must appear underlined and with blank space behind in the hatching.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. “Drawing and specification corrections, presentation of a new oath and the like are generally considered as formal matters, although the filing of drawing corrections in reply to an objection to the drawings cannot normally be held in abeyance … An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive” (MPEP § 714.02). The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 2, and 5-18 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1: Claims 1, 2, and 5-9 are directed to a method and fall within the statutory category of process. Claims 10-18 are directed to a network and fall within the statutory category of machine. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claims 1 and 10: The limitation of claim 1 of “a method for executing a complex computation using a network of computational nodes comprising: assigning a component computation of the complex computation to a first computational node in the network of computational nodes,”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally assign a component computation of a complex computation to a first computational node in a network of computational nodes. This may also be done with pencil and paper. Further, the limitations of “and wherein the local memory is reserved to be used for a cache by the first computational node for executing the component computation;”, “and reserving a remote memory on a second computational node in the network of computational nodes to be used for the cache by the first computational node for executing the component computation”, “a memory on the first computational node reserved to be used as a cache by the first computational node for executing a component computation from the complex computation;”, and “and a memory on the second computational node reserved to be used for the cache by the first computational node for executing the component computation”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally reserve a memory to be used for a cache by a first computational node by using mental assignment. This may also be done with pencil and paper.
Therefore, Yes, claims 1 and 10 recite a judicial exception.
Step 2A Prong 2:
Claims 1 and 10: The judicial exception is not integrated into a practical application. In particular, the Claims recite the following additional elements – “wherein the first computational node includes a local memory,”, “a network of computational nodes comprising: a set of instructions for a complex computation distributed amongst the computational nodes in the network of computational nodes;”, “a first computational node;”, and “a second computational node;”, which are merely recitations of generic computing components and technological environment/field of use (see MPEP § 2106.05(f) and 2106.05(h)) which does not integrate a judicial exception into practical application.
Step 2B:
Claims 1 and 10: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components and field of use/technological environment which do not amount to significantly more than the abstract idea.
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, Claims 1 and 10 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 2 and 11, the claims recite additional element recitations of “wherein: the first computational node and the second computational node are executing different component computations of the complex computation”, “wherein: the first computational node executes a first component of the complex computation;” and “and the second computational node executes a second component of the complex computation, the second component being different than the first component”, which are merely recitations of generic computing components and functions (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, claims 2 and 11 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 2 and 11 also fail both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 2 and 11 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 5 and 14, the claims recite additional element recitations of “the second computational node using a shared remote memory as a cache for the second computational node in place of a portion of the remote memory being used by the first computational node” and “the second computational node uses a shared remote memory as a cache for the second computational node in place of a portion of the memory on the second computational node being used by the first computational node”, which are merely recitations of technological environment/field of use (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Further, claims 5 and 14 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 5 and 14 also fail both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 5 and 14 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 6 and 15, the claims recite additional abstract idea recitations of “and reserving the remote memory on the second computational node in the network of computational nodes includes the second computational node partitioning at least a portion of the second L2 layer cache for use by the first computational node while saving the second L1 layer cache for exclusive use by the second computational node” and “wherein the memory on the second computational node in the network of computational nodes is reserved based at least in part on the second computational node repartitioning at least a portion of the second L2 layer cache for use by the first computational node while saving the second L1 layer cache for exclusive use by the second computational node”, as drafted, is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally partition or repartition at least a portion of an L2 layer cache for use by a computational node by mentally assigning at least a portion of the L2 layer cache to the computational node. Further, a person can mentally save a L1 layer cache for exclusive use by a computational node by not mentally assigning any other node to the L1 layer cache. This may also be done with pencil and paper. Further, the claims recite additional element recitations of “wherein: the first computational node has a first L1 layer cache and a first L2 layer cache; the second computational node has a second L1 layer cache and a second L2 layer cache;” and “a first L1 layer cache associated with the first computational node; a first L2 layer cache associated with the first computational node; a second L1 layer cache associated with the second computational node; and a second L2 layer cache associated with the second computational node;”, which are merely recitations of generic computing components (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, claims 6 and 15 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 6 and 15 also fail both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 6 and 15 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 7 and 16, the claims recite additional abstract idea recitations of “reserving the remote memory on the second computational node in the network of computational nodes is done at boot time” and “the memory on the second computational node in the network of computational nodes is reserved at boot time”, as drafted, is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe boot time of a computer and, based on this observation, can mentally reserve a memory to be used for a cache by a first computational node by using mental assignment. This may also be done with pencil and paper. Further, claims 7 and 16 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 7 and 16 also fail both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 7 and 16 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 8 and 17, the claims recite additional abstract idea recitations of “and the local memory is partitioned…” and “and the memory on the first computational node is partitioned…”, as drafted, is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally partition a memory through mental assignment. This may also be done with pencil and paper. Further, the claims recite additional element recitations of “the local memory is either a scratch pad memory or a first L1 layer cache of the first computational node;” and “the memory on the first computational node is either a scratch pad memory or a first L1 layer cache of the first computational node;”, which are merely recitations of technological environment/field of use (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Further, the claims recite additional element recitations of “and the local memory is partitioned programmatically” and “and the memory on the first computational node is partitioned programmatically”, which are merely recitations of generically using a computer as a tool to implement the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, claims 8 and 17 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 8 and 17 also fail both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 8 and 17 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 9 and 18, claim 9 recites additional abstract idea recitations of “reserving a second remote memory on a third computational node in the network of computational nodes to be used for the cache by the first computational node for executing the component computation”, as drafted, is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally reserve a second remote memory on a third computational node to be used for a cache by a first computational node by using mental assignment. Further, a person can mentally save a L1 layer cache for exclusive use by a computational node by not mentally assigning any other node to the L1 layer cache. This may also be done with pencil and paper. Further, claim 18 recites additional element recitations of “a third computational node;” and “and a second remote memory on the third computational node to be used for the cache by the first computational node for executing the component computation”, which are merely recitations of generic computing components (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, claims 9 and 18 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 9 and 18 also fail both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 9 and 18 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 12, the claim recites additional element recitations of “wherein: the second computational node is in an idle state;”, “a CPU of the second computational node is off while the second computational node is in the idle state;”, and “and the memory on the second computational node and network layer circuitry of the second computational node are on while the second computational node is in the idle state”, which are merely recitations of technological environment/field of use (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Further, claim 12 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 12 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 12 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 13, the claim recites additional element recitations of “further comprising: a network interface unit (NIU) associated with the network layer circuitry;”, and “and a router associated with the network layer circuitry”, which are merely recitations of generic computing components (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, claim 13 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 13 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 13 does not recite patent eligible subject matter under 35 U.S.C. § 101.
Therefore, Claims 1, 2, and 5-18 do not recite patent eligible subject matter under U.S.C. §101.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 10, 15, and 18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Szapiro et al. US 2024/0394186 A1 (hereafter Szapiro).
With regard to claim 10, Szapiro teaches:
A network of computational nodes comprising: a set of instructions for a complex computation distributed amongst the computational nodes in the network of computational nodes; “Other embodiments include, without limitation, a system that implements one or more aspects of the disclosed techniques, and one or more computer readable media including instructions for performing one or more aspects of the disclosed techniques” [Szapiro ¶ 8]. “A computing system generally includes, among other things, one or more processing units, such as central processing units (CPUs) and/or graphics processing units (GPUs), network adapters, and one or more memory systems. Processing units execute user mode software applications, which submit and launch compute tasks, executing on one or more compute engines included in the processing units” [Szapiro ¶ 2]. “As shown, the network topology of FIG. 3 is a 2D mesh network 300. The cores 210 and system level cache memories (SLCs) 220 communicate over the network 300 via switches 310. Together, the switches 310 constitute the switching fabric of the 2D mesh network 300 through which data flows between active cores 210, inactive cores 210 with repurposed level 2 cache memories 212(1), system level cache memories 220, and system memory 104 (not shown in FIG. 3)” [Szapiro ¶ 34].
a first computational node; “As shown, the system on chip 200 includes, without limitation, one or more active cores (first computational node), such as active core 210(0), one or more inactive cores, such as inactive core 210(1), one or more system level cache memories, such as system level cache memory 220, and a system level cache controller 230, all connected via a network-on-chip 240” [Szapiro ¶ 28].
a memory on the first computational node reserved to be used as a cache by the first computational node for executing a component computation from the complex computation; “Processing units typically access data via a hierarchical memory system, including one or more relatively small, high performance cache memory systems and a relatively large, low performance main memory system. In one example, each processing unit may have a small, high-performance level 1 cache memory that stores the data that is most likely to be requested by the processing unit in the immediate future. Each processing unit may further have a somewhat larger, somewhat lower performance level 2 cache memory that stores the data that is likely to be requested by the processing unit in the near future, but not as immediately as the data in the level 1 cache memory” [Szapiro ¶ 3].
a second computational node; “In order to increase performance of such a hierarchical memory system, the memory controller can recycle or repurpose the level 2 cache memory associated with a processing unit (second computational node) that is not currently using the local level 2 cache memory. This situation can occur when a processing unit fails or when a processing unit is in an inactive, low-power state because the processing unit is not currently executing any application programs” [Szapiro ¶ 4].
and a memory on the second computational node reserved to be used for the cache by the first computational node for executing the component computation. “When an active core
210 issues a memory operation, and there is a cache miss in the level 2 cache memory 212 of that active core 210, one of the system level cache memories 220 (and the associated system level cache controller 230) in the 2D mesh network 300 can service the memory operation … The system level cache controller 230 retrieves the data from the system level cache memory 220 or from one of the repurposed level 2 cache memories 212, depending on where the data resides … The system level cache controller 230 preferentially stores the data in a cache line of a repurposed level 2 cache memory 212 in an inactive core 210 that is on the path between the requesting active core 210 and the system level cache memory 220 that services the memory operation … When the requesting active core 210, or other active core 210, subsequently requests data in that cache line, the system level cache controller 230 accesses and updates the repurposed level 2 cache memory 212 as needed. The requesting active core 210 and/or other active cores 210 access the data in the repurposed level 2 cache memory 212” [Szapiro ¶ 37-38].
With regard to claim 15, Szapiro teaches the network of claim 10, as referenced above. Szapiro further teaches:
further comprising: a first L1 layer cache associated with the first computational node; a first L2 layer cache associated with the first computational node; a second L1 layer cache associated with the second computational node; and a second L2 layer cache associated with the second computational node; “Processing units typically access data via a hierarchical memory system, including one or more relatively small, high performance cache memory systems and a relatively large, low performance main memory system. In one example, each processing unit may have a small, high-performance level 1 cache memory that stores the data that is most likely to be requested by the processing unit in the immediate future. Each processing unit may further have a somewhat larger, somewhat lower performance level 2 cache memory that stores the data that is likely to be requested by the processing unit in the near future, but not as immediately as the data in the level 1 cache memory” [Szapiro ¶ 3].
wherein the memory on the second computational node in the network of computational nodes is reserved based at least in part on the second computational node repartitioning at least a portion of the second L2 layer cache for use by the first computational node “When an active core 210 issues a memory operation, and there is a cache miss in the level 2 cache memory 212 of that active core 210, one of the system level cache memories 220 (and the associated system level cache controller 230) in the 2D mesh network 300 can service the memory operation … The system level cache controller 230 retrieves the data from the system level cache memory 220 or from one of the repurposed level 2 cache memories 212, depending on where the data resides … The system level cache controller 230 preferentially stores the data in a cache line of a repurposed level 2 cache memory 212 in an inactive core 210 that is on the path between the requesting active core 210 and the system level cache memory 220 that services the memory operation … When the requesting active core 210, or other active core 210, subsequently requests data in that cache line, the system level cache controller 230 accesses and updates the repurposed level 2 cache memory 212 as needed. The requesting active core 210 and/or other active cores 210 access the data in the repurposed level 2 cache memory 212” [Szapiro ¶ 37-38].
while saving the second L1 layer cache for exclusive use by the second computational node. “In one example, each processing unit may have a small, high-performance level 1 cache memory that stores the data that is most likely to be requested by the processing unit in the immediate future. Each processing unit may further have a somewhat larger, somewhat lower performance level 2 cache memory that stores the data that is likely to be requested by the processing unit in the near future, but not as immediately as the data in the level 1 cache memory. The system may include a system level cache memory that services multiple processing units” [Szapiro ¶ 3].
With regard to claim 18, Szapiro teaches the network of claim 10, as referenced above. Szapiro further teaches:
further comprising: a third computational node; “As shown, the system on chip 200 includes, without limitation, one or more active cores, such as active core 210(0), one or more inactive cores, such as inactive core 210(1), one or more system level cache memories, such as system level cache memory 220, and a system level cache controller 230, all connected via a network-on-chip 240” [Szapiro ¶ 28]. “A second portion of the cores are inactive cores 210 with repurposed level 2 cache memories 212. In some examples, inactive cores 210 that include a repurposed level 2 cache memory 212 are distributed randomly in the 2D mesh network 300. As a result, some regions of the 2D mesh network 300 can have a relatively high concentration of repurposed level 2 cache memories 212, while other regions of the 2D mesh network 300 can have a moderate concentration or relatively low concentration of repurposed level 2 cache memories 212” [Szapiro ¶ 36].
and a second remote memory on the third computational node to be used for the cache by the first computational node for executing the component computation. “A second portion of the cores are inactive cores 210 with repurposed level 2 cache memories 212. In some examples, inactive cores 210 that include a repurposed level 2 cache memory 212 are distributed randomly in the 2D mesh network 300. As a result, some regions of the 2D mesh network 300 can have a relatively high concentration of repurposed level 2 cache memories 212, while other regions of the 2D mesh network 300 can have a moderate concentration or relatively low concentration of repurposed level 2 cache memories 212” [Szapiro ¶ 36]. “In general, the system level cache controller 230 can select any repurposed level 2 cache memory 212 corresponding to any inactive core 210 to store data for a particular memory requestion operation” [Szapiro ¶ 42]. “In some examples, the total possible number of repurposed level 2 cache memories 212 available at a given switch 310 is two” [Szapiro ¶ 49].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6, 9, 11, 12, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Szapiro et al. US 2024/0394186 A1 (hereafter Szapiro) in view of Bieswanger et al. US 2010/0037038 A1 (hereafter Bieswanger).
With regard to claim 1, Szapiro teaches:
A method for executing a complex computation using a network of computational nodes comprising: “A computing system generally includes, among other things, one or more processing units, such as central processing units (CPUs) and/or graphics processing units (GPUs), network adapters, and one or more memory systems. Processing units execute user mode software applications, which submit and launch compute tasks, executing on one or more compute engines included in the processing units” [Szapiro ¶ 2]. “As shown, the network topology of FIG. 3 is a 2D mesh network 300. The cores 210 and system level cache memories (SLCs) 220 communicate over the network 300 via switches 310. Together, the switches 310 constitute the switching fabric of the 2D mesh network 300 through which data flows between active cores 210, inactive cores 210 with repurposed level 2 cache memories 212(1), system level cache memories 220, and system memory 104 (not shown in FIG. 3)” [Szapiro ¶ 34].
wherein the first computational node includes a local memory, and wherein the local memory is reserved to be used for a cache by the first computational node for executing the component computation; “Processing units typically access data via a hierarchical memory system, including one or more relatively small, high performance cache memory systems and a relatively large, low performance main memory system. In one example, each processing unit may have a small, high-performance level 1 cache memory that stores the data that is most likely to be requested by the processing unit in the immediate future. Each processing unit may further have a somewhat larger, somewhat lower performance level 2 cache memory that stores the data that is likely to be requested by the processing unit in the near future, but not as immediately as the data in the level 1 cache memory” [Szapiro ¶ 3].
and reserving a remote memory on a second computational node in the network of computational nodes to be used for the cache by the first computational node for executing the component computation. “When an active core 210 issues a memory operation, and there is a cache miss in the level 2 cache memory 212 of that active core 210, one of the system level cache memories 220 (and the associated system level cache controller 230) in the 2D mesh network 300 can service the memory operation … The system level cache controller 230 retrieves the data from the system level cache memory 220 or from one of the repurposed level 2 cache memories 212 (remote memory), depending on where the data resides … The system level cache controller 230 preferentially stores the data in a cache line of a repurposed level 2 cache memory 212 in an inactive core 210 that is on the path between the requesting active core 210 and the system level cache memory 220 that services the memory operation … When the requesting active core 210, or other active core 210, subsequently requests data in that cache line, the system level cache controller 230 accesses and updates the repurposed level 2 cache memory 212 as needed. The requesting active core 210 and/or other active cores 210 access the data in the repurposed level 2 cache memory 212” [Szapiro ¶ 37-38].
Szapiro fails to explicitly teach assigning a component computation of the complex computation to a first computational node in the network of computational nodes.
However, Bieswanger teaches assigning a component computation of the complex computation to a first computational node in the network of computational nodes, “As the load on system 100 rises, virtual machine manager 114 may switch cores that were switched to the low power state back to higher power states and begin assigning work to the activated cores, spreading the load across a larger number of processing elements” [Bieswanger ¶ 41].
Bieswanger is considered to be analogous to the claimed invention because it is in the same field of partitioning or combining of resources. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Szapiro to incorporate the teachings of Bieswanger and include assigning a component computation of the complex computation to a first computational node in the network of computational nodes. Doing so would allow for computational nodes to be activated when needed for processing. “However, virtual machine manager 114 may activate the cores one at a time when needed without forcing system 100 to restart” [Bieswanger ¶ 41].
With regard to claim 2, Szapiro in view of Bieswanger teaches the method of claim 1, as referenced above. Szapiro fails to explicitly teach wherein: the first computational node and the second computational node are executing different component computations of the complex computation.
However, Bieswanger teaches wherein: the first computational node and the second computational node are executing different component computations of the complex computation. “In an embodiment, virtual processors may comprise whole numbers of concurrent operations which an operating system can utilize. The processing power may be conceptualized as being spread equally across these virtual processors” [Bieswanger ¶ 44]. “For example, core 241 may be able to execute instructions via some number "n" of hardware threads, with 0 to n hardware threads being concurrently active based on the operation of core 241. Contrasted with core 241, cores 243, 246, and 247 are less heavily loaded” [Bieswanger ¶ 46]. “In some embodiments, an operating system image may have a performance requirement that implies that when the operating system image executes, the operating system must execute on a minimum number of distinct hardware threads” [Bieswanger ¶ 55].
With regard to claim 3, Szapiro in view of Bieswanger teaches the method of claim 1, as referenced above. Szapiro further teaches:
further comprising: putting the second computational node into an idle state; “In order to increase performance of such a hierarchical memory system, the memory controller can recycle or repurpose the level 2 cache memory associated with a processing unit that is not currently using the local level 2 cache memory. This situation can occur when a processing unit fails or when a processing unit is in an inactive, low-power state because the processing unit is not currently executing any application programs” [Szapiro ¶ 4]. “For example, if a core 210 transitions from active to inactive, the active level 2 cache memory 212 for that core 210 becomes available as a repurposed level 2 cache memory 212” [Szapiro ¶ 40].
and the remote memory and network layer circuitry of the second computational node are on in the idle state. “Although inactive core 210(1) is rendered inoperable and/or in a low-power state, repurposed level 2 cache memory 212(1) can be powered up and operable” [Szapiro ¶ 31]. “As shown, the network topology of FIG. 3 is a 2D mesh network 300. The cores 210 and system level cache memories (SLCs) 220 communicate over the network 300 via switches 310. Together, the switches 310 constitute the switching fabric of the 2D mesh network 300 through which data flows between active cores 210, inactive cores 210 with repurposed level 2 cache memories 212(1), system level cache memories 220, and system memory 104 (not shown in FIG. 3)” [Szapiro ¶ 34].
Szapiro fails to explicitly teach wherein a CPU of the second computational node is off in the idle state.
However, Bieswanger teaches wherein a CPU of the second computational node is off in the idle state “For example, cores of system 100 that are inactive may not require the amount of power provided for an idle power state. System 100 may comprise an advanced system, capable of switching the inactive cores into very low-power states or turning the inactive cores off entirely” [Bieswanger ¶ 39].
With regard to claim 6, Szapiro in view of Bieswanger teaches the method of claim 1, as referenced above. Szapiro further teaches:
wherein: the first computational node has a first L1 layer cache and a first L2 layer cache; the second computational node has a second L1 layer cache and a second L2 layer cache; “Processing units typically access data via a hierarchical memory system, including one or more relatively small, high performance cache memory systems and a relatively large, low performance main memory system. In one example, each processing unit may have a small, high-performance level 1 cache memory that stores the data that is most likely to be requested by the processing unit in the immediate future. Each processing unit may further have a somewhat larger, somewhat lower performance level 2 cache memory that stores the data that is likely to be requested by the processing unit in the near future, but not as immediately as the data in the level 1 cache memory” [Szapiro ¶ 3].
and reserving the remote memory on the second computational node in the network of computational nodes includes the second computational node partitioning at least a portion of the second L2 layer cache for use by the first computational node “When an active core 210 issues a memory operation, and there is a cache miss in the level 2 cache memory 212 of that active core 210, one of the system level cache memories 220 (and the associated system level cache controller 230) in the 2D mesh network 300 can service the memory operation … The system level cache controller 230 retrieves the data from the system level cache memory 220 or from one of the repurposed level 2 cache memories 212, depending on where the data resides … The system level cache controller 230 preferentially stores the data in a cache line of a repurposed level 2 cache memory 212 in an inactive core 210 that is on the path between the requesting active core 210 and the system level cache memory 220 that services the memory operation … When the requesting active core 210, or other active core 210, subsequently requests data in that cache line, the system level cache controller 230 accesses and updates the repurposed level 2 cache memory 212 as needed. The requesting active core 210 and/or other active cores 210 access the data in the repurposed level 2 cache memory 212” [Szapiro ¶ 37-38].
while saving the second L1 layer cache for exclusive use by the second computational node. “In one example, each processing unit may have a small, high-performance level 1 cache memory that stores the data that is most likely to be requested by the processing unit in the immediate future. Each processing unit may further have a somewhat larger, somewhat lower performance level 2 cache memory that stores the data that is likely to be requested by the processing unit in the near future, but not as immediately as the data in the level 1 cache memory. The system may include a system level cache memory that services multiple processing units” [Szapiro ¶ 3].
With regard to claim 9, Szapiro in view of Bieswanger teaches the method of claim 1, as referenced above. Szapiro further teaches further comprising: reserving a second remote memory on a third computational node in the network of computational nodes to be used for the cache by the first computational node for executing the component computation. “As shown, the system on chip 200 includes, without limitation, one or more active cores, such as active core 210(0), one or more inactive cores, such as inactive core 210(1), one or more system level cache memories, such as system level cache memory 220, and a system level cache controller 230, all connected via a network-on-chip 240” [Szapiro ¶ 28]. “A second portion of the cores are inactive cores 210 with repurposed level 2 cache memories 212. In some examples, inactive cores 210 that include a repurposed level 2 cache memory 212 are distributed randomly in the 2D mesh network 300. As a result, some regions of the 2D mesh network 300 can have a relatively high concentration of repurposed level 2 cache memories 212, while other regions of the 2D mesh network 300 can have a moderate concentration or relatively low concentration of repurposed level 2 cache memories 212” [Szapiro ¶ 36]. “In general, the system level cache controller 230 can select any repurposed level 2 cache memory 212 corresponding to any inactive core 210 to store data for a particular memory requestion operation” [Szapiro ¶ 42]. “In some examples, the total possible number of repurposed level 2 cache memories 212 available at a given switch 310 is two” [Szapiro ¶ 49].
With regard to claim 11, Szapiro teaches the network of claim 10, as referenced above. Szapiro fails to explicitly teach wherein: the first computational node executes a first component of the complex computation; and the second computational node executes a second component of the complex computation, the second component being different than the first component.
However, Bieswanger teaches wherein: the first computational node executes a first component of the complex computation; and the second computational node executes a second component of the complex computation, the second component being different than the first component. “In an embodiment, virtual processors may comprise whole numbers of concurrent operations which an operating system can utilize. The processing power may be conceptualized as being spread equally across these virtual processors” [Bieswanger ¶ 44]. “For example, core 241 may be able to execute instructions via some number "n" of hardware threads, with 0 to n hardware threads being concurrently active based on the operation of core 241. Contrasted with core 241, cores 243, 246, and 247 are less heavily loaded” [Bieswanger ¶ 46]. “In some embodiments, an operating system image may have a performance requirement that implies that when the operating system image executes, the operating system must execute on a minimum number of distinct hardware threads” [Bieswanger ¶ 55].
Bieswanger is considered to be analogous to the claimed invention because it is in the same field of partitioning or combining of resources. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Szapiro to incorporate the teachings of Bieswanger and include the first computational node executes a first component of the complex computation; and the second computational node executes a second component of the complex computation, the second component being different than the first component. Doing so would allow for computational nodes to be activated when needed for processing concurrent operations. “However, virtual machine manager 114 may activate the cores one at a time when needed without forcing system 100 to restart” [Bieswanger ¶ 41].
With regard to claim 12, Szapiro teaches the network of claim 10, as referenced above. Szapiro further teaches:
wherein: the second computational node is in an idle state; “In order to increase performance of such a hierarchical memory system, the memory controller can recycle or repurpose the level 2 cache memory associated with a processing unit that is not currently using the local level 2 cache memory. This situation can occur when a processing unit fails or when a processing unit is in an inactive, low-power state because the processing unit is not currently executing any application programs” [Szapiro ¶ 4]. “For example, if a core 210 transitions from active to inactive, the active level 2 cache memory 212 for that core 210 becomes available as a repurposed level 2 cache memory 212” [Szapiro ¶ 40].
and the memory on the second computational node and network layer circuitry of the second computational node are on while the second computational node is in the idle state. “Although inactive core 210(1) is rendered inoperable and/or in a low-power state, repurposed level 2 cache memory 212(1) can be powered up and operable” [Szapiro ¶ 31]. “As shown, the network topology of FIG. 3 is a 2D mesh network 300. The cores 210 and system level cache memories (SLCs) 220 communicate over the network 300 via switches 310. Together, the switches 310 constitute the switching fabric of the 2D mesh network 300 through which data flows between active cores 210, inactive cores 210 with repurposed level 2 cache memories 212(1), system level cache memories 220, and system memory 104 (not shown in FIG. 3)” [Szapiro ¶ 34].
Szapiro fails to explicitly teach a CPU of the second computational node is off while the second computational node is in the idle state.
However, Bieswanger teaches a CPU of the second computational node is off while the second computational node is in the idle state; “For example, cores of system 100 that are inactive may not require the amount of power provided for an idle power state. System 100 may comprise an advanced system, capable of switching the inactive cores into very low-power states or turning the inactive cores off entirely” [Bieswanger ¶ 39].
It would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Szapiro to incorporate the teachings of Bieswanger and include a CPU of the second computational node is off while the second computational node is in the idle state. Doing so would allow for power savings. “Even so, such lower power states may offer significantly more power savings than the higher power states” [Bieswanger ¶ 52].
With regard to claim 19, Szapiro teaches:
A method for operating a network of computational nodes comprising: “A computing system generally includes, among other things, one or more processing units, such as central processing units (CPUs) and/or graphics processing units (GPUs), network adapters, and one or more memory systems. Processing units execute user mode software applications, which submit and launch compute tasks, executing on one or more compute engines included in the processing units” [Szapiro ¶ 2]. “As shown, the network topology of FIG. 3 is a 2D mesh network 300. The cores 210 and system level cache memories (SLCs) 220 communicate over the network 300 via switches 310. Together, the switches 310 constitute the switching fabric of the 2D mesh network 300 through which data flows between active cores 210, inactive cores 210 with repurposed level 2 cache memories 212(1), system level cache memories 220, and system memory 104 (not shown in FIG. 3)” [Szapiro ¶ 34].
putting a first computational node into an idle state, in response to sensing the decrease in demand, “In order to increase performance of such a hierarchical memory system, the memory controller can recycle or repurpose the level 2 cache memory associated with a processing unit that is not currently using the local level 2 cache memory. This situation can occur when a processing unit fails or when a processing unit is in an inactive, low-power state because the processing unit is not currently executing any application programs” [Szapiro ¶ 4]. “Additionally or alternatively, inactive core 210(1) could be in a state where the processing unit is not currently accessing repurposed level 2 cache memory 212(1). Inactive core 210(1) can be in such a state because the processing unit is not executing any application programs, because the system on chip 200 is in a low-power state to reduce power consumption, because of a system policy or configuration, and/or the like. Although inactive core 210(1) is rendered inoperable and/or in a low-power state, repurposed level 2 cache memory 212(1) can be powered up and operable” [Szapiro ¶ 31].
and a first memory and network layer circuitry of the first computational node are on in the idle state; “Although inactive core 210(1) is rendered inoperable and/or in a low-power state, repurposed level 2 cache memory 212(1) can be powered up and operable” [Szapiro ¶ 31]. “As shown, the network topology of FIG. 3 is a 2D mesh network 300. The cores 210 and system level cache memories (SLCs) 220 communicate over the network 300 via switches 310. Together, the switches 310 constitute the switching fabric of the 2D mesh network 300 through which data flows between active cores 210, inactive cores 210 with repurposed level 2 cache memories 212(1), system level cache memories 220, and system memory 104 (not shown in FIG. 3)” [Szapiro ¶ 34].
and executing the component computation using the second computational node, “Processing units execute user mode software applications, which submit and launch compute tasks, executing on one or more compute engines included in the processing units” [Szapiro ¶ 2]. “As shown, the system on chip 200 includes, without limitation, one or more active cores (second computational node), such as active core 210(0), one or more inactive cores, such as inactive core 210(1), one or more system level cache memories, such as system level cache memory 220, and a system level cache controller 230, all connected via a network-on-chip 240” [Szapiro ¶ 28].
where the second computational node includes a second memory, “Processing units typically access data via a hierarchical memory system, including one or more relatively small, high performance cache memory systems and a relatively large, low performance main memory system. In one example, each processing unit may have a small, high-performance level 1 cache memory that stores the data that is most likely to be requested by the processing unit in the immediate future. Each processing unit may further have a somewhat larger, somewhat lower performance level 2 cache memory that stores the data that is likely to be requested by the processing unit in the near future, but not as immediately as the data in the level 1 cache memory” [Szapiro ¶ 3].
the second computational node uses a cache to execute the component computation, and the cache uses the first memory, the network layer circuitry, and the second memory. “When an active core 210 issues a memory operation, and there is a cache miss in the level 2 cache memory 212 (second memory) of that active core 210, one of the system level cache memories 220 (and the associated system level cache controller 230) in the 2D mesh network 300 can service the memory operation … The system level cache controller 230 retrieves the data from the system level cache memory 220 or from one of the repurposed level 2 cache memories 212 (first memory), depending on where the data resides … The system level cache controller 230 preferentially stores the data in a cache line of a repurposed level 2 cache memory 212 in an inactive core 210 that is on the path between the requesting active core 210 and the system level cache memory 220 that services the memory operation … When the requesting active core 210, or other active core 210, subsequently requests data in that cache line, the system level cache controller 230 accesses and updates the repurposed level 2 cache memory 212 as needed. The requesting active core 210 and/or other active cores 210 access the data in the repurposed level 2 cache memory 212” [Szapiro ¶ 37-38]. “As shown, the network topology of FIG. 3 is a 2D mesh network 300. The cores 210 and system level cache memories (SLCs) 220 communicate over the network 300 via switches 310. Together, the switches 310 constitute the switching fabric of the 2D mesh network 300 through which data flows between active cores 210, inactive cores 210 with repurposed level 2 cache memories 212(1), system level cache memories 220, and system memory 104 (not shown in FIG. 3)” [Szapiro ¶ 34].
Szapiro fails to explicitly teach sensing a decrease in demand for the network of computational nodes; where a CPU of the first computational node is off in the idle state … assigning a component computation of a complex computation to a second computational node in the network of computational nodes.
However, Bieswanger teaches:
sensing a decrease in demand for the network of computational nodes; “As the demand of the applications changes with time, system 100 may change the number of cores which are active and inactive based on the demand. For example, in an alternative embodiment processor 140 and processor 150 may each have four cores, for a total of eight cores. Under heavy demand, virtual machine manager 114 may pool the eight cores together, making them all active and operating at full power. However, as the demand decreases, virtual machine manager 114 may reduce the number of cores in the pool of active cores from eight to seven cores, or to three cores, as examples” [Bieswanger ¶ 26].
where a CPU of the first computational node is off in the idle state “For example, cores of system 100 that are inactive may not require the amount of power provided for an idle power state. System 100 may comprise an advanced system, capable of switching the inactive cores into very low-power states or turning the inactive cores off entirely” [Bieswanger ¶ 39].
assigning a component computation of a complex computation to a second computational node in the network of computational nodes; “As the load on system 100 rises, virtual machine manager 114 may switch cores that were switched to the low power state back to higher power states and begin assigning work to the activated cores, spreading the load across a larger number of processing elements” [Bieswanger ¶ 41].
Bieswanger is considered to be analogous to the claimed invention because it is in the same field of partitioning or combining of resources. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Szapiro to incorporate the teachings of Bieswanger and include sensing a decrease in demand for the network of computational nodes; where a CPU of the first computational node is off in the idle state … assigning a component computation of a complex computation to a second computational node in the network of computational nodes. Doing so would allow for computational nodes to be activated when needed for processing. “However, virtual machine manager 114 may activate the cores one at a time when needed without forcing system 100 to restart” [Bieswanger ¶ 41].
With regard to claim 20, Szapiro in view of Bieswanger teaches the method of claim 19, as referenced above. Szapiro further teaches wherein: the first memory comprises an L2 layer cache of the first computational node. “In order to increase performance of such a hierarchical memory system, the memory controller can recycle or repurpose the level 2 cache memory associated with a processing unit that is not currently using the local level 2 cache memory” [Szapiro ¶ 4].
Claim(s) 4 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Szapiro et al. US 2024/0394186 A1 (hereafter Szapiro) in view of Bieswanger et al. US 2010/0037038 A1 (hereafter Bieswanger) in view of Sebexen et al. US 2018/0109452 A1 (hereafter Sebexen).
With regard to claim 4, Szapiro in view of Bieswanger teaches the method of claim 3, as referenced above. Szapiro further teaches wherein: the network layer circuitry comprises a network interface unit (NIU), “Additionally, active core 210(0) includes other components, such as a memory bridge 105, an I/O bridge 107, a network adapter 118, a level 1 cache memory (not shown), a local memory controller (not shown), and/or the like” [Szapiro ¶ 29]. “Switch 116 is configured to provide connections between I/O bridge 107 and other components of the computing system 100, such as a network adapter 118 and various add-in cards 120 and 121. In some examples, network adapter 118 serves as the primary or exclusive input device to receive input data for processing via the disclosed techniques” [Szapiro ¶ 19].
Szapiro in view of Bieswanger fails to explicitly teach and a router.
However, Sebexen teaches and a router. “In general, in one aspect, embodiments relate to a network-on-chip microprocessor chip, including a set of scratchpad memory modules; and a set of tiles arranged in a grid configuration, each tile including a processor core and a router communicatively coupled with one another, where: each processor core corresponds to and is communicatively coupled with a different scratchpad memory module of the set of scratchpad memory modules, each router includes a set of input ports and a set of output ports, where each output port includes a FIFO memory element operable to store a data packet for subsequent sending to a router of an adjacent tile, based on a physical destination address of a data packet, each router is operable to send one or more data packets to routers of one or more adjacent tiles or the processor core corresponding to the router, and each router implements a static priority routing policy in the event of a traffic condition” [Sebexen ¶ 6].
Sebexen is considered to be analogous to the claimed invention because it is in the same field of grid computing. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Szapiro in view of Bieswanger to incorporate the teachings of Sebexen and include a router. Doing so would allow for the routing of data packets to and from each computational node. “In one or more embodiments, a router includes functionality to receive one or more packets (e.g., including a data payload and destination address information) and route the one or more packets for delivery to the destination” [Sebexen ¶ 29].
With regard to claim 13, Szapiro in view of Bieswanger teaches the network of claim 12, as referenced above. Szapiro further teaches further comprising: a network interface unit (NIU) associated with the network layer circuitry; “Additionally, active core 210(0) includes other components, such as a memory bridge 105, an I/O bridge 107, a network adapter 118, a level 1 cache memory (not shown), a local memory controller (not shown), and/or the like” [Szapiro ¶ 29]. “Switch 116 is configured to provide connections between I/O bridge 107 and other components of the computing system 100, such as a network adapter 118 and various add-in cards 120 and 121. In some examples, network adapter 118 serves as the primary or exclusive input device to receive input data for processing via the disclosed techniques” [Szapiro ¶ 19].
Szapiro in view of Bieswanger fails to explicitly teach and a router associated with the network layer circuitry.
However, Sebexen teaches and a router associated with the network layer circuitry. “In general, in one aspect, embodiments relate to a network-on-chip microprocessor chip, including a set of scratchpad memory modules; and a set of tiles arranged in a grid configuration, each tile including a processor core and a router communicatively coupled with one another, where: each processor core corresponds to and is communicatively coupled with a different scratchpad memory module of the set of scratchpad memory modules, each router includes a set of input ports and a set of output ports, where each output port includes a FIFO memory element operable to store a data packet for subsequent sending to a router of an adjacent tile, based on a physical destination address of a data packet, each router is operable to send one or more data packets to routers of one or more adjacent tiles or the processor core corresponding to the router, and each router implements a static priority routing policy in the event of a traffic condition” [Sebexen ¶ 6].
Sebexen is considered to be analogous to the claimed invention because it is in the same field of grid computing. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Szapiro in view of Bieswanger to incorporate the teachings of Sebexen and include and a router associated with the network layer circuitry. Doing so would allow for the routing of data packets to and from each computational node. “In one or more embodiments, a router includes functionality to receive one or more packets (e.g., including a data payload and destination address information) and route the one or more packets for delivery to the destination” [Sebexen ¶ 29].
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Szapiro et al. US 2024/0394186 A1 (hereafter Szapiro) in view of Bieswanger et al. US 2010/0037038 A1 (hereafter Bieswanger) in view of Sunwoo et al. US 2022/0035679 A1 (hereafter Sunwoo).
With regard to claim 5, Szapiro in view of Bieswanger teaches the method of claim 1, as referenced above. Szapiro further teaches wherein executing the component computation includes: the second computational node using a shared remote memory as a cache for the second computational node in place of a portion of the remote memory being used by the first computational node. “The system may include a system level cache memory that services multiple processing units. The system level cache memory is typically larger and lower performance than the level 2 cache memories. Finally, the system may include a main memory system that is larger and lower in performance than the system level cache memory” [Szapiro ¶ 3]. “If the requested data is not stored in repurposed level 2 cache memory 212(1), then system level cache controller 230 can retrieve the requested data from system memory 104” [Szapiro ¶ 33].
Szapiro in view of Bieswanger fails to explicitly teach the second computational node using a shared remote memory as a cache for the second computational node in place of a portion of the remote memory being used by the first computational node.
However, Sunwoo teaches the second computational node using a shared remote memory as a cache for the second computational node in place of a portion of the remote memory being used by the first computational node. “The method may comprise selecting a group of workloads to execute in parallel on respective processor cores of the processing system, based on at least one selection criterion which favours grouping together of workloads for which the performance monitoring data indicates that the workloads have differing performance or resource utilisation requirements” [Sunwoo ¶ 52].“For example a suitable hardware resource for such a combination of workloads could include a first processor core borrowing pipeline slots or execution units from a second core and the second core borrowing cache capacity from the first core so that a compute-bound workload on the first core and a memory-bound workload on the second core can operate more efficiently” [Sunwoo ¶ 57]. “When hardware resource allocation is reconfigured based on the control information generated at step 252, some operations may be performed to drain the reallocated hardware resource of information associated with the workload previously using that resource, or to wait for that resource to become idle, before reallocating the resource to another core for use in processing a different workload. For example, when borrowing a portion of cache storage, dirty data in the cache may be written back to memory, or when borrowing a pipeline unit or portion of a queue, the borrowed element may be drained of instructions/requests or be required to become idle before the borrowing proceeds and the element is made available for use by another core” [Sunwoo ¶ 156]. “For example, each core 4 may have one or more local caches 6. A shared cache 8 may be accessible to multiple processor cores 4 and each of the processor cores has access to shared memory 10” [Sunwoo ¶ 97].
Sunwoo is considered to be analogous to the claimed invention because it is in the same field of partitioning or combining of resources. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Szapiro in view of Bieswanger to incorporate the teachings of Sunwoo and include the second computational node using a shared remote memory as a cache for the second computational node in place of a portion of the remote memory being used by the first computational node. Doing so would allow for the second computational node to access memory while maintaining a suitable configuration for the workload. “For example if the machine learning model predicted that a configuration where the workload is executed using less cache resource is suitable for that workload then the workload could be identified as being more likely to be a compute-bound workload while if the model predicts than a resource configuration with less pipeline resource may be more suitable then it may be more likely that the workload is a memory-bound workload” [Sunwoo ¶ 160].
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Szapiro et al. US 2024/0394186 A1 (hereafter Szapiro) in view of Bieswanger et al. US 2010/0037038 A1 (hereafter Bieswanger) in view of Pudiyapura US 2024/0259330 A1 (hereafter Pudiyapura).
With regard to claim 7, Szapiro in view of Bieswanger teaches the method of claim 1, as referenced above. Szapiro further teaches reserving the remote memory on the second computational node in the network of computational nodes “The system level cache controller 230 preferentially stores the data in a cache line of a repurposed level 2 cache memory 212 in an inactive core 210 that is on the path between the requesting active core 210 and the system level cache memory 220 that services the memory operation … When the requesting active core 210, or other active core 210, subsequently requests data in that cache line, the system level cache controller 230 accesses and updates the repurposed level 2 cache memory 212 as needed. The requesting active core 210 and/or other active cores 210 access the data in the repurposed level 2 cache memory 212” [Szapiro ¶ 37-38].
Szapiro in view of Bieswanger fails to teach wherein: reserving the remote memory on the second computational node in the network of computational nodes is done at boot time.
However, Pudiyapura teaches wherein: reserving the remote memory on the second computational node in the network of computational nodes is done at boot time. “A pre-allocated block can be a block of memory that is allocated for or set aside for a specific purpose when the network device is initialized or booted” [Pudiyapura ¶ 127].
Pudiyapura is considered to be analogous to the claimed invention because it is in the same field of partitioning or combining of resources. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Szapiro in view of Bieswanger to incorporate the teachings of Pudiyapura and include that reserving the remote memory on the second computational node in the network of computational nodes is done at boot time. Doing so would allow for further efficiency through the pre-allocation of memory. “A pre-allocated block can be a block of memory that is allocated for or set aside for a specific purpose when the network device is initialized or booted” [Pudiyapura ¶ 127].
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Szapiro et al. US 2024/0394186 A1 (hereafter Szapiro) in view of Bieswanger et al. US 2010/0037038 A1 (hereafter Bieswanger) in view of Yudanov US 2022/0197814 A1 (hereafter Yudanov).
With regard to claim 8, Szapiro in view of Bieswanger teaches the method of claim 1, as referenced above. Szapiro further teaches wherein: the local memory is either a scratch pad memory or a first L1 layer cache of the first computational node; “Processing units typically access data via a hierarchical memory system, including one or more relatively small, high performance cache memory systems and a relatively large, low performance main memory system. In one example, each processing unit may have a small, high-performance level 1 cache memory that stores the data that is most likely to be requested by the processing unit in the immediate future” [Szapiro ¶ 3].
Szapiro in view of Bieswanger fails to explicitly teach and the local memory is partitioned programmatically.
However, Yudanov teaches and the local memory is partitioned programmatically. “In this embodiment, the method may programmatically determine how to allocate memory. For example, if the cache parameters indicate that caching is desired (e.g., a cache size, associativity type, etc. parameter is received), the method may allocate memory from an in-memory cache part (e.g., 702) of a memory device” [Yudanov ¶ 75].
Yudanov is considered to be analogous to the claimed invention because it is in the same field of partitioning or combining of resources. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Szapiro in view of Bieswanger to incorporate the teachings of Yudanov and include that the local memory is partitioned programmatically. Doing so would allow for the system to programmatically reserve memory based on commands. “As discussed above, an OS may issue commands to a memory device to reserve a region or share of memory for the local context of a process. The specific format of this command is not limiting. However, in the illustrated embodiment, the command includes one or more cache parameters (e.g., those discussed in FIG. 3). In one embodiment, the command also includes a size of memory requested” [Yudanov ¶ 73].
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Szapiro et al. US 2024/0394186 A1 (hereafter Szapiro) in view of Sunwoo et al. US 2022/0035679 A1 (hereafter Sunwoo).
With regard to claim 14, Szapiro teaches the network of claim 10, as referenced above. Szapiro further teaches wherein: the second computational node uses a shared remote memory as a cache for the second computational node in place of a portion of the memory on the second computational node being used by the first computational node. “The system may include a system level cache memory that services multiple processing units. The system level cache memory is typically larger and lower performance than the level 2 cache memories. Finally, the system may include a main memory system that is larger and lower in performance than the system level cache memory” [Szapiro ¶ 3]. “If the requested data is not stored in repurposed level 2 cache memory 212(1), then system level cache controller 230 can retrieve the requested data from system memory 104” [Szapiro ¶ 33].
Szapiro fails to explicitly teach the second computational node uses a shared remote memory as a cache for the second computational node in place of a portion of the memory on the second computational node being used by the first computational node.
However, Sunwoo teaches the second computational node uses a shared remote memory as a cache for the second computational node in place of a portion of the memory on the second computational node being used by the first computational node. “The method may comprise selecting a group of workloads to execute in parallel on respective processor cores of the processing system, based on at least one selection criterion which favours grouping together of workloads for which the performance monitoring data indicates that the workloads have differing performance or resource utilisation requirements” [Sunwoo ¶ 52].“For example a suitable hardware resource for such a combination of workloads could include a first processor core borrowing pipeline slots or execution units from a second core and the second core borrowing cache capacity from the first core so that a compute-bound workload on the first core and a memory-bound workload on the second core can operate more efficiently” [Sunwoo ¶ 57]. “When hardware resource allocation is reconfigured based on the control information generated at step 252, some operations may be performed to drain the reallocated hardware resource of information associated with the workload previously using that resource, or to wait for that resource to become idle, before reallocating the resource to another core for use in processing a different workload. For example, when borrowing a portion of cache storage, dirty data in the cache may be written back to memory, or when borrowing a pipeline unit or portion of a queue, the borrowed element may be drained of instructions/requests or be required to become idle before the borrowing proceeds and the element is made available for use by another core” [Sunwoo ¶ 156]. “For example, each core 4 may have one or more local caches 6. A shared cache 8 may be accessible to multiple processor cores 4 and each of the processor cores has access to shared memory 10” [Sunwoo ¶ 97].
Sunwoo is considered to be analogous to the claimed invention because it is in the same field of partitioning or combining of resources. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Szapiro to incorporate the teachings of Sunwoo and include the second computational node uses a shared remote memory as a cache for the second computational node in place of a portion of the memory on the second computational node being used by the first computational node. Doing so would allow for the second computational node to access memory while maintaining a suitable configuration for the workload. “For example if the machine learning model predicted that a configuration where the workload is executed using less cache resource is suitable for that workload then the workload could be identified as being more likely to be a compute-bound workload while if the model predicts than a resource configuration with less pipeline resource may be more suitable then it may be more likely that the workload is a memory-bound workload” [Sunwoo ¶ 160].
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Szapiro et al. US 2024/0394186 A1 (hereafter Szapiro) in view of Pudiyapura US 2024/0259330 A1 (hereafter Pudiyapura).
With regard to claim 16, Szapiro teaches the network of claim 10, as referenced above. Szapiro further teaches wherein: the memory on the second computational node in the network of computational nodes is reserved “The system level cache controller 230 preferentially stores the data in a cache line of a repurposed level 2 cache memory 212 in an inactive core 210 that is on the path between the requesting active core 210 and the system level cache memory 220 that services the memory operation … When the requesting active core 210, or other active core 210, subsequently requests data in that cache line, the system level cache controller 230 accesses and updates the repurposed level 2 cache memory 212 as needed. The requesting active core 210 and/or other active cores 210 access the data in the repurposed level 2 cache memory 212” [Szapiro ¶ 37-38].
Szapiro fails to teach wherein: the memory on the second computational node in the network of computational nodes is reserved at boot time.
However, Pudiyapura teaches wherein: the memory on the second computational node in the network of computational nodes is reserved at boot time. “A pre-allocated block can be a block of memory that is allocated for or set aside for a specific purpose when the network device is initialized or booted” [Pudiyapura ¶ 127].
Pudiyapura is considered to be analogous to the claimed invention because it is in the same field of partitioning or combining of resources. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Szapiro to incorporate the teachings of Pudiyapura and include that the memory on the second computational node in the network of computational nodes is reserved at boot time. Doing so would allow for further efficiency through the pre-allocation of memory. “A pre-allocated block can be a block of memory that is allocated for or set aside for a specific purpose when the network device is initialized or booted” [Pudiyapura ¶ 127].
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Szapiro et al. US 2024/0394186 A1 (hereafter Szapiro) in view of Yudanov US 2022/0197814 A1 (hereafter Yudanov).
With regard to claim 17, Szapiro teaches the network of claim 10, as referenced above. Szapiro further teaches wherein: the memory on the first computational node is either a scratch pad memory or a first L1 layer cache of the first computational node; “Processing units typically access data via a hierarchical memory system, including one or more relatively small, high performance cache memory systems and a relatively large, low performance main memory system. In one example, each processing unit may have a small, high-performance level 1 cache memory that stores the data that is most likely to be requested by the processing unit in the immediate future” [Szapiro ¶ 3].
Szapiro fails to explicitly teach and the memory on the first computational node is partitioned programmatically.
However, Yudanov teaches and the memory on the first computational node is partitioned programmatically. “In this embodiment, the method may programmatically determine how to allocate memory. For example, if the cache parameters indicate that caching is desired (e.g., a cache size, associativity type, etc. parameter is received), the method may allocate memory from an in-memory cache part (e.g., 702) of a memory device” [Yudanov ¶ 75].
Yudanov is considered to be analogous to the claimed invention because it is in the same field of partitioning or combining of resources. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Szapiro to incorporate the teachings of Yudanov and include that the memory on the first computational node is partitioned programmatically. Doing so would allow for the system to programmatically reserve memory based on commands. “As discussed above, an OS may issue commands to a memory device to reserve a region or share of memory for the local context of a process. The specific format of this command is not limiting. However, in the illustrated embodiment, the command includes one or more cache parameters (e.g., those discussed in FIG. 3). In one embodiment, the command also includes a size of memory requested” [Yudanov ¶ 73].
Conclusion
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/A.F.R./Examiner, Art Unit 2197
/BRADLEY A TEETS/ Supervisory Patent Examiner, Art Unit 2197
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