DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 09/17/2024 is in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7, and 10 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Walker et al. (U.S. Patent Application Publication No. US 2022/0121514 A1), hereinafter “Walker.”
With regards to Claim 1, Walker teaches:
a semiconductor device (Figs. 1A-1B and ¶ 0028-0029; regarding, e.g., chiplet system package 110.) configured
to include: a selection input terminal configured to receive a selection signal (Fig. 3; ¶ 0070; and ¶ 0076; regarding, e.g., part of secondary device controller 316 which includes chip select [CS] port.); a clock input terminal (Fig. 3 and ¶ 0076; regarding, e.g., clock [SCLK] port.); a data input terminal (Fig. 3 and ¶ 0076; regarding, e.g., controller output peripheral input [COPI / MOSI] port.); and a data output terminal (Fig. 3 and ¶ 0076; regarding, e.g., controller input peripheral output [CIPO / MISO] port.), and
to be capable of performing serial communication (¶ 0065-0069.), the semiconductor device comprising
a control circuit (Fig. 3; ¶ 0076; regarding, e.g., secondary device controller 316; and ¶ 0080; also regarding, e.g., register bus 340 and registers 326 coupled to the secondary device controller 316.) configured
to receive, as an input data signal, during a selection period in which the selection signal has a predetermined level, a signal applied to the data input terminal in synchronization with a clock signal applied to the clock input terminal (Fig. 3; ¶ 0078-0079; regarding, e.g., during when a chip select [CS] signal is active [e.g. low]; Figs. 4-5; ¶ 0089 including TABLE 1; and ¶ 0093 including TABLE 2.), and
to perform a corresponding operation corresponding to the input data signal during the selection period (Fig. 3; ¶ 0078-0079; regarding, e.g., during when a chip select [CS] signal is active [e.g. low]; Figs. 4-5; ¶ 0089 including TABLE 1; ¶ 0093 including TABLE 2; and ¶ 0095.) or after the selection period,
wherein the control circuit
holds an error flag indicating whether a specific error has occurred (Fig. 3; ¶ 0081; Figs. 4-5; ¶ 0093 including TABLE 2; ¶ 0099; regarding, e.g., secondary device status field 410; and ¶ 0103; regarding, e.g., secondary device status field 508.),
outputs, during a part of the selection period, a response signal corresponding to the input data signal from the data output terminal (Fig. 4; ¶ 0096-0099; Fig. 5; and ¶ 0101-0103.) and
outputs, during another part of the selection period, an error flag signal corresponding to a value of the error flag from the data output terminal (¶ 0093 including TABLE 2; regarding, e.g., one or more of a S[2:0] status field value for the secondary device status field [error flag signal]; Fig. 4; ¶ 0096-0099; Fig. 5; and ¶ 0101-0103.).
With regards to Claim 2, Walker teaches the device of Claim 1 as referenced above. Walker further teaches:
wherein the control circuit
outputs the error flag signal from the data output terminal in response to transition of a level of the selection signal from another level to the predetermined level (Fig. 3; ¶ 0078-0079; Fig. 4; ¶ 0096-0099; Fig. 5; and ¶ 0101-0103.), and
thereafter outputs the response signal from the data output terminal (Fig. 3; ¶ 0078-0079; Fig. 4; ¶ 0096-0099; Fig. 5; and ¶ 0101-0103.).
With regards to Claim 3, Walker teaches the device of Claim 2 as referenced above. Walker further teaches:
wherein the clock signal for a plurality of cycles is applied to the clock input terminal during the selection period (Fig. 4; ¶ 0096-0099; Fig. 5; and ¶ 0101-0103.), and
the control circuit
outputs, during the selection period, the error flag signal from the data output terminal in a first cycle for the clock signal (Figs. 4-5; ¶ 0093 including TABLE 2; Fig. 4; ¶ 0096-0099; Fig. 5; and ¶ 0101-0103. As interpreted by the Examiner, when the secondary status field is, e.g., a one-bit field or message, then it must propagate in only one clock cycle [a first cycle].), and
outputs the response signal from the data output terminal in second and subsequent cycles for the clock signal (Fig. 4; ¶ 0096-0099; Fig. 5; and ¶ 0101-0103.).
With regards to Claim 4, Walker teaches the device of Claim 1 as referenced above. Walker further teaches:
wherein the control circuit
outputs, during the selection period, the error flag signal from the data output terminal after completion of the output of the response signal from the data output terminal (Fig. 5 and ¶ 0101-0103.), or
outputs, during the selection period, the error flag signal after a part of the response signal is output from the data output terminal (Fig. 4 and ¶ 0096-0099.) and
thereafter outputs a remaining part of the response signal from the data output terminal (Fig. 4 and ¶ 0096-0099.).
With regards to Claim 5, Walker teaches the device of Claim 1 as referenced above. Walker further teaches:
wherein the control circuit includes a memory (Fig. 3 and ¶ 0082; regarding, e.g., a combination of cache register 304, cache bus 338, and NAND array 308.) and is capable of performing, as the corresponding operation, a write operation on the memory in response to the reception of the input data signal (Fig. 5; ¶ 0095; and ¶ 0101-0103.),
the input data signal when the write operation is performed includes
an address signal indicating a write target address in the memory (Fig. 5 and ¶ 0101-0103.) and
a write data signal indicating write data to be written to the write target address (Fig. 5 and ¶ 0101-0103.) and
the control circuit writes, during the write operation, the write data to the write target address in the memory (Fig. 5 and ¶ 0101-0103.).
With regards to Claim 7, Walker teaches the device of Claim 1 as referenced above. Walker further teaches:
wherein the control circuit includes a memory (Fig. 3 and ¶ 0082; regarding, e.g., a combination of cache register 304, cache bus 338, and NAND array 308.) and is capable of performing, as the corresponding operation, a read operation on the memory in response to the reception of the input data signal (Fig. 4 and ¶ 0095-0099.),
the input data signal when the read operation is performed includes an address signal indicating a read target address in the memory (Fig. 4 and ¶ 0096-0099.),
when the read operation is performed, the selection period includes an error flag output period (Fig. 4; regarding, e.g., where S2 is read until where either S0 or SP is read; and ¶ 0096-0099.) and a response signal output period (Fig. 4; regarding, e.g., where D63 is read until where either D0 or DP is read; and ¶ 0096-0099.) and
when the read operation is performed in response to the reception of the input data signal, the control circuit
outputs the error flag signal from the data output terminal during the error flag output period (Fig. 4 and ¶ 0096-0099.), and
outputs the response signal including a signal of storage data in the read target address from the data output terminal during the response signal output period (Fig. 4 and ¶ 0096-0099.).
With regards to Claim 10, Walker teaches the device of Claim 1 as referenced above. Walker further teaches:
wherein the control circuit includes an error detection circuit configured to detect whether a plurality of types of errors have occurred (Fig. 3; ¶ 0081; Figs. 4-5; and ¶ 0093 including TABLE 2.), and
one or more errors of the plurality of types of errors correspond to the specific error (Figs. 4-5 and ¶ 0093 including TABLE 2.).
Allowable Subject Matter
Claims 6, 8, and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Choi et al. (U.S. Patent No. US 9,389,953 B2); teaching that a chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to read information from a secondary device about whether the secondary device supports parity-protected data communications. The primary device can be configured to selectively send or receive parity-protected data communications depending on a capability of the secondary device to support parity.
Chang et al. (U.S. Patent No. US 9,852,811 B2); teaching a memory device configured to implement an error detection protocol. The memory device includes a memory array and a first input for receiving a control signal corresponding to a command cycle. The memory device also includes a second input for receiving an access control signal during a command cycle and for receiving an error detection signal during the command cycle, wherein the error detection signal includes information corresponding to the access control signal. The memory device further includes control logic configured to verify the correctness of the access control signal by a comparison with the error detection signal and perform an operation on the memory array during the command cycle when the correctness of the access control signal is verified.
Whately et al. (U.S. Patent Application Publication No. US 2021/0042189 A1); teaching, in response to receiving a read request at a memory controller, sending a read command and address values on a command address bus in synchronism with a clock. In response to the read command, receiving an uninterrupted burst of read data values on at least one parallel data bus, the burst of read data values having double date rate with respect to the clock, and receiving error correction code (ECC) values for the read data values in response to the same read command, the ECC values not being included in the burst of read data values being output on non-ECC input/outputs (I/Os); wherein the non-ECC I/Os are I/Os not assigned to ECC data according to a preexisting standards organization. Corresponding systems and devices are disclosed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH KUDIRKA whose telephone number is (571)270-7126. The examiner can normally be reached M-F 7:30am - 5pm ET.
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/JOSEPH R KUDIRKA/Primary Patent Examiner, Art Unit 2114