DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Figs. 3, 7-10 and 14 in the reply filed on 6/11/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ko et al (PGPUB 2015/0187304 A1)..
As to claim 1, Ko (Figs. 2-4) teaches, a display driving circuit (liquid crystal display device) operating in a video mode (normal mode), comprising:
an interface (interface 141) configured to receive, from an external source (external system, ¶ 49), sync signals (Hsync, Vsync, DE) and image data (image data RGB)) corresponding to each of a plurality of frames (frame, ¶ 53, 54)(¶ 39);
a data processor ( image processor 1423) configured to receive the image data (image data RGB) from the interface and convert the image data to generate a converted image data (converted image data aRGB)(¶ 51); and
a timing controller (timing controller 140) configured to generate internal control signals (gate control signals GCS and data control signals DCS) for driving a driver circuit (gate driver 110 and data driver 120) based on the sync signals and the converted image data (¶ 34, 36),
wherein the internal control signals are configured to be output based on the sync signals and signals corresponding to the image data being input simultaneously into the driver circuit (¶ 51: i.e. receives Hsync, Vsync, and DE to generate GCS and DCS and outputs aRGB), and
wherein panel driving signals (gate drive signal Vg and data signal Vdata) are configured to be output to a display panel (liquid crystal panel 100) based on the internal control signals being output to the driver circuit (¶ 30).
As to claim 2, Ko (Figs. 1-4) teaches, wherein the internal control signals are configured to be output to the driver circuit based on the signals corresponding to the image data being applied to the driver circuit (¶ 49: i.e. generates control signal for controlling each driver), and
wherein the signals corresponding to the image data include horizontal sync signals (¶ 51: i.e. Hsync).
As to claim 3, Ko (Figs. 1-4) teaches, wherein the sync signals comprise a first sync signal (Hsync) corresponding to a start signal of each of the plurality of frames and a second sync signal (Hsync) that is different from the first sync signal (¶ 51).
As to claim 4, Ko (Figs. 1-4) teaches, wherein at least one of a pulse width, a number of pulses, or a pulse pattern of the first sync signal is different from a corresponding one of a pulse width, a number of pulses, or a pulse pattern of the second sync signal (¶ 51: i.e. Hsync and Vsync must have different pulse width due to driving different length of periods).
Allowable Subject Matter
Claims 6-20 are allowed.
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Applicant’s claimed invention regards the display driving circuit that handles the display mode and control signals based on the status image data being transmitted. Examiner conducted a search to find the prior arts that would teach all of the limitations alone or in combination before the effective filing date of the claimed invention. However, none of the prior arts from the search teaches the following limitations for each claims.
Claim 5
“wherein the first sync signal is a start signal of a second section that is a next frame section of a first section, and wherein the first sync signal is configured to, based on the signals corresponding to the image data being not received in the first section, be delayed by a section in which the signals corresponding to the image data are not received”
Claim 6
“when part of the image data generated from the display processor is not transmitted normally to a display device, the host is configured to operate in at least one of a first mode that delays output of the first sync signals corresponding to a next frame section of a section where part of the image data is not normally received by the display device, or a second mode that outputs the first sync signals corresponding to the next frame section of the section where part of the image data is not normally received by the display device”
Claim 15
“wherein the display driving circuit is further configured to generate the control signals only when the sync signals and the image data are normally input, and to output panel driving signals when the control signals are generated”
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANGHYUK PARK whose telephone number is (571)270-7359. The examiner can normally be reached on 10:00AM - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on ((571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/SANGHYUK PARK/Primary Examiner, Art Unit 2623
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