DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1 recites many limitations separated by commas, which can be confusing. It is suggested that Applicant amend the claim to have a colon after the term “comprising” and semicolon after each method limitation to clearly identify each limitation. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 10-12, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shigeta (JP 2004128368 A; see machine translation) in view of Sakai et al. (WO 2023/282126; see machine translation; hereinafter Sakai).
With regards to claims 1 and 11, Shigeta teaches a method (and an apparatus) of inspecting defects in a semiconductor ([0001]), the method comprising
inspecting, by an exterior inspection unit, an exterior of a semiconductor (third step; [0010]),
inspecting, by a function inspection unit, functions of the semiconductor (sixth step; [0010]),
performing, by a pretreatment tester, a pretreatment on the semiconductor (fourth-fifth step; [0010]),
performing, by a second inspection unit, a second inspection on the semiconductor for which the pretreatment has been completed (ninth step; [0010]).
However, Shigeta is silent regarding the method comprising: performing, by a first ultrasonic inspection unit, a first ultrasonic inspection on the semiconductor, and inspecting, by a cross-sectional inspection unit, a cross-section of the semiconductor when the second ultrasonic inspection shows that delamination has increased after the pretreatment.
Sakai teaches an inspection method (abstract) similar to Shigeta and the instant invention. Sakai further teaches performing, by a first ultrasonic inspection unit, a first ultrasonic inspection on the semiconductor, and inspecting, by a cross-sectional inspection unit, a cross-section of the semiconductor ([0022, 0024, 0029]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the method of operating the ultrasonic inspection unit and cross-section inspection unit as taught by Sakai to each inspection method/apparatus of Shigeta to further test for internal structure such as delamination ([0029]; Sakai). Thus, the combination of Shigeta and Sakai would teach inspecting, by a cross-sectional inspection unit, a cross-section of the semiconductor ([0029]; Sakai) when the second ultrasonic inspection shows that delamination has increased after the pretreatment (it is noted that the cross-sectional inspection unit is capable of performing when the second ultrasonic inspection shows delamination).
With regards to claims 2 and 12, Shigeta, as combined with Sakai, teaches the method of claim 1 and the apparatus of claim 11, respectively, wherein during the inspecting of the cross-section, the cross-section of a lead portion of the semiconductor is inspected ([0024, 0029]; Sakai).
With regards to claims 10 and 20, Shigeta, as combined with Sakai, teaches the method of claim 1 and the apparatus of claim 11, respectively, wherein the method of inspecting defects is incorporated into a vehicle production process (it is noted that the claim does not include additional limitation to further distinguish the claimed from those of the prior art. The claim merely provides a suggested use of the claimed invention. Since Shigeta and Sakai teaches the totality of claim 1 and 11, Shigeta, as combined with Sakai, is considered to teach the claimed invention).
Claims 3-5, 9, 13-15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Shigeta (JP 2004128368 A; see machine translation) in view of Sakai et al. (WO 2023/282126; see machine translation; hereinafter Sakai), and further in view of Konishi et al. (US Publication 2013/0342956; hereinafter Konishi).
With regards to claims 3 and 13, Shigeta, as combined with Sakai, teaches the method of claim 2 and the apparatus of claim 12, respectively. However, Shigeta, as combined with Sakai, is silent regarding wherein the inspection of the cross-section of the lead portion is carried out using ion milling equipment.
Konishi teaches a method of making an electronic component (abstract), wherein cutting a cross-section is carried out using ion milling equipment ([0037]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to replace one known method of cutting such as those taught by Konishi with another known cutting method (“diced”; [0010]; Shigeta) as taught by Shigeta, as combined with Sakai, to obtain a smooth section suitable for subsequent inspection ([0037]; Konishi).
With regards to claims 4 and 14, Shigeta, as combined with Sakai and Konishi, teaches the method of claims 3 and the apparatus of claim 13, respectively, further comprising performing a verification of reliability of the semiconductor when it is determined that delamination has occurred on the cross-section of the lead portion after inspecting the cross-section ([0029]; Sakai).
With regards to claims 5 and 15, Shigeta, as combined with Sakai and Konishi, teaches the method of claim 3 and the apparatus of claim 13, respectively, further comprising determining that the semiconductor is defect-proof when it is determined that delamination has occurred under a preset delamination level on the cross-section of the lead portion after inspecting the cross-section ([0022, 0029]; Sakai).
With regards to claims 9 and 19, Shigeta, as combined with Sakai and Konishi, method of claim 4 and the apparatus of claim 14, respectively. However, Shigeta, as combined with Sakai and Konishi, is silent regarding the method further comprising performing a third ultrasonic inspection after performing the verification of the reliability.
It has been held that the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (see MPEP§ 2144.04, part VI, B). In this instance, there has been no unexpected result disclosed with the additional third ultrasonic inspection step.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to duplicate the ultrasonic inspection as taught by Shigeta, as combined with Sakai and Konishi, with reasonable expectation of having the benefit of additional ultrasonic inspection to verify the absence of defects as originally intended ([0022]; Sakai).
Claims 6-8 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Shigeta (JP 2004128368 A; see machine translation) in view of Sakai et al. (WO 2023/282126; see machine translation; hereinafter Sakai) and Konishi et al. (US Publication 2013/0342956; hereinafter Konishi) as applied to claims 3 and 13, and further in view of Nagata et al. (US Publication 2023/0413451; hereinafter Nagata).
With regards to claims 6 and 16, Shigeta, as combined with Sakai and Konishi, teaches the method of claim 3 and the apparatus of claim 13, respectively. However, Shigeta, as combined with Sakai and Konishi, is silent regarding wherein the verification of the reliability includes a temperature and cycle test.
Nagata teaches a method of manufacturing circuit board (abstract), wherein the verification of the reliability includes a temperature and cycle test ([0059]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the method and apparatus as taught by Nagata to test the circuit board to the method and apparatus as taught by Shigeta, as combined with Sakai and Konishi, to evaluate the reliability of the semiconductor components ([0059]; Nagata).
With regards to claims 7 and 17, Shigeta, as combined with Sakai, Konishi, and Nagata, teaches the method of claim 6 and the apparatus of claim 16, respectively, wherein the temperature and cycle test includes a heat shock test ([0059]; Nagata).
With regards to claims 8 and 18, Shigeta, as combined with Sakai, Konishi, and Nagata, teaches the method of claim 7 and the apparatus of claim 17, respectively, wherein the heat shock test is performed under conditions of 1,000 cycles to 2,000 cycles and a temperature of -55 °C to 125 °C ([0059]; Nagata).
Conclusion
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/QXN/Examiner, Art Unit 2853
/STEPHEN D MEIER/Supervisory Patent Examiner, Art Unit 2853
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