Prosecution Insights
Last updated: April 19, 2026
Application No. 18/888,010

INTELLIGENT SCHEDULING OF OPERATIONS IN A STORAGE SYSTEM

Non-Final OA §103§112
Filed
Sep 17, 2024
Examiner
CHAN, TRACY C
Art Unit
2138
Tech Center
2100 — Computer Architecture & Software
Assignee
Pure Storage Inc.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
79%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
280 granted / 354 resolved
+24.1% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
16 currently pending
Career history
370
Total Applications
across all art units

Statute-Specific Performance

§101
4.5%
-35.5% vs TC avg
§103
56.3%
+16.3% vs TC avg
§102
10.7%
-29.3% vs TC avg
§112
15.7%
-24.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 354 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Application This office action is in response to the Application filed on 09/17/2024. Claims 1-20 are presented for examination. Drawings The drawings submitted on 09/17/2024 are accepted. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 8 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 8 recites limitations “the set of background operations are performed by the first non-volatile memory module outside of the time period when a priority of the set of background operations exceeds as threshold priority”. It is unclear what scope and meaning the limitation “exceeds as threshold priority” refers to. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-7 and 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Malwankar et al. (US 10,241,722; hereinafter Malwankar) in view of Riska et al. (US 2009/0132754; hereinafter Riska). Regarding independent claims 1, 12, and 20, taking claim 1 as exemplary analysis, Malwankar teaches An apparatus (Fig. 1; claim 1, method; claim 19, A non-transitory computer readable storage medium having instructions that, when executed by a processing device of a storage server that manages a plurality of solid state storage devices (SSDs), cause the processing device to), comprising: a plurality of non-volatile memory modules (Fig. 6, SSD 150a~z); and a processing device operatively coupled to the plurality of non-volatile memory modules (Fig. 1, I/O Controller 108 coupled to SSD 150), the processing device configured to: analyze a set of storage operations to be performed on the plurality of non-volatile memory modules (col. 12, ll. 40-42, when read module 257 receives a request to read data from an SSD, it can first determine the SSD on which the data is stored); and coordinate a time period for a set of background operations to be performed by a first non-volatile memory module of the plurality of non-volatile memory modules ( col. 6, ll. 59-67 & col. 7, ll. 1-20, Management module 115 may determine the background operation schedule based on a particular array configuration and/or based on information about the SSDs, such as maximum amounts of time for them to complete background operation operations, a minimum frequency for performing background operations, and so on. In some implementations, management module 115 may receive one or more attributes associated with a background operation to be executed by an SSD. For example, management module 115 may receive the duration of a background operation for a particular SSD. Management module 115 may also receive a maximum time interval for executing the background operation (e.g., the maximum amount of time between performing garbage collection operations, which may be equivalent to the minimum frequency for performing the garbage collection operations). Based on this information, management module 115 may allocate a time window for each SSD 150A-Z.). Malwankar teaches coordinate a time period for a set of background operations based on attributes associated with a background operation including background operation being delayed for a threshold time (col. 11, ll. 50-67, To generate the schedule, scheduling module 261 may receive from an SSD one or more attributes 274 associated with a background operation to be executed by the SSD...the attributes 274 may include a duration of the background operation and/or a maximum interval between background operations (or a minimum frequency of background operations)), however, Malwankar does not expressly teach determine the background operation schedule based on the set of storage operations. In an analogous art of memory operation scheduling, Riska teaches analyze a set of storage operations to be performed on the plurality of non-volatile memory modules ( [0028], User service requests are also referred to herein as “foreground” requests. Foreground requests are scheduled with a higher priority that “background” requests that are generated internally in the data storage device 134; [0030], The cumulative data histogram 154 comprises a distribution of past lengths of idle times between successive foreground user service requests); and coordinate a time period for a set of background operations to be performed by a first non-volatile memory module of the plurality of non-volatile memory modules based on the set of storage operations ([0033], The schedule circuit 160 schedules background service requests 162 following a user service request (such as user service request 142) after a time delay that is controlled by the schedule circuit 160 as a schedule function 168 of the cumulative data histogram 154 and a calculated maximum length 164 of a busy time of the background service request 162. In case a user foreground job arrives before the maximum background busy time is reached, the algorithm allows the current background job to finish, but no additional background jobs are started). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention was made, with the teachings of Malwankar and Riska before them, to incorporate Riska’s scheduling background service requests based on idle times between successive foreground requests because of higher priorities to meet user requests and foreground service average performance target (Riska [0034]-[0035]). Regarding claim(s) 2 and 13, the combination of Malwankar and Riska further teaches wherein to coordinate the time period the processing device is further configured to: determine a schedule based on one or more of the set of storage operations and the set of background operations (Riska [0033], The schedule circuit 160 schedules background service requests 162 following a user service request (such as user service request 142) after a time delay that is controlled by the schedule circuit 160 as a schedule function 168 of the cumulative data histogram 154 and a calculated maximum length 164 of a busy time of the background service request 162). Regarding claim(s) 3 and 14, the combination of Malwankar and Riska further teaches wherein to coordinate the time period the processing device is further configured to: transmit a token to the first non-volatile memory module, wherein the token grants the first non-volatile memory module permission to perform the set of background operations during the time period (Malwankar, col. 12, ll. 17-35, scheduling module 261 may send the notification to the SSD at the start of the time window, where the SSD is to perform the background operation responsive to receiving the notification. Thus, scheduling module 261 can send a notification each time a background operation is to be performed based on the generated schedule). Regarding claim(s) 4 and 15, the combination of Malwankar and Riska further teaches wherein to coordinate the time period the processing device is further configured to: transmit a message to the first non-volatile memory module indicating the time period (Malwankar, col. 12, ll. 17-35, scheduling module 261 may send the notification to the SSD at the start of the time window, where the SSD is to perform the background operation responsive to receiving the notification. Thus, scheduling module 261 can send a notification each time a background operation is to be performed based on the generated schedule. In some implementations, scheduling module 261 may send a notification to the SSD that includes the schedule of multiple time windows allocated to the SSD for performing background operations. In this implementation, scheduling module 261 may send the notification to the SSD prior to the first time window in the schedule so that the SSD may perform the background operations according to the time windows in the schedule). Regarding claim(s) 5 and 16, the combination of Malwankar and Riska further teaches wherein the time period is based on a requested time period received from the first non-volatile memory module (Malwankar, col. 11, ll. 50-67, To generate the schedule, scheduling module 261 may receive from an SSD one or more attributes 274 associated with a background operation to be executed by the SSD...the attributes 274 may include a duration of the background operation and/or a maximum interval between background operations (or a minimum frequency of background operations)). Regarding claim(s) 6, the combination of Malwankar and Riska further teaches wherein the processing device is located on a first storage node of a storage system and the plurality of non-volatile memory modules are located on a second storage node of the storage system (Malwankar, Fig. 1, I/O controller is on a first node; SSD is on a second node). Regarding claim(s) 7 and 17, the combination of Malwankar and Riska further teaches wherein the first non-volatile memory module refrains from performing the set of background operations until the time period (Malwankar, col. 7, ll. 15-17, Each SSD 150A-Z performs background operations during their allotted time windows, and refrains from performing background operations outside of the allotted time windows). Regarding claim(s) 9, the combination of Malwankar and Riska further teaches wherein the set of background operations are performed by the first non-volatile memory module outside of the time period when the set of background operations have been delayed for a threshold time (Malwankar col. 11, ll. 50-67, To generate the schedule, scheduling module 261 may receive from an SSD one or more attributes 274 associated with a background operation to be executed by the SSD...the attributes 274 may include a duration of the background operation and/or a maximum interval between background operations (or a minimum frequency of background operations)). Regarding claim(s) 10 and 18, the combination of Malwankar and Riska further teaches wherein the processing device is further configured to: receive a message indicating the set of background operations from first non-volatile memory module (Riska [0032], background service requests 162 and calculated busy time lengths 164 associated with each background service request 162); and determine the time period based on the message ([0033], The schedule circuit 160 schedules background service requests 162 following a user service request (such as user service request 142) after a time delay that is controlled by the schedule circuit 160 as a schedule function 168 of the cumulative data histogram 154 and a calculated maximum length 164 of a busy time of the background service request 162). Regarding claim(s) 11 and 19, the combination of Malwankar and Riska further teaches wherein the processing device is further configured to: coordinate a second time period for a second set of background operations to be performed by a first non-volatile memory module based on the set of storage operations (Riska, [0052], The algorithm distinguishes between infinite amount of background work (for example repeating background media scans) and finite amount of background work), wherein the set of background operations are for a first schedulable unit of the first non-volatile memory module and the second set of background operations are for a second schedulable unit of the first non-volatile memory module (Riska, [0053], For infinite amount of background work, the goal is to complete as much as possible background work. So the tuple (IW, TE) is chosen to maximize the amount of work that can be accomplished; [0054], For finite amount of background work, the goal is to complete the required amount of work as fast as possible. This means that the tuple (IW, TE) should be the one that ensure work completion with the shortest amount of IW). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY C CHAN whose telephone number is (571)272-9992. The examiner can normally be reached on Monday - Friday 10 AM to 6 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIM VO can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TRACY C CHAN/ Primary Examiner, Art Unit 2138
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Prosecution Timeline

Sep 17, 2024
Application Filed
Feb 03, 2026
Non-Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
79%
With Interview (+0.0%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 354 resolved cases by this examiner. Grant probability derived from career allow rate.

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