DETAILED ACTION
The instant action is in response to application 17 September 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in France on 26 September 2023.
Response to Arguments
The 112(b) rejection has been withdrawn.
As to claim 11, applicant’s amendment is persuasive. The rejection has bene withdrawn.
As to claims 1 and 6, applicant’s arguments have been considered but are not persuasive. Applicant argues that “a correction circuit configured to: generate a correction current equal to a difference between a base current of one of the first and second transistors and a base current of the other one of the first and second transistors; and inject the correction current on an emitter of one of the first and second bipolar transistor” is not taught by Zhao. Examiner respectfully disagrees. A person of ordinary skill would recognize item OPA in the figure below takes the difference of the emitter-base current of Q1 and Q3 and injecting it into the current mirror with MP0, MP2, MP4, MP6, MP8. That current mirror then biases the base of Q1 and Q3 via MP0 and MP4. As such, one of ordinary skill in the art would recognize that the claim language “a correction circuit configured to: generate a correction current equal to a difference between a base current of one of the first and second transistors and a base current of the other one of the first and second transistors; and inject the correction current on an emitter of one of the first and second bipolar transistor” is taught by Zhuo. Unfortunately, the office must maintain the prior art rejection at this time.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhuo et als “A curvature calibrated bandgap reference with base—emitter current compensating in a 0.13 μm CMOS process” (NPL).
As to claim 1, Zhuo discloses A circuit, comprising: a bandgap circuit including: a first bipolar transistor; and a second bipolar transistor, the bandgap circuit being configured to deliver a temperature-stable DC voltage based on a difference between a base-emitter voltage of the first bipolar transistor and a base-emitter voltage of the second bipolar transistor; and a correction circuit configured to: generate a correction current equal to a difference between a base current of one of the first and second transistors and a base current of the other one of the first and second transistors; and inject the correction current on an emitter of one of the first and second bipolar transistors to correct an error (it compensated to 6.2 ppm per degree C, see section 5, results) on a value of the temperature-stable voltage resulting from a current gain (section 3 “and the same as those of Q2 and Q3; the second precondition is that the emitter area in Q2 and Q3 is M times those of Q0 and Q1”) difference between the first and second bipolar transistors.
As to claim 2, Zhuo teaches wherein the correction circuit includes a third bipolar (Q4) transistor and a fourth bipolar transistor (Q5).
As to claim 3, Zhuo teaches wherein the correction circuit further includes: a first metal-oxide-semiconductor (MOS) transistor coupled in series to the third bipolar transistor; and a second MOS transistor coupled in series to the fourth bipolar transistor (MP19, MP15).
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As to claim 4, Zhuo teaches wherein the third bipolar transistor is smaller than the fourth bipolar transistor (they are approximately 12x smaller).
As to claim 5, Zhuo teaches further comprising: a third MOS transistor; and a fourth MOS transistor, a gate of the fourth MOS transistor being coupled directly to a gate of the third MOS transistor (MP4, MP6).
As to claim 6, Zhuo teaches a device, comprising: a bandgap circuit including: a first bipolar transistor; and a second bipolar transistor, the bandgap circuit being configured to deliver a temperature-stable DC voltage based on a difference between a base-emitter voltage of the first bipolar transistor and a base-emitter voltage of the second bipolar transistor; and a correction circuit configured to generate a correction current equal to a difference between a base current of one of the first and second transistors and a base current of the other one of the first and second transistors (this is similar to claim 1 above, but does has fewer limitations and as such is anticipated for similar reasons).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Zhuo (NPL).in view of Ramorini (US 20210165438).
As to claim 7, wherein: the first bipolar transistor has smaller dimensions than the second bipolar transistor; the first and second bipolar transistors
Ramorini teaches the first (Q2) and second (Q1) bipolar transistors have their bases connected together and their emitters coupled to a first node of application of a reference potential (ground); and the bandgap circuit includes: a first metal-oxide-semiconductor (MOS) transistor (122b) having a source (connected via 122a) connected to a second node configured to receive a power supply potential and a drain coupled to the collector of the first bipolar transistor; and a second MOS transistor (121b) identical to the first MOS transistor and having a source connected to the second node, a drain coupled to the collector of the second bipolar transistor (connected via 121a), and a gate connected to a gate of the first MOS transistor, the first and second MOS transistors being configured to deliver a first current to the first bipolar transistor and a second current equal to the first current to the second bipolar transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use common base as disclosed in Ramorini to reduce the parts count.
As to claim 8, Zhuo in view of Ramorini teaches wherein the bandgap circuit comprises: a first resistor (Ramorini, R1) coupled between an emitter of first bipolar transistor and an emitter of the second bipolar transistor; and a second resistor (Ramorini, R2) coupled between the emitter of the first bipolar transistor and the first node.
As to claim 10, Zhuo in view of Ramorini teaches Zhuo wherein the correction circuit is configured to inject the correction current on a node of connection of the first resistor to the first bipolar transistor (Zhuo teaches feeding the collector, Ramorini teaches correcting the base. Either would bias the resistor in the common base configuration).
Allowable Subject Matter
Claims 9 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
Claims 11-20 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 9, the prior art fails to disclose: “wherein the bandgap circuit comprises: a first resistor connected between an emitter of the first bipolar transistor and the first node; a second resistor connected between an emitter of second bipolar transistor and the first node; a third bipolar transistor having a collector coupled to the second node; a third MOS transistor having a drain coupled to a base of the third bipolar transistor and coupled to the second node by a current source, its gate coupled to the collector of the second bipolar transistor, and its source connected to the first node; a capacitive element coupling the drain and the gate of the additional MOS transistor; and a third resistor coupled between the emitter of the second bipolar transistor and an emitter of the additional bipolar transistor” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 11, the prior art fails to disclose “a bandgap circuit including: a first node coupled to ground; a first bipolar transistor; a second bipolar transistor; a first metal-oxide-semiconductor (MOS) transistor having a source connected to a second node configured to receive a power supply potential and a drain coupled to the collector of the first bipolar transistor; anda second MOS transistor having a source connected to the second node, a drain coupled to the collector of the second bipolar transistor, and a gate connected to a gate of the first MOS transistor, the first and second MOS transistors being configured to deliver a first current to the first bipolar transistor and a second current equal to the first current to the second bipolar transistor; and a correction circuit including: a third MOS transistor; a third bipolar transistor coupled in series with the third MOS transistor between the first and second nodes; a fourth MOS transistor; a fourth bipolar transistor coupled in series with the fourth MOS transistor between the first and second nodes; and a voltage source coupling the third or fourth node to an output of the correction circuit configured to deliver the correction current,” in combination with the additionally claimed features, as are claimed by the Applicant.
Please note: while objected or allowed claims have been indicated, only the presented claims have been examined for compliance with form and 35 USC 112 consideration. As a reminder, claims that are dependent upon objected claims still require examination for form and 35 USC 112 issues even if they overcome 35 USC 102 and 103 rejections. Similarly, amendments incorporating allowable subject matter into independent claims requires reconsideration for dependent claim form and any possible 35 USC 112 issues that arise through amendments even if the 35 USC 102 and 103 rejections are overcome. As such, applicant is advised that while examiner can enter previously allowed claims or previously objected claims rewritten into independent form after final rejection, any other claims may not be entered.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached on 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M NOVAK/ Primary Examiner, Art Unit 2839
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