DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This communication is in response to the application filed on 09/17/2024.
Claims 1-20 are pending and are rejected.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/18/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claim 1-2, 5, 7-8, 10, 13-14, and 17-19 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-2 , 10-11, 14-15, and 19-20 of Patent No. 12,112,060.
Present Application 18/888111
Patent No. 12,112,060
Claims 1, 13, and 18
transmit, by the first host system and to a memory system of the one or more memory systems, a command to write data to a buffer of the memory system, the buffer coupled to the first host system and a second host system; and
transmit, by the first host system and to the second host system, an interrupt signal that indicates to suspend one or more operations at the second host system for a duration and to read the data from the buffer of the memory system based on the command.
Claim 10
the first host system has read access and write access to the buffer and the second host system has read only access to the buffer.
Claim 1
receiving, by a memory system from a first host system, a write command to store first data to a buffer of the memory system, wherein the buffer is coupled with the first host system and a second host system different than the first host system;
writing, by the memory system, the first data to the buffer of the memory system based at least in part on receiving the write command, wherein the first host system has write access and read access to the buffer and the second host system has read access to the buffer;
transmitting, to the second host system, an interrupt signal indicating to suspend one or more operations for a duration and to read the buffer based at least in part on writing the first data to the buffer; and
transmitting the first data from the buffer of the memory system to the second host system based at least in part on transmitting the interrupt signal.
Claim 11
receiving, by a first host system, an interrupt signal indicating to suspend one or more operations for a duration and to read a buffer of a memory system based at least in part on a second host system transmitting first data to the buffer of the memory system, wherein the buffer is coupled with the first host system and the second host system, the second host system different than the first host system; and
reading, by the first host system, the first data from the buffer of the memory system based at least in part on receiving the interrupt signal.
Claim 19
receive, by a memory system from a first host system, a write command to store first data to a buffer of the memory system, wherein the buffer is coupled with the first host system and a second host system different than the first host system; write, by the memory system, the first data to the buffer of the memory system based at least in part on receiving the write command, wherein the first host system has write access and read access to the buffer and the second host system has read access to the buffer;
transmit, to the second host system, an interrupt signal indicating to suspend one or more operations for a duration and read to the buffer based at least in part on writing the first data to the buffer; and
transmit the first data from the buffer of the memory system to the second host system based at least in part on transmitting the interrupt signal.
Claim 2, 14, and 19
transmit, by the first host system and to the memory system, an indication that the second host system is a target host system for the data written to the buffer.
Claims 2 and 20
receiving, by a register the memory system from the first host system, an indication that the second host system is a target host system for the first data written to the buffer.
Claim 5
erase the data stored to the buffer based on the acknowledgement feedback.
Claim 10
erasing, by the memory system, the first data from the buffer of the memory system based at least in part on transmitting the acknowledgement message from the second buffer of the memory system.
.
Claims 7 and 17
refrain, by the first host system, from performing the one or more operations at the first host system for the second duration based on receiving the second interrupt signal, wherein reading the second buffer occurs during at least a portion of the second duration.
Claim 14
refraining, by the first host system, from performing one or more ongoing operations for a duration based at least in part on receiving the interrupt signal, wherein the data is read from the buffer by the first host system during at least a portion of the duration.
Claim 8
resume, by the first host system, performing the one or more operations at the first host system after the second duration.
Claim 15
resuming, by the first host system, performing one or more operations after the duration.
Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed subject matter of the present applicant and that of Patent No. 12,112,060 are substantially the same and the claimed subject matter of the present application would have been obvious to one of ordinary skill in the art based on the claimed subject matter of Patent No. 12,112,060.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 10-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Thatcher et al. (US 20230161506 A1 ) hereafter Thatcher, in view of Kang et al. (US 20220171571 A1), hereafter Kang
Regarding claim 1, Thatcher teaches a first host system, comprising:
one or more interfaces comprising one or more signal paths operable for communications with one or more memory systems ([0009], fig. 1, host A 150a is operatively coupled to bus A interface 121a of controller 120 via host bus A); and
processing circuitry coupled with the one or more interfaces and configured to cause the first host system to ([0011] Hosts A-B 150a-150b may comprise one or more processors):
transmit, by the first host system and to a memory system of the one or more memory systems, a command to write data to a buffer of the memory system, the buffer coupled to the first host system and a second host system ([0035], fig.1, controller 120 (a memory system) may receive, from host A 150a (first host), a first write command to write first data, also received via bus A interface 121a, to memory device 131; [0036] Based on the first memory command, the first data is stored in first write buffer circuitry at least until the first data is written to the memory device. The write buffers 122a or 122b is coupled to host A and Host B (second host), as shows in fig. 1)); and
transmit, by the first host system and to the second host system, an interrupt signal that indicates to read the data from the buffer of the memory system based on the command ([0021], fig. 1, bus B interface 121b may receive, from host B 150b and via the command interface of bus B interface 121b, a second memory access command to read the first data from one or more memory devices 131-132).
Thatcher does not explicitly teach
transmit, by the first host system and to the second host system, an interrupt signal that indicates to suspend one or more operations at the second host system for a duration;
Kang teaches
transmit, by the first host system and to the second host system, an interrupt signal that indicates to suspend one or more operations at the second host system for a duration ([0010] The memory controller may suspend execution of the first command when receiving a lock request for the first command from the host; [0011] The memory controller may resume the execution of the first command when receiving an unlock request for the first command or after the execution of the first command is suspended for an amount of time corresponding to a suspend time value transmitted together with the lock request).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, message to suspend operation, as taught by Kang. One would be motivated to do so to optimize the overall performance of the memory device and a problem that performance experienced by a user using the host may be degraded.
Regarding claims 2, 14, and 19, Thatcher and Kang teach all limitations of parent claims 1, 13, and 18, wherein Thatcher further teaches the processing circuitry is further configured to cause the first host system to:
transmit, by the first host system and to the memory system, an indication that the second host system is a target host system for the data written to the buffer ([0015] bus B interface 121b comprises at least a second command interface to receive command from host B 150b, and a second data interface to transmit read data and receive write data, to/from host B 150b, via host bus B 155b).
Regarding claims 3, 15, and 20, Thatcher and Kang teach all limitations of parent claims 1, 13, and 18, Kang further teaches wherein the processing circuitry is further configured to cause the first host system to:
receive, at the first host system, a second interrupt signal that instructs the first host system to suspend one or more operations at the second host system for a second duration and to read a second buffer of the memory system ([0175], fig. 12, the processor 124 of the memory controller 120 may dequeue and execute the second command CMD_2 from the command queue CMD_Q. Therefore, the host HOST may advance the execution time of the second command CMD_2 by suspending the execution of the first command CMD_1 even without directly requesting the execution of the second command CMD_2).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, message to suspend operation, as taught by Kang. One would be motivated to do so to optimize the overall performance of the memory device and a problem that performance experienced by a user using the host may be degraded.
Regarding claims 4 and 16, Thatcher and Kang teach all limitations of parent claims 3 and 15, wherein Kang further teaches the processing circuitry is further configured to cause the first host system to:
read, from the second buffer and based on the second interrupt signal, acknowledgement feedback associated with the data ([0156] When the execution of the first command CMD_1 is completed after resuming execution of the first command CMD_1, the processor 124 may transmit the response message for the execution result of the first command CMD_1 to the host HOST).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, results are sent to the host as a feedback, as taught by Kang. One would be motivated to do so that the host can control the execution order of commands, and prevent delays in execution of other commands requiring rapid processing for QoS satisfaction due to the first command.
Regarding claim 5, Thatcher and Kang teach the first host system of claim 4, wherein Kang further teaches the processing circuitry is further configured to cause the first host system to:
erase the data stored to the buffer based on the acknowledgement feedback ([0181] when the first command CMD_1 is aborted, information related to the first command CMD_1 may be erased from the memory controller 120 except interrupted point of execution of the first command CMD_1).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, erase data in memory after command is aborted, as taught by Kang. One would be motivated to do so that the host can control the execution order of commands, and prevent delays in execution of other commands requiring rapid processing for QoS satisfaction due to the first command.
Regarding claim 6, Thatcher and Kang teach the first host system of claim 4, wherein Kang further teaches the processing circuitry is further configured to cause the first host system to:
invalidate the data stored in the buffer based on the acknowledgement feedback ([0171] When the processor 124 of the memory controller 120 receives the unlock request for the first command CMD_1 from the host and resumes execution of the first command CMD_1, the processor 124 may execute an operation in which the first command CMD_1 is retrieved from the locker and then removed, or an operation to invalidate the first command CMD_1 stored in the lock).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, invalidate the stored command data in memory after command is aborted, as taught by Kang. One would be motivated to do so that the host can control the execution order of commands, and prevent delays in execution of other commands requiring rapid processing for QoS satisfaction due to the first command.
Regarding claim 10, Thatcher and Kang teach the first host system of claim 1, wherein Thatcher further teaches the first host system has read access and write access to the buffer and the second host system has read only access to the buffer ([0039] By the controller and in first write buffer circuitry, the first data is stored at least until the first data is written to a memory device by the controller; [0040] controller 120 may receive from host B 150b and via the command interface of bus B interface 121b, a read command to read the data at the first address in memory device 131 ).
Regarding claim 11, Thatcher and Kang teach the first host system of claim 1, wherein Thatcher further teaches the data is stored to a first portion of the buffer, and wherein the first host system has read access and write access to the first portion of the buffer and the second host system has read only access to the first portion of the buffer ([0036] Based on the first memory command, the first data is stored in first write buffer circuitry at least until the first data is written to the memory device. For example, based on the first write command, controller 120 may store the first write data in bus A write buffer 122a at least until the first write data is stored. A second memory command to read the first data is received).
Regarding claim 12, Thatcher and Kang teach the first host system of claim 11, wherein Thatcher further teaches the first host system has read only access to a second portion of the buffer different from the first portion of the buffer and the second host system has read access and write access to the second portion of the buffer ([0021] bus interface A 121a may receive, from host A 150a and via the command interface of bus interface A 121a, a first memory access command to write first data to one or more memory devices 131-132. This first data is received from host A 150a via the data interface bus interface A 121a. Based on the first memory access command, bus A write buffer 122a may store this first data at least until it is written to one or more memory devices 131-132. Bus B interface 121b may receive, from host B 150b and via the command interface of bus B interface 121b, a second memory access command to read the first data from one or more memory devices 131-13).
Regarding claim 13, Thatcher teaches a method by a first host system, comprising:
transmitting, by the first host system and to a memory system, a command to write data to a buffer of the memory system, the buffer coupled to the first host system and a second host system ([0035], fig.1, controller 120 (a memory system) may receive, from host A 150a (first host), a first write command to write first data, also received via bus A interface 121a, to memory device 131; [0036] Based on the first memory command, the first data is stored in first write buffer circuitry at least until the first data is written to the memory device. The write buffers 122a or 122b is coupled to host A and Host B (second host), as shows in fig. 1)); and
transmitting, by the first host system and to the second host system, an interrupt signal that indicates to read the data from the buffer of the memory system based on the command ([0021], fig. 1, bus B interface 121b may receive, from host B 150b and via the command interface of bus B interface 121b, a second memory access command to read the first data from one or more memory devices 131-132).
Thatcher does not explicitly teach
transmit, by the first host system and to the second host system, an interrupt signal that indicates to suspend one or more operations at the second host system for a duration;
Kang teaches
transmit, by the first host system and to the second host system, an interrupt signal that indicates to suspend one or more operations at the second host system for a duration ([0010] The memory controller may suspend execution of the first command when receiving a lock request for the first command from the host; [0011] The memory controller may resume the execution of the first command when receiving an unlock request for the first command or after the execution of the first command is suspended for an amount of time corresponding to a suspend time value transmitted together with the lock request).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, message to suspend operation, as taught by Kang. One would be motivated to do so to optimize the overall performance of the memory device and a problem that performance experienced by a user using the host may be degraded.
Regarding claim 18, Thatcher teaches a non-transitory computer-readable medium storing code ([0047] a non-transitory computer readable medium), the code comprising instructions executable by one or more processors to:
transmit, by a first host system and to a memory system, a command to write data to a buffer of the memory system, the buffer coupled to the first host system and a second host system ([0035], fig.1, controller 120 (a memory system) may receive, from host A 150a (first host), a first write command to write first data, also received via bus A interface 121a, to memory device 131; [0036] Based on the first memory command, the first data is stored in first write buffer circuitry at least until the first data is written to the memory device. The write buffers 122a or 122b is coupled to host A and Host B (second host), as shows in fig. 1)); and
transmit, by the first host system and to the second host system, an interrupt signal that indicates to read the data from the buffer of the memory system based on the command ([0021], fig. 1, bus B interface 121b may receive, from host B 150b and via the command interface of bus B interface 121b, a second memory access command to read the first data from one or more memory devices 131-132)
Thatcher does not explicitly teach
transmit, by the first host system and to the second host system, an interrupt signal that indicates to suspend one or more operations at the second host system for a duration;
Kang teaches
transmit, by the first host system and to the second host system, an interrupt signal that indicates to suspend one or more operations at the second host system for a duration ([0010] The memory controller may suspend execution of the first command when receiving a lock request for the first command from the host; [0011] The memory controller may resume the execution of the first command when receiving an unlock request for the first command or after the execution of the first command is suspended for an amount of time corresponding to a suspend time value transmitted together with the lock request).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, message to suspend operation, as taught by Kang. One would be motivated to do so to optimize the overall performance of the memory device and a problem that performance experienced by a user using the host may be degraded.
Claims 7-8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Thatcher, in view of Kang, and further in view of LEE et al. (US 20190079698 A1) hereafter Lee.
Regarding claims 7 and 17, Thatcher and Kang teach all limitations of parent claims 3 and 15, Thatcher does not explicitly teach wherein the processing circuitry is further configured to cause the first host system to:
refrain, by the first host system, from performing the one or more operations at the first host system for the second duration based on receiving the second interrupt signal, wherein reading the second buffer occurs during at least a portion of the second duration.
Lee teaches
refrain, by the first host system, from performing the one or more operations at the first host system for the second duration based on receiving the second interrupt signal, wherein reading the second buffer occurs during at least a portion of the second duration ([0096] The controller 1330 may suspend the DMA write operation for the memory chip 1311, in response to the read request (S135 of FIG. 7 and a time point t13 of FIG. 8)).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, a suspend commend, as taught by Lee. One would be motivated to do so to operations and configurations of a storage device which stores and outputs data.
Regarding claim 8, Thatcher, Kang, and Lee teach the first host system of claim 7, wherein Kang further teaches the processing circuitry is further configured to cause the first host system to:
resume, by the first host system, performing the one or more operations at the first host system after the second duration ([0151] The unlock request for the first command CMD_1 is a request instructing to resume execution of the suspended first command CMD_1).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, resume operation after suspend, as taught by Kang. One would be motivated to do so to optimize the overall performance of the memory device and a problem that performance experienced by a user using the host may be degraded.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Thatcher, in view of Kang, and further in view of Yong et al. (US 20120307827 A1) hereafter Yong.
Regarding claim 9, Thatcher and Kang teach the first host system of claim 3, Thatcher does not explicitly teach wherein the interrupt signal comprises a unicast signal, a multicast signal, or a broadcast signal.
Yong teaches the interrupt signal comprises a unicast signal, a multicast signal, or a broadcast signal ([0055] The first DMA control unit may be informed that the multicast message MM is stored by an interrupt signal transmitted from the first processor).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, the interrupt signal comprise a multicast message, as taught by Yong. One would be motivated to do so to provide efficient communication between processors in multi-processor device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
SHIMADA (US 20230075635 A1) and HSU (US 20220137874 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH NGUYEN whose telephone number is (571)270-0657. The examiner can normally be reached M-F.
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/ANH NGUYEN/Primary Examiner, Art Unit 2458