DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This communication is in response to the amendment filed on 06/11/2026.
Claims 1-20 are pending and are rejected.
Response to Arguments
Applicant's arguments filed 06/11/2026 have been fully considered but they are not persuasive. Applicants are arguing in substance the following:
Arguments to claims 1, 12, and 18: a) The claim feature recites three systems: a first host system, a second host system, and a memory system while the Office Action mapped the controller 120 to both “the memory system” and “the second host system.”
b) Kang does not teaches transmit, by the first host system and to the second host system, an interrupt signal that indicates to suspend one or more operations at the second host system for a duration
Response to the arguments:
a) The Non-Final (03/11/2026) mapped host A, host B, and controller 120 to the claimed elements a first host system, a second host system, and a memory system, respectively. Thatcher, paragraph 0021 and fig. 1 teaches that “control circuitry 129 may detect that the first data is stored in bus A write buffer 122a and based on this detection, cause the first data to be retrieved from bus A write buffer 122a and be transmitted to host B 150b via the data interface of bus B interface 121b”. In this paragraph, Thatcher discloses that after data is stored in the write buffer 122a, the data is retrieved based on a read command and transmitted from host A (first host system) to the host B (second host system). That is, the first host system transmits to the second host system an interrupt signal indicates that the data is to be read the data from the buffer of the memory system based on the command.
b) Kang, paragraph 0163, fig. 11 further teaches that the controller 120 receives a lock command and a key from the HOST. Controller 120 stores key information for the corresponding command in the locker together with the command. The HOST, the Controller 120, and the locker are reasonably interpreted as the claimed the first host system, the second host system, and the memory system, respectively. The claims do not require these three elements to be separate or distinct components.
The rejection is therefore maintained.
The Double Patenting rejection has been withdrawn because a Terminal Disclaimer has been filed in connection with prior patent #12112060.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 10-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Thatcher et al. (US 20230161506 A1 ) hereafter Thatcher, in view of Kang et al. (US 20220171571 A1), hereafter Kang
Regarding claim 1, Thatcher teaches a first host system, comprising:
one or more interfaces comprising one or more signal paths operable for communications with one or more memory systems ([0009], fig. 1, host A 150a is operatively coupled to bus A interface 121a of controller 120 via host bus A); and
processing circuitry coupled with the one or more interfaces and configured to cause the first host system to ([0011] Hosts A-B 150a-150b may comprise one or more processors):
transmit, by the first host system and to a memory system of the one or more memory systems, a command to write data to a buffer of the memory system, the buffer coupled to the first host system and a second host system ([0035], fig.1, controller 120 (a memory system) may receive, from host A 150a (first host), a first write command to write first data, also received via bus A interface 121a, to memory device 131; [0036] Based on the first memory command, the first data is stored in first write buffer circuitry at least until the first data is written to the memory device. The write buffers 122a or 122b is coupled to host A and Host B (second host), as shows in fig. 1)); and
transmit, by the first host system and to the second host system, an interrupt signal that indicates to read the data from the buffer of the memory system based on the command ([0021], fig. 1, bus B interface 121b may receive, from host B 150b and via the command interface of bus B interface 121b, a second memory access command to read the first data from one or more memory devices 131-132).
Thatcher does not explicitly teach
transmit, by the first host system and to the second host system, an interrupt signal that indicates to suspend one or more operations at the second host system for a duration;
Kang teaches
transmit, by the first host system and to the second host system, an interrupt signal that indicates to suspend one or more operations at the second host system for a duration ([0010] The memory controller may suspend execution of the first command when receiving a lock request for the first command from the host; [0011] The memory controller may resume the execution of the first command when receiving an unlock request for the first command or after the execution of the first command is suspended for an amount of time corresponding to a suspend time value transmitted together with the lock request).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, message to suspend operation, as taught by Kang. One would be motivated to do so to optimize the overall performance of the memory device and a problem that performance experienced by a user using the host may be degraded.
Regarding claims 2, 14, and 19, Thatcher and Kang teach all limitations of parent claims 1, 13, and 18, wherein Thatcher further teaches the processing circuitry is further configured to cause the first host system to:
transmit, by the first host system and to the memory system, an indication that the second host system is a target host system for the data written to the buffer ([0015] bus B interface 121b comprises at least a second command interface to receive command from host B 150b, and a second data interface to transmit read data and receive write data, to/from host B 150b, via host bus B 155b).
Regarding claims 3, 15, and 20, Thatcher and Kang teach all limitations of parent claims 1, 13, and 18, Kang further teaches wherein the processing circuitry is further configured to cause the first host system to:
receive, at the first host system, a second interrupt signal that instructs the first host system to suspend one or more operations at the first host system for a second duration and to read a second buffer of the memory system ([0175], fig. 12, the processor 124 of the memory controller 120 may dequeue and execute the second command CMD_2 from the command queue CMD_Q. Therefore, the host HOST may advance the execution time of the second command CMD_2 by suspending the execution of the first command CMD_1 even without directly requesting the execution of the second command CMD_2).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, message to suspend operation, as taught by Kang. One would be motivated to do so to optimize the overall performance of the memory device and a problem that performance experienced by a user using the host may be degraded.
Regarding claims 4 and 16, Thatcher and Kang teach all limitations of parent claims 3 and 15, wherein Kang further teaches the processing circuitry is further configured to cause the first host system to:
read, from the second buffer and based on the second interrupt signal, acknowledgement feedback associated with the data ([0156] When the execution of the first command CMD_1 is completed after resuming execution of the first command CMD_1, the processor 124 may transmit the response message for the execution result of the first command CMD_1 to the host HOST).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, results are sent to the host as a feedback, as taught by Kang. One would be motivated to do so that the host can control the execution order of commands, and prevent delays in execution of other commands requiring rapid processing for QoS satisfaction due to the first command.
Regarding claim 5, Thatcher and Kang teach the first host system of claim 4, wherein Kang further teaches the processing circuitry is further configured to cause the first host system to:
erase the data stored to the buffer based on the acknowledgement feedback ([0181] when the first command CMD_1 is aborted, information related to the first command CMD_1 may be erased from the memory controller 120 except interrupted point of execution of the first command CMD_1).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, erase data in memory after command is aborted, as taught by Kang. One would be motivated to do so that the host can control the execution order of commands, and prevent delays in execution of other commands requiring rapid processing for QoS satisfaction due to the first command.
Regarding claim 6, Thatcher and Kang teach the first host system of claim 4, wherein Kang further teaches the processing circuitry is further configured to cause the first host system to:
invalidate the data stored in the buffer based on the acknowledgement feedback ([0171] When the processor 124 of the memory controller 120 receives the unlock request for the first command CMD_1 from the host and resumes execution of the first command CMD_1, the processor 124 may execute an operation in which the first command CMD_1 is retrieved from the locker and then removed, or an operation to invalidate the first command CMD_1 stored in the lock).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, invalidate the stored command data in memory after command is aborted, as taught by Kang. One would be motivated to do so that the host can control the execution order of commands, and prevent delays in execution of other commands requiring rapid processing for QoS satisfaction due to the first command.
Regarding claim 10, Thatcher and Kang teach the first host system of claim 1, wherein Thatcher further teaches the first host system has read access and write access to the buffer and the second host system has read only access to the buffer ([0039] By the controller and in first write buffer circuitry, the first data is stored at least until the first data is written to a memory device by the controller; [0040] controller 120 may receive from host B 150b and via the command interface of bus B interface 121b, a read command to read the data at the first address in memory device 131 ).
Regarding claim 11, Thatcher and Kang teach the first host system of claim 1, wherein Thatcher further teaches the data is stored to a first portion of the buffer, and wherein the first host system has read access and write access to the first portion of the buffer and the second host system has read only access to the first portion of the buffer ([0036] Based on the first memory command, the first data is stored in first write buffer circuitry at least until the first data is written to the memory device. For example, based on the first write command, controller 120 may store the first write data in bus A write buffer 122a at least until the first write data is stored. A second memory command to read the first data is received).
Regarding claim 12, Thatcher and Kang teach the first host system of claim 11, wherein Thatcher further teaches the first host system has read only access to a second portion of the buffer different from the first portion of the buffer and the second host system has read access and write access to the second portion of the buffer ([0021] bus interface A 121a may receive, from host A 150a and via the command interface of bus interface A 121a, a first memory access command to write first data to one or more memory devices 131-132. This first data is received from host A 150a via the data interface bus interface A 121a. Based on the first memory access command, bus A write buffer 122a may store this first data at least until it is written to one or more memory devices 131-132. Bus B interface 121b may receive, from host B 150b and via the command interface of bus B interface 121b, a second memory access command to read the first data from one or more memory devices 131-13).
Regarding claim 13, Thatcher teaches a method by a first host system, comprising:
transmitting, by the first host system and to a memory system, a command to write data to a buffer of the memory system, the buffer coupled to the first host system and a second host system ([0035], fig.1, controller 120 (a memory system) may receive, from host A 150a (first host), a first write command to write first data, also received via bus A interface 121a, to memory device 131; [0036] Based on the first memory command, the first data is stored in first write buffer circuitry at least until the first data is written to the memory device. The write buffers 122a or 122b is coupled to host A and Host B (second host), as shows in fig. 1)); and
transmitting, by the first host system and to the second host system, an interrupt signal that indicates to read the data from the buffer of the memory system based on the command ([0021], fig. 1, bus B interface 121b may receive, from host B 150b and via the command interface of bus B interface 121b, a second memory access command to read the first data from one or more memory devices 131-132).
Thatcher does not explicitly teach
transmit, by the first host system and to the second host system, an interrupt signal that indicates to suspend one or more operations at the second host system for a duration;
Kang teaches
transmit, by the first host system and to the second host system, an interrupt signal that indicates to suspend one or more operations at the second host system for a duration ([0010] The memory controller may suspend execution of the first command when receiving a lock request for the first command from the host; [0011] The memory controller may resume the execution of the first command when receiving an unlock request for the first command or after the execution of the first command is suspended for an amount of time corresponding to a suspend time value transmitted together with the lock request).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, message to suspend operation, as taught by Kang. One would be motivated to do so to optimize the overall performance of the memory device and a problem that performance experienced by a user using the host may be degraded.
Regarding claim 18, Thatcher teaches a non-transitory computer-readable medium storing code ([0047] a non-transitory computer readable medium), the code comprising instructions executable by one or more processors to:
transmit, by a first host system and to a memory system, a command to write data to a buffer of the memory system, the buffer coupled to the first host system and a second host system ([0035], fig.1, controller 120 (a memory system) may receive, from host A 150a (first host), a first write command to write first data, also received via bus A interface 121a, to memory device 131; [0036] Based on the first memory command, the first data is stored in first write buffer circuitry at least until the first data is written to the memory device. The write buffers 122a or 122b is coupled to host A and Host B (second host), as shows in fig. 1)); and
transmit, by the first host system and to the second host system, an interrupt signal that indicates to read the data from the buffer of the memory system based on the command ([0021], fig. 1, bus B interface 121b may receive, from host B 150b and via the command interface of bus B interface 121b, a second memory access command to read the first data from one or more memory devices 131-132)
Thatcher does not explicitly teach
transmit, by the first host system and to the second host system, an interrupt signal that indicates to suspend one or more operations at the second host system for a duration;
Kang teaches
transmit, by the first host system and to the second host system, an interrupt signal that indicates to suspend one or more operations at the second host system for a duration ([0010] The memory controller may suspend execution of the first command when receiving a lock request for the first command from the host; [0011] The memory controller may resume the execution of the first command when receiving an unlock request for the first command or after the execution of the first command is suspended for an amount of time corresponding to a suspend time value transmitted together with the lock request).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, message to suspend operation, as taught by Kang. One would be motivated to do so to optimize the overall performance of the memory device and a problem that performance experienced by a user using the host may be degraded.
Claims 7-8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Thatcher, in view of Kang, and further in view of LEE et al. (US 20190079698 A1) hereafter Lee.
Regarding claims 7 and 17, Thatcher and Kang teach all limitations of parent claims 3 and 15, Thatcher does not explicitly teach wherein the processing circuitry is further configured to cause the first host system to:
refrain, by the first host system, from performing the one or more operations at the first host system for the second duration based on receiving the second interrupt signal, wherein reading the second buffer occurs during at least a portion of the second duration.
Lee teaches
refrain, by the first host system, from performing the one or more operations at the first host system for the second duration based on receiving the second interrupt signal, wherein reading the second buffer occurs during at least a portion of the second duration ([0096] The controller 1330 may suspend the DMA write operation for the memory chip 1311, in response to the read request (S135 of FIG. 7 and a time point t13 of FIG. 8)).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, a suspend commend, as taught by Lee. One would be motivated to do so to operations and configurations of a storage device which stores and outputs data.
Regarding claim 8, Thatcher, Kang, and Lee teach the first host system of claim 7, wherein Kang further teaches the processing circuitry is further configured to cause the first host system to:
resume, by the first host system, performing the one or more operations at the first host system after the second duration ([0151] The unlock request for the first command CMD_1 is a request instructing to resume execution of the suspended first command CMD_1).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, resume operation after suspend, as taught by Kang. One would be motivated to do so to optimize the overall performance of the memory device and a problem that performance experienced by a user using the host may be degraded.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Thatcher, in view of Kang, and further in view of Yong et al. (US 20120307827 A1) hereafter Yong.
Regarding claim 9, Thatcher and Kang teach the first host system of claim 3, Thatcher does not explicitly teach wherein the interrupt signal comprises a unicast signal, a multicast signal, or a broadcast signal.
Yong teaches the interrupt signal comprises a unicast signal, a multicast signal, or a broadcast signal ([0055] The first DMA control unit may be informed that the multicast message MM is stored by an interrupt signal transmitted from the first processor).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Thatcher disclosure, the interrupt signal comprise a multicast message, as taught by Yong. One would be motivated to do so to provide efficient communication between processors in multi-processor device.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH NGUYEN whose telephone number is (571)270-0657. The examiner can normally be reached M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Umar Cheema can be reached at 5712703037. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANH NGUYEN/Primary Examiner, Art Unit 2458
Prosecution Insights