DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21 – 40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 14 and 16 – 20 of U.S. Patent No. 12105952. Although the claims at issue are not identical, they are not patentably distinct from each other because each limitation of the instant claim is obviously anticipated by a corresponding limitation in the parent patent.
Instant Application 18/888463
US Patent 12105952
21. A system comprising: a fabric addressable memory connected via one or more interconnect switches having a plurality of edge ports;
1. A system comprising: a fabric addressable memory connected via one or more interconnect switches having a plurality of edge ports;
and a plurality of nodes that are each connected to the one or more interconnect switches via a respective edge port of the plurality of edge ports;
wherein at least one interconnect switch is to store a mapping between locations in a physical fabric memory block of a connected node and one or more destination port identifiers (DPIDs) that are each associated with a respective edge port of the plurality of edge ports;
wherein each interconnect switch is to store a mapping between locations in a physical fabric memory block of a connected node and one or more destination port identifiers (DPIDs) that are each associated with a respective edge port of the plurality of edge ports;
and wherein at least one edge port is to route memory access requests based on the stored mapping.
and wherein each edge port is to route a memory access request, based on the stored mapping,
from a sending node to a destination edge port of the plurality of edge ports.
As can be seen above, each limitation of the instant claim has a corresponding limitation in the US Patent that obviously anticipates the claimed invention. The first difference between the claims is that the US Patent gives additional limitations, making it more specific than required to anticipate the instant claim. The second difference between the claims is that the instant claim includes two instances of “at least one of” which is obviously anticipated by a recitation of “each” (“each” element obviously includes “at least one” same element).
Claims 22 – 40 of the instant application are similarly obviously anticipated by claims 1 – 14 and 16 – 20 of the US Patent.
Allowable Subject Matter
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The following is a statement of reasons for the indication of allowable subject matter: Claim 21 discloses, “A system comprising: a fabric addressable memory connected via one or more interconnect switches having a plurality of edge ports; wherein at least one interconnect switch is to store a mapping between locations in a physical fabric memory block of a connected node and one or more destination port identifiers (DPIDs) that are each associated with a respective edge port of the plurality of edge ports; and wherein at least one edge port is to route memory access requests based on the stored mapping.” Claims 31 and 39 include similar limitations. Boyd et al. US Patent No. 7430630 describes a routing mechanism in PCI multi-host topologies using destination ID field. When a physical or virtual host or end point receives a PCI data packet it compares a list of source identifiers with destination identifiers to determine if a source identifier included in the transaction packet is associated with a destination identifier included in the transaction packet to determine if the transaction packet has a valid association. If the transaction packet has a valid association, it is routed to the target device (Abstract). Furthermore, Fig. 7 presents a diagram that schematically illustrates the operation of a Memory to DID Translation Table according to an exemplary embodiment of the present invention. The Memory to DID Translation Table is included in bridges or switches for use when an incoming PCIe data packet does not contain a DID#. In particular, if an incoming PCIe data packet such as data packet 710 does not include a DID#, the memory address 712 in the packet is used to look up the DID# in the Memory to DID Translation Table 720 and obtain the DID# from the table, as schematically illustrated at 730, in order to identify which port in the bridge or switch is associated with the DID# in the DID Routing Table (column 7, lines 21 – 32). Boyd discloses that the system uses PCI Express protocol to communicate over an I/O fabric and that enables each host that attaches to PCI switches and shares a set of common PCI devices to have it’s own PCI 64-bit address space (column 1, lines 47 – 51). Boyd also discloses that each end-to-end association can have its own PCI Bus Memory Address Space, because the bridges or switches do not use the address for routing (column 6, lines 20 – 22). However, this is not believed to teach or suggest a “fabric addressable memory” as claimed since the specification describes a ”fabric addressable memory” as memory devices capable of processing fabric addresses associated with a global addressing scheme of the GAF [Global Addressable Fabric] (page 7, paragraph [0031] of the originally filed specification). Kapoor et al. US Patent Application Publication No. 2008/0080400 describes a method including a fabric manager implementing a scheme to discover one or more devices coupled to the switch fabric. Furthermore, the switch fabric map includes each device discovered by fabric manager, for example, as described for discovering an endpoint (page 2, paragraph [0020]). However, this is not believed to teach or suggest a “fabric addressable memory” as claimed since the specification describes a ”fabric addressable memory” as memory devices capable of processing fabric addresses associated with a global addressing scheme of the GAF [Global Addressable Fabric] (page 7, paragraph [0031] of the originally filed specification). Brown US Patent Application Publication No. 2016/0253186 describes a storage system capable of receiving storage system configuration information that is indicative of access permissions of multiple host computer ports to storage logical units that are associated with a certain set of storage system ports. Specifically, LUN mapping 120 associates LUN 110 with host ports H1 and H2. The notations S1 – S4 of the storage ports and H1 – H2 of the host ports represents a WWPN for each of these ports. However, it does not explicitly describe all of the limitations presented in the claims. Perry et al. US Patent Application Publication No. 2022/0365688 describes a system for providing high-performance access to shared computer memory via different interconnect fabrics. Specifically, exposing the memory block device may further include associating the memory block device to the particular computing device by linking the unique identifier (e.g., a first NQN) of the memory block device to the unique identifier of the particular computing device (e.g., a second NQN). For instance, controller 106 may generate an NVMe namespace for the memory block device (e.g., create a NQN for accessing the memory block device), may attach the NVMe namespace to a port that is associated with the specified interconnect fabric that will be used to exchange data between the particular computing device and the memory block device, and may provide messaging to the particular computing device that it may access the memory block device by including the NQN of the memory block device in access requests issued over the selected interconnect fabric using the selected transport. However, it does not explicitly describe all of the limitations presented in the claims. Dhatchinamoorthy et al. US Patent Application Publication No. 2022/0231905 describes that storage fabric service may include configuration functions for configuring port identifiers and port forwarding services, in addition to supporting volume definition and subsystem management for host nodes mapped to one or more storage resources in the storage node. However, it does not explicitly describe all of the limitations presented in the claims. Feehrer et al. US Patent No. 11182309 describes a Fabric Attached Memory that provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit, over a network fabric. Specifically, it is disclosed that the fabric attached memory may provide address mapping and memory access request distribution techniques for ensuring that the fabric attached memory capacity is fully utilized. However, it does not explicitly describe all of the limitations presented in the claims. Tavallaei et al. US Patent Application Publication No. 2022/0075520 describes a computing device comprising two or more independently coherent nodes. Specifically, the inclusion of a fabric manager is disclosed, that may be configured to monitor and govern the entire computing environment. For example, the fabric manager may set and apply policies that facilitate efficient and secure use of the memory pool by each of the plurality of compute nodes. Furthermore, it is disclosed that a method for memory address mapping may comprise receiving a memory access request from a first compute node including a host physical address for the first compute node; mapping the host physical address for the received request to a system address map including ranges of host physical addresses for each of the two or more independently coherent compute nodes; outputting a package physical address based on the mapped host physical address. However, it does not explicitly describe all of the limitations presented in the claims. Park et al. US Patent No. 9537751 describes a divided hierarchical network system based on software defined networks, including: an edge controller; generating mapping information such that each of a plurality of edge ports of each of a plurality of switches that form the lower level corresponds to each of a plurality of virtual ports of one virtual switch. However, it does not explicitly describe all of the limitations presented in the claims. Rajan et al. US Patent Application Publication No. 2006/0206603 describes an intelligent storage switch with a flexible virtualization system to enable efficient service of file and block protocol data access requests for information stored on the system. Specifically, it is disclosed that a volume manager provides virtualization mapping metadata to a storage switch over a switch port. However, it does not explicitly describe all of the limitations presented in the claims. Li et al. US Patent Application Publication No. 2021/0004171 describes a host and a storage system communicating with each other by using a NVMeoF protocol. Specifically, it is disclosed that each control node may obtain an identifier of a host port connected to the control node and then replace a mapping relationship between a virtual host and a disk code of the logical disk with a mapping relationship between a host port identifier and the disk code of the logical disk. However, it does not explicitly describe all of the limitations presented in the claims. Worley et al. US Patent Application Publication No. 2018/0167352 describes a method for reducing IP addresses usage of NVMe over fabrics devices. However, it does not explicitly describe all of the limitations presented in the claims. Warfield et al. US Patent Application Publication No. 2014/0025770 describes that the population of a MAC table may happen as a by product of data packet communication during the population of a ARP table (i.e., the switch may learn of a MAC address to port association when an ARP request is in progress). However, it does not explicitly describe all of the limitations presented in the claims.
Conclusion
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/RALPH A VERDERAMO III/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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March 26, 2026
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