Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 8 and 11-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nomura US publication no.: US 2018/0062633 A1.
Regarding claim 1, Nomura teaches, A gate driver circuit (gate drive circuit 20-1-2, figure 4) for driving an N-type power transistor that constitutes a switching circuit (see bridge circuit 110, figure 4; paragraph 55, where it can be seen that NMOS is used) , comprising: a high-level line on which a voltage higher than a source of the power transistor is generated (see the voltage line as seen in figure 4); a turn-on transistor (sw1-sw3, figure 4; paragraph 78) configured to source a current to a gate of the power transistor; a turn-off transistor (sw4-sw6, figure 4; paragraph 83) configured to sink a current from the gate of the power transistor; and a control circuit configured to control the turn-on transistor and the turn-off transistor (see paragraphs 108-113 and figure 8, where the switches sw1-sw6 are controlled in an on/off state), wherein the turn-on transistor includes a plurality of transistors connected between the gate of the power transistor and the high-level line (see sw1-sw3, figure 4), and wherein the control circuit controls on/off states of the plurality of transistors so that when turning the power transistor on, the turn-on transistor has a first drive capability in a first period, second drive capability lower than the first drive capability in a second period, and a third drive capability higher than the second drive capability in a third period (see figure 8, where the gate current t1 > t2 and t3 > t1) .
Regarding claim 2, Nomura teaches, the gate driver circuit of claim 1, wherein the third drive capability is higher than the first drive capability (see figure 8, where the gate current in t3 > t1) .
Regarding claim 3, Nomura teaches, the gate driver circuit of claim 1, wherein the plurality of transistors include at least one transistor assigned to a first transistor group and at least one transistor assigned to a second transistor group, and wherein the control circuit fixes the at least one transistor assigned to the second transistor group to an off state during the second period, without changing the on/off state of the at least one transistor assigned to the first transistor group from the first period to the third period (see the transistor groups sw1-sw-3 to sw4-5, figure 4 and 8).
Regarding claim 8, Nomura teaches, the gate driver circuit of claim 1, further comprising a second sensor configured to compare an output voltage of the switching circuit with a second threshold voltage, wherein the control circuit performs a transition to the third period in response to a change in an output of the second sensor during the second period (see monitor circuit 21, figure 4 and figure 8 for the transitions of between the 2nd to 3rd period based on the voltage detection from the monitor circuit).
Regarding claim 11, Nomura teaches, A motor drive device comprising: a bridge circuit including a high-side transistor and a low-side transistor (see bridge circuit 110, figure 4) ; side driver which is the gate driver circuit of claim 1 configured to drive the high-side transistor as the power transistor (gate drive circuit 20-1, figure 4) ; and a low-side driver which is the gate driver circuit configured to drive the low-side transistor as the power transistor( gate drive circuit 20-2, figure 4.
Regarding claim 12, Nomura teaches, an electronic device comprising: a motor ; and the motor drive device of claim 11 configured to drive the motor (see rejection of claim 1 and 11 above and paragraph 55, where the load is a motor).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Nomura US publication no.: US 2018/0062633 A1 in view of Georgescu et al. US publication no.: US 2024/0212781 A1.
Regarding claim 5, Nomura is silent on specifically teaching, the gate driver circuit of claim 1, wherein the plurality of transistors have a same size.
However, Geogescu et al. is in the same field of art and teach: wherein the plurality of transistors have a same size (see paragraph 55).
In view of Georgescu et al.’s teachings, it would’ve been obvious to one with the ordinary skills in the art, before the effective filing date of the invention, with the apparatus as taught by Nomura to include; wherein the plurality of transistors have a same size, for the purpose of providing a design variant.
Regarding claim 6, Nomura is silent on specifically teaching, the gate driver circuit of claim 1, wherein the plurality of transistors have binary weighted sizes.
However, Geogescu et al. is in the same field of art and teach: wherein the plurality of transistors have binary weighted sizes (see paragraph 55).
In view of Georgescu et al.’s teachings, it would’ve been obvious to one with the ordinary skills in the art, before the effective filing date of the invention, with the apparatus as taught by Nomura to include; wherein the plurality of transistors have a same size, for the purpose of providing a design variant.
Regarding claim 10, Nomura is silent on specifically teaching, the gate driver circuit of claim 1, which is integrated on a single semiconductor substrate.
However, Geogescu et al. is in the same field of art and teach: which is integrated on a single semiconductor substrate (see paragraph 55).
In view of Georgescu et al.’s teachings, it would’ve been obvious to one with the ordinary skills in the art, before the effective filing date of the invention, with the apparatus as taught by Nomura to include; which is integrated on a single semiconductor substrate, for the purpose of providing a design variant.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Nomura US publication no.: US 2018/0062633 A1 in view of Kaufmann et al. US publication no.: US 2024/0113611 A1.
Regarding claim 7, Nomura is silent on specifically teaching, the gate driver circuit of claim 1, further comprising a first sensor configured to compare a gate-source voltage of the power transistor with a first threshold voltage, wherein the control circuit performs a transition to the second period in response to a change in an output of the first sensor during the first period.
However, Geogescu et al. is in the same field of art and teach: further comprising a first sensor configured to compare a gate-source voltage of the power transistor with a first threshold voltage, wherein the control circuit performs a transition to the second period in response to a change in an output of the first sensor during the first period (see paragraph 58 and figures 1 and 16, where the transistors are controlled based on the gate voltage detection).
In view of Georgescu et al.’s teachings, it would’ve been obvious to one with the ordinary skills in the art, before the effective filing date of the invention, with the apparatus as taught by Nomura to include; further comprising a first sensor configured to compare a gate-source voltage of the power transistor with a first threshold voltage, wherein the control circuit performs a transition to the second period in response to a change in an output of the first sensor during the first period, for the purpose of improving the switching controls.
Allowable Subject Matter
Claim 4 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ZOHEB S IMTIAZ/Primary Examiner , Art Unit 2837
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