Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to Applicant' s communication filed 7/21/2026 in response to the Office action dated 4/21/2026. Claims 1-2, 7-9, 14-16, and 20 have been amended. Claims 1-2, 4-9, 11-16, and 18-20 are pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-9, 13-16 and 20 are rejected under 35 U.S.C 103 as being unpatentable over Agrawal et al. (US 20220405253 A1), hereinafter Agrawal, in view of Kawamura et al. (US 20180067850 A1), hereinafter Kawamura, further in view of Bailey (US 20040243612 A1), and Ranganathan et al. (US 20230032586 A1), hereinafter Ranganathan.
Regarding claim 1, Agrawal teaches a system comprising: a plurality of memory devices (Paragraph 70; Fig. 1, system 1 includes a source system 100S containing source storage 200 and a target system 100T containing target storage 300);
and a processing device, operatively coupled with the plurality of memory devices (Paragraph 80; Fig. 1, source server 100a of source system 100S and target server 100c of target system 100T are managed by central processing units), to perform operations comprising:
in response to a host command to track migration of a namespace (Paragraph 76, server request [host command] to copy [migrate] data),
allocating a subset of the physical pages to each bitmap of a set of bitmaps for the namespace (Paragraphs 71, 82, 85; Fig. 2, creating bitmaps M1 and M2 which map [allocate] logical pages (which correspond to physical locations [physical pages]) within a namespace).
Agrawal does not explicitly teach dividing a memory device of the plurality of memory devices into a plurality of physical pages, wherein each physical page of the plurality of physical pages is a first predetermined page size; allocating memory of the memory device for a set of bitmaps; and dividing each bitmap of the set of bitmaps into a plurality of logical pages, wherein each logical page of the plurality of logical pages has a second predetermined page size and includes a subset of bits of the bitmap, wherein each bit of the subset of bits corresponds to a respective memory page in the namespace, wherein the first predetermined page size is equal to the second predetermined page size, wherein the subset of bits of the bitmap for each logical page of the plurality of logical pages of each bitmap is stored at a corresponding physical page of the subset of physical pages, wherein the subset of physical pages are non-contiguous in the memory device.
However, Kawamura teaches dividing a memory device of the plurality of memory devices into a plurality of physical pages (Paragraphs 73-74; Fig. 4, memory is composed of physical blocks 404 which include one or more physical pages 405),
wherein each physical page of the plurality of physical pages has a first predetermined page size (Paragraph 79; Fig. 5, a size of the physical page 504 is fixed [predetermined]),
each logical page of the plurality of logical pages has a second predetermined page size (Paragraph 79; Fig. 5, a size of the logical page 502 is fixed [predetermined]), and
wherein the first predetermined page size is equal to the second predetermined page size (Paragraph 79; Fig. 5, the physical page 504 size [first size] and the logical page 502 size [second size] are equal)
Agrawal and Kawamura are analogous art because they are in the same field of endeavor, that being data migration. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Agrawal to further include the physical and logical pages and the predetermined, equal page sizes according to the teachings of Kawamura. The motivation for doing so would have been to construct a simple and efficient storage system by dividing the memory into fixed length logical portions and mapping the portions onto physical portions (Kawamura, Paragraph 9).
Agrawal in view of Kawamura does not explicitly teach allocating memory of the memory device for a set of bitmaps; and dividing each bitmap of the set of bitmaps into a plurality of logical pages, wherein each logical page of the plurality of logical pages includes a subset of bits of the bitmap, wherein each bit of the subset of bits corresponds to a respective memory page in the namespace, wherein the subset of bits of the bitmap for each logical page of the plurality of logical pages of each bitmap is stored at a corresponding physical page of the subset of physical pages, wherein the subset of physical pages are non-contiguous in the memory device.
However, Bailey teaches allocating memory of the memory device for a set of bitmaps (Paragraphs 18, 33; Fig. 1, storing [allocating] a logical ID allocation bitmap into a database file in memory); and
dividing each bitmap of the set of bitmaps into a plurality of logical pages (Paragraphs 30, 33; Fig. 5, storing [dividing] the logical ID allocation bitmap into a set of pages, wherein each page is identified by a logical ID 54 [logical page] in mapping table 500),
wherein each logical page of the plurality of logical pages includes a subset of bits of the bitmap (Paragraphs 33-34, storing the logical ID allocation bitmap into a set of pages, wherein the bitmap may be a size of 131,072 bytes [bits of the bitmap] and each page storing the bitmap can contain 4,096 of those bytes [subset of bits of the bitmap]),
wherein each bit of the subset of bits corresponds to a respective memory page in the namespace (Paragraphs 30, 32; Fig. 5, each bit of the logical ID allocation bitmap corresponds to a page entry in mapping table 500, wherein each page entry maps to a physical page address 56 of a respective memory page),
wherein the subset of bits of the bitmap for each logical page of the plurality of logical pages of each bitmap is stored at a corresponding physical page of the subset of physical pages (Paragraphs 30, 32, 34; Fig. 5, each [logical] page (corresponding to a logical ID 54) can store 4,096 bytes of the logical ID allocation bitmap [subset of bits of the bitmap], wherein each [logical] page is stored at a corresponding physical memory page at physical page address 56).
The Examiner notes that Agrawal teaches the set of bitmaps (Agrawal, Paragraphs 82, 85; Fig. 2, bitmaps M1 and M2) and the namespace (Agrawal, Paragraph 82, namespace) while Bailey teaches the remaining limitations above.
Agrawal, Kawamura, and Bailey are analogous art because they are in the same field of endeavor, that being storage allocation management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Agrawal in view of Kawamura to further include the logical ID allocation bitmap according to the teachings of Bailey. The motivation for doing so would have been to improve concurrency (Bailey, Paragraph 34).
Agrawal in view of Kawamura, further in view of Bailey does not explicitly teach wherein the subset of physical pages are non-contiguous in the memory device.
However, Ranganathan teaches wherein the subset of physical pages are non-contiguous in the memory device (Paragraph 30; Fig. 1, bitmap virtual pages are mapped to non-contiguous physical pages in memory).
Agrawal, Kawamura, Bailey, and Ranganathan are analogous art because they are in the same field of endeavor, that being storage allocation management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Agrawal in view of Kawamura, further in view of Bailey to further include the non-contiguous mapping of physical pages according to the teachings of Ranganathan. The motivation for doing so would have been to avoid difficulty in finding a contiguous physical memory space in fragmented memory and to conserve memory (Ranganathan, Paragraphs 37-38).
Regarding claim 2, Agrawal in view of Kawamura, further in view of Bailey and Ranganathan teaches the system of claim 1, wherein allocating a subset of the physical pages to each bitmap of a set of bitmaps for the namespace comprises: identifying, for the plurality of logical pages, the subset of the physical pages for the respective bitmap (Agrawal, Paragraphs 71, 82, bitmaps contain LBAs which are associated with physical storage locations);
mapping each logical page of the plurality of logical pages to a physical address of a physical page of the subset of the physical pages for the respective bitmap (Kawamura, Paragraph 81; Fig. 6, logical pages correspond [map] to physical addresses 603 of [physical] pages).
Regarding claim 6, Agrawal in view of Kawamura, further in view of Bailey and Ranganathan teaches the system of claim 1, wherein a first bitmap of the set of bitmaps tracks memory pages copied from a source namespace to a destination namespace (Agrawal, Paragraphs 82-83; Figs. 1 and 2, bitmap of mapped pages BMP (M1) tracks whether a given LBA (page) is to be copied to target storage 300),
a second bitmap of the set of bitmaps tracks memory pages modified at the source namespace during migration (Agrawal, Paragraphs 85, 97; Figs. 1 and 2, active bitmap of dirty pages BDP (M2) tracks updates to locations [pages] of source storage 200 that occur during a live migration operation),
and a third bitmap of the set of bitmaps tracks memory pages modified at the source namespace during migration when the second bitmap is unavailable for tracking memory pages (Agrawal, Paragraphs 97-99; Fig. 3, second bitmap of dirty pages BDP may act as a replacement active buffer to track updates to modified locations [pages] while the first BDP bitmap is being used as a passive buffer [unavailable for tracking pages]).
Regarding claim 7, Agrawal in view of Kawamura, further in view of Bailey and Ranganathan teaches the system of claim 2, wherein mapping each logical page of the plurality of logical pages to the physical address of the physical page of the subset of the physical pages for the respective bitmap comprises: for each logical page of the plurality of logical pages, appending, to an array of pointers, an entry containing a physical address of a physical page of the plurality of physical pages (Kawamura, Paragraph 81; Fig. 6, each logical page in the translation table 601 [array of pointers] corresponds to a physical address 603 of a (physical) page),
wherein the entry is indexed by a logical page number of a respective logical page (Kawamura, Paragraph 81; Fig. 6, logical page number 602).
Regarding claims 8-9 and 13-14, these are method versions of the claimed system discussed above (claims 1-2 and 6-7, respectively), wherein all claim limitations have also been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Agrawal in view of Kawamura, further in view of Bailey and Ranganathan.
Regarding claims 15-16 and 20, these are non-transitory computer-readable storage medium versions of the claimed system discussed above (claims 1-2 and 7, respectively), wherein Agrawal in view of Kawamura, further in view of Bailey and Ranganathan also teaches a non-transitory computer-readable storage medium comprising instructions executed by a processing device (Agrawal, Paragraph 47, processor executing computer program instructions stored within non-transitory computer readable media).
The remaining claim limitations have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Agrawal in view of Kawamura, further in view of Bailey and Ranganathan.
Claims 4-5, 11-12, and 18-19 are rejected under 35 U.S.C 103 as being unpatentable over Agrawal in view of Kawamura, further in view of Bailey and Ranganathan as applied to claims 1-2, 8-9, and 15-16 above, and further in view of Tsirkin et al. (US 20180060100 A1), hereinafter Tsirkin.
Regarding claim 4, Agrawal in view of Kawamura, further in view of Bailey and Ranganathan teaches the system of claim 2, but does not explicitly teach wherein identifying, for the plurality of logical pages, the subset of the physical pages for the respective bitmap comprises: determining a number of logical pages in the plurality of logical pages; and selecting, from a free physical page data structure, the subset of physical pages based on the number of logical pages in the plurality of logical pages, wherein the free physical page data structure includes one or more physical pages of the plurality of physical pages designated as available for allocation.
However, Tsirkin teaches wherein identifying, for the plurality of logical pages, the subset of the physical pages for the respective bitmap comprises: determining a number of logical pages in the plurality of logical pages (Paragraph 29; Fig. 1, guest page tables 126 and host page tables 124 provide ranges [numbers] of virtual memory addresses (logical pages) mapped to physical addresses); and
selecting, from a free physical page data structure, the subset of physical pages based on the number of logical pages in the plurality of logical pages (Paragraphs 34, 51; Figs. 1 and 2, step 212, modifying [selecting] free memory pages identified by a free page bitmap 130 [data structure] to be included in the migration),
wherein the free physical page data structure includes one or more physical pages of the plurality of physical pages designated as available for allocation (Paragraph 34; Fig. 1, free bitmap 130 indicates [includes] free memory pages that are available for allocation).
Agrawal, Kawamura, Bailey, Ranganathan, and Tsirkin are analogous art because they are in the same field of endeavor, that being storage allocation management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Agrawal in view of Kawamura, further in view of Bailey and Ranganathan to further include the free page data structure according to the teachings of Tsirkin. The motivation for doing so would have been to improve migration by identifying free memory pages (Tsirkin, Paragraph 14).
Regarding claim 5, Agrawal in view of Kawamura, further in view of Bailey, Ranganathan, and Tsirkin teaches the system of claim 1, wherein the processing device is to perform operations further comprising: in response to allocating the subset of the physical pages to a respective bitmap, removing, from a free physical page data structure, the subset of the physical pages (Tsirkin, Paragraph 34; Fig. 1, updating [removing pages from] free bitmap 130 in response to memory pages being allocated);
and including, in a used physical page data structure, the subset of the physical pages, wherein the used physical page data structure includes one or more physical pages of the plurality of physical pages designated as unavailable for allocation (Tsirkin, Paragraphs 32, 35; Fig. 1, dirty bitmap 132 [used page data structure] indicates [includes] dirty memory pages that have been allocated [are unavailable for allocation]).
Regarding claims 11-12, these are method versions of the claimed system discussed above (claims 4-5, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Agrawal in view of Kawamura, further in view of Bailey, Ranganathan, and Tsirkin.
Regarding claims 18-19, these are non-transitory computer-readable storage medium versions of the claimed system discussed above (claims 4-5, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Agrawal in view of Kawamura, further in view of Bailey, Ranganathan, and Tsirkin.
Response to Arguments
Applicant’s arguments (see page 9 of the remarks) filed 7/21/2026, with respect to the rejections of claim 14 under 35 U.S.C 112 have been fully considered and are persuasive. Therefore, the rejection of claim 14 under 35 U.S.C 112 has been withdrawn.
Applicant’s arguments (see pages 9-11 of the remarks) filed 7/21/2026, with respect to the rejections of claims 1-2, 4-9, 11-16, and 18-20 under 35 U.S.C 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Agrawal, Kawamura, Bailey, Tsirkin, and Ranganathan.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Pinga whose telephone number is (571) 272-2620. The examiner can normally be reached on M-F 8:30am-6pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla, can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/J.M.P./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
